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      1 /*	$NetBSD: intel_mocs.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2015 Intel Corporation
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  */
     25 
     26 #ifndef INTEL_MOCS_H
     27 #define INTEL_MOCS_H
     28 
     29 /**
     30  * DOC: Memory Objects Control State (MOCS)
     31  *
     32  * Motivation:
     33  * In previous Gens the MOCS settings was a value that was set by user land as
     34  * part of the batch. In Gen9 this has changed to be a single table (per ring)
     35  * that all batches now reference by index instead of programming the MOCS
     36  * directly.
     37  *
     38  * The one wrinkle in this is that only PART of the MOCS tables are included
     39  * in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32
     40  * registers). The rest are not (the settings for the other rings).
     41  *
     42  * This table needs to be set at system start-up because the way the table
     43  * interacts with the contexts and the GmmLib interface.
     44  *
     45  *
     46  * Implementation:
     47  *
     48  * The tables (one per supported platform) are defined in intel_mocs.c
     49  * and are programmed in the first batch after the context is loaded
     50  * (with the hardware workarounds). This will then let the usual
     51  * context handling keep the MOCS in step.
     52  */
     53 
     54 struct intel_engine_cs;
     55 struct intel_gt;
     56 
     57 void intel_mocs_init(struct intel_gt *gt);
     58 void intel_mocs_init_engine(struct intel_engine_cs *engine);
     59 
     60 #endif
     61