1 1.1 riastrad /* $NetBSD: cl0002.h,v 1.2 2021/12/18 23:45:33 riastradh Exp $ */ 2 1.1 riastrad 3 1.1 riastrad /* SPDX-License-Identifier: MIT */ 4 1.1 riastrad #ifndef __NVIF_CL0002_H__ 5 1.1 riastrad #define __NVIF_CL0002_H__ 6 1.1 riastrad 7 1.1 riastrad struct nv_dma_v0 { 8 1.1 riastrad __u8 version; 9 1.1 riastrad #define NV_DMA_V0_TARGET_VM 0x00 10 1.1 riastrad #define NV_DMA_V0_TARGET_VRAM 0x01 11 1.1 riastrad #define NV_DMA_V0_TARGET_PCI 0x02 12 1.1 riastrad #define NV_DMA_V0_TARGET_PCI_US 0x03 13 1.1 riastrad #define NV_DMA_V0_TARGET_AGP 0x04 14 1.1 riastrad __u8 target; 15 1.1 riastrad #define NV_DMA_V0_ACCESS_VM 0x00 16 1.1 riastrad #define NV_DMA_V0_ACCESS_RD 0x01 17 1.1 riastrad #define NV_DMA_V0_ACCESS_WR 0x02 18 1.1 riastrad #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 19 1.1 riastrad __u8 access; 20 1.1 riastrad __u8 pad03[5]; 21 1.1 riastrad __u64 start; 22 1.1 riastrad __u64 limit; 23 1.1 riastrad /* ... chipset-specific class data */ 24 1.1 riastrad }; 25 1.1 riastrad 26 1.1 riastrad struct nv50_dma_v0 { 27 1.1 riastrad __u8 version; 28 1.1 riastrad #define NV50_DMA_V0_PRIV_VM 0x00 29 1.1 riastrad #define NV50_DMA_V0_PRIV_US 0x01 30 1.1 riastrad #define NV50_DMA_V0_PRIV__S 0x02 31 1.1 riastrad __u8 priv; 32 1.1 riastrad #define NV50_DMA_V0_PART_VM 0x00 33 1.1 riastrad #define NV50_DMA_V0_PART_256 0x01 34 1.1 riastrad #define NV50_DMA_V0_PART_1KB 0x02 35 1.1 riastrad __u8 part; 36 1.1 riastrad #define NV50_DMA_V0_COMP_NONE 0x00 37 1.1 riastrad #define NV50_DMA_V0_COMP_1 0x01 38 1.1 riastrad #define NV50_DMA_V0_COMP_2 0x02 39 1.1 riastrad #define NV50_DMA_V0_COMP_VM 0x03 40 1.1 riastrad __u8 comp; 41 1.1 riastrad #define NV50_DMA_V0_KIND_PITCH 0x00 42 1.1 riastrad #define NV50_DMA_V0_KIND_VM 0x7f 43 1.1 riastrad __u8 kind; 44 1.1 riastrad __u8 pad05[3]; 45 1.1 riastrad }; 46 1.1 riastrad 47 1.1 riastrad struct gf100_dma_v0 { 48 1.1 riastrad __u8 version; 49 1.1 riastrad #define GF100_DMA_V0_PRIV_VM 0x00 50 1.1 riastrad #define GF100_DMA_V0_PRIV_US 0x01 51 1.1 riastrad #define GF100_DMA_V0_PRIV__S 0x02 52 1.1 riastrad __u8 priv; 53 1.1 riastrad #define GF100_DMA_V0_KIND_PITCH 0x00 54 1.1 riastrad #define GF100_DMA_V0_KIND_VM 0xff 55 1.1 riastrad __u8 kind; 56 1.1 riastrad __u8 pad03[5]; 57 1.1 riastrad }; 58 1.1 riastrad 59 1.1 riastrad struct gf119_dma_v0 { 60 1.1 riastrad __u8 version; 61 1.1 riastrad #define GF119_DMA_V0_PAGE_LP 0x00 62 1.1 riastrad #define GF119_DMA_V0_PAGE_SP 0x01 63 1.1 riastrad __u8 page; 64 1.1 riastrad #define GF119_DMA_V0_KIND_PITCH 0x00 65 1.1 riastrad #define GF119_DMA_V0_KIND_VM 0xff 66 1.1 riastrad __u8 kind; 67 1.1 riastrad __u8 pad03[5]; 68 1.1 riastrad }; 69 1.1 riastrad #endif 70
Indexes created Wed Oct 01 07:09:59 GMT 2025