1 /* $NetBSD: cl0002.h,v 1.2 2021/12/18 23:45:33 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 #ifndef __NVIF_CL0002_H__ 5 #define __NVIF_CL0002_H__ 6 7 struct nv_dma_v0 { 8 __u8 version; 9 #define NV_DMA_V0_TARGET_VM 0x00 10 #define NV_DMA_V0_TARGET_VRAM 0x01 11 #define NV_DMA_V0_TARGET_PCI 0x02 12 #define NV_DMA_V0_TARGET_PCI_US 0x03 13 #define NV_DMA_V0_TARGET_AGP 0x04 14 __u8 target; 15 #define NV_DMA_V0_ACCESS_VM 0x00 16 #define NV_DMA_V0_ACCESS_RD 0x01 17 #define NV_DMA_V0_ACCESS_WR 0x02 18 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 19 __u8 access; 20 __u8 pad03[5]; 21 __u64 start; 22 __u64 limit; 23 /* ... chipset-specific class data */ 24 }; 25 26 struct nv50_dma_v0 { 27 __u8 version; 28 #define NV50_DMA_V0_PRIV_VM 0x00 29 #define NV50_DMA_V0_PRIV_US 0x01 30 #define NV50_DMA_V0_PRIV__S 0x02 31 __u8 priv; 32 #define NV50_DMA_V0_PART_VM 0x00 33 #define NV50_DMA_V0_PART_256 0x01 34 #define NV50_DMA_V0_PART_1KB 0x02 35 __u8 part; 36 #define NV50_DMA_V0_COMP_NONE 0x00 37 #define NV50_DMA_V0_COMP_1 0x01 38 #define NV50_DMA_V0_COMP_2 0x02 39 #define NV50_DMA_V0_COMP_VM 0x03 40 __u8 comp; 41 #define NV50_DMA_V0_KIND_PITCH 0x00 42 #define NV50_DMA_V0_KIND_VM 0x7f 43 __u8 kind; 44 __u8 pad05[3]; 45 }; 46 47 struct gf100_dma_v0 { 48 __u8 version; 49 #define GF100_DMA_V0_PRIV_VM 0x00 50 #define GF100_DMA_V0_PRIV_US 0x01 51 #define GF100_DMA_V0_PRIV__S 0x02 52 __u8 priv; 53 #define GF100_DMA_V0_KIND_PITCH 0x00 54 #define GF100_DMA_V0_KIND_VM 0xff 55 __u8 kind; 56 __u8 pad03[5]; 57 }; 58 59 struct gf119_dma_v0 { 60 __u8 version; 61 #define GF119_DMA_V0_PAGE_LP 0x00 62 #define GF119_DMA_V0_PAGE_SP 0x01 63 __u8 page; 64 #define GF119_DMA_V0_KIND_PITCH 0x00 65 #define GF119_DMA_V0_KIND_VM 0xff 66 __u8 kind; 67 __u8 pad03[5]; 68 }; 69 #endif 70
Indexes created Sat Sep 20 22:09:52 GMT 2025