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      1 /*	$NetBSD: atom-names.h,v 1.4 2021/12/18 23:45:42 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2008 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Author: Stanislaw Skowronek
     25  */
     26 
     27 #ifndef ATOM_NAMES_H
     28 #define ATOM_NAMES_H
     29 
     30 #include "atom.h"
     31 
     32 #ifdef ATOM_DEBUG
     33 
     34 #define ATOM_OP_NAMES_CNT 123
     35 static const char *atom_op_names[ATOM_OP_NAMES_CNT] = {
     36 "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
     37 "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
     38 "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
     39 "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
     40 "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
     41 "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
     42 "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
     43 "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
     44 "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
     45 "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
     46 "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
     47 "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
     48 "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
     49 "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
     50 "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
     51 "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
     52 "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
     53 "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
     54 "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
     55 "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
     56 "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
     57 "DEBUG", "CTB_DS",
     58 };
     59 
     60 #define ATOM_TABLE_NAMES_CNT 74
     61 static const char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
     62 "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
     63 "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
     64 "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
     65 "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
     66 "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
     67 "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
     68 "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
     69 "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
     70 "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
     71 "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
     72 "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
     73 "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
     74 "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
     75 "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
     76 "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
     77 "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
     78 "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
     79 "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
     80 "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
     81 "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
     82 "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
     83 "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
     84 "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
     85 "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
     86 "MemoryDeviceInit", "EnableYUV",
     87 };
     88 
     89 #define ATOM_IO_NAMES_CNT 5
     90 static const char *atom_io_names[ATOM_IO_NAMES_CNT] = {
     91 "MM", "PLL", "MC", "PCIE", "PCIE PORT",
     92 };
     93 
     94 #else
     95 
     96 #define ATOM_OP_NAMES_CNT 0
     97 #define ATOM_TABLE_NAMES_CNT 0
     98 #define ATOM_IO_NAMES_CNT 0
     99 
    100 #endif
    101 
    102 #endif
    103