1 /* $NetBSD: cik_reg.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef __CIK_REG_H__ 27 #define __CIK_REG_H__ 28 29 #define CIK_DIDT_IND_INDEX 0xca00 30 #define CIK_DIDT_IND_DATA 0xca04 31 32 #define CIK_DC_GPIO_HPD_MASK 0x65b0 33 #define CIK_DC_GPIO_HPD_A 0x65b4 34 #define CIK_DC_GPIO_HPD_EN 0x65b8 35 #define CIK_DC_GPIO_HPD_Y 0x65bc 36 37 #define CIK_GRPH_CONTROL 0x6804 38 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0) 39 # define CIK_GRPH_DEPTH_8BPP 0 40 # define CIK_GRPH_DEPTH_16BPP 1 41 # define CIK_GRPH_DEPTH_32BPP 2 42 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 43 # define CIK_ADDR_SURF_2_BANK 0 44 # define CIK_ADDR_SURF_4_BANK 1 45 # define CIK_ADDR_SURF_8_BANK 2 46 # define CIK_ADDR_SURF_16_BANK 3 47 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4) 48 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 49 # define CIK_ADDR_SURF_BANK_WIDTH_1 0 50 # define CIK_ADDR_SURF_BANK_WIDTH_2 1 51 # define CIK_ADDR_SURF_BANK_WIDTH_4 2 52 # define CIK_ADDR_SURF_BANK_WIDTH_8 3 53 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8) 54 /* 8 BPP */ 55 # define CIK_GRPH_FORMAT_INDEXED 0 56 /* 16 BPP */ 57 # define CIK_GRPH_FORMAT_ARGB1555 0 58 # define CIK_GRPH_FORMAT_ARGB565 1 59 # define CIK_GRPH_FORMAT_ARGB4444 2 60 # define CIK_GRPH_FORMAT_AI88 3 61 # define CIK_GRPH_FORMAT_MONO16 4 62 # define CIK_GRPH_FORMAT_BGRA5551 5 63 /* 32 BPP */ 64 # define CIK_GRPH_FORMAT_ARGB8888 0 65 # define CIK_GRPH_FORMAT_ARGB2101010 1 66 # define CIK_GRPH_FORMAT_32BPP_DIG 2 67 # define CIK_GRPH_FORMAT_8B_ARGB2101010 3 68 # define CIK_GRPH_FORMAT_BGRA1010102 4 69 # define CIK_GRPH_FORMAT_8B_BGRA1010102 5 70 # define CIK_GRPH_FORMAT_RGB111110 6 71 # define CIK_GRPH_FORMAT_BGR101111 7 72 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 73 # define CIK_ADDR_SURF_BANK_HEIGHT_1 0 74 # define CIK_ADDR_SURF_BANK_HEIGHT_2 1 75 # define CIK_ADDR_SURF_BANK_HEIGHT_4 2 76 # define CIK_ADDR_SURF_BANK_HEIGHT_8 3 77 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 78 # define CIK_ADDR_SURF_TILE_SPLIT_64B 0 79 # define CIK_ADDR_SURF_TILE_SPLIT_128B 1 80 # define CIK_ADDR_SURF_TILE_SPLIT_256B 2 81 # define CIK_ADDR_SURF_TILE_SPLIT_512B 3 82 # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4 83 # define CIK_ADDR_SURF_TILE_SPLIT_2KB 5 84 # define CIK_ADDR_SURF_TILE_SPLIT_4KB 6 85 # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 86 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0 87 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1 88 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2 89 # define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3 90 # define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 91 # define CIK_GRPH_ARRAY_LINEAR_GENERAL 0 92 # define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1 93 # define CIK_GRPH_ARRAY_1D_TILED_THIN1 2 94 # define CIK_GRPH_ARRAY_2D_TILED_THIN1 4 95 # define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) 96 # define CIK_ADDR_SURF_P2 0 97 # define CIK_ADDR_SURF_P4_8x16 4 98 # define CIK_ADDR_SURF_P4_16x16 5 99 # define CIK_ADDR_SURF_P4_16x32 6 100 # define CIK_ADDR_SURF_P4_32x32 7 101 # define CIK_ADDR_SURF_P8_16x16_8x16 8 102 # define CIK_ADDR_SURF_P8_16x32_8x16 9 103 # define CIK_ADDR_SURF_P8_32x32_8x16 10 104 # define CIK_ADDR_SURF_P8_16x32_16x16 11 105 # define CIK_ADDR_SURF_P8_32x32_16x16 12 106 # define CIK_ADDR_SURF_P8_32x32_16x32 13 107 # define CIK_ADDR_SURF_P8_32x64_32x32 14 108 # define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29) 109 # define CIK_DISPLAY_MICRO_TILING 0 110 # define CIK_THIN_MICRO_TILING 1 111 # define CIK_DEPTH_MICRO_TILING 2 112 # define CIK_ROTATED_MICRO_TILING 4 113 114 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 115 #define CIK_CUR_CONTROL 0x6998 116 # define CIK_CURSOR_EN (1 << 0) 117 # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8) 118 # define CIK_CURSOR_MONO 0 119 # define CIK_CURSOR_24_1 1 120 # define CIK_CURSOR_24_8_PRE_MULT 2 121 # define CIK_CURSOR_24_8_UNPRE_MULT 3 122 # define CIK_CURSOR_2X_MAGNIFY (1 << 16) 123 # define CIK_CURSOR_FORCE_MC_ON (1 << 20) 124 # define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 125 # define CIK_CURSOR_URGENT_ALWAYS 0 126 # define CIK_CURSOR_URGENT_1_8 1 127 # define CIK_CURSOR_URGENT_1_4 2 128 # define CIK_CURSOR_URGENT_3_8 3 129 # define CIK_CURSOR_URGENT_1_2 4 130 #define CIK_CUR_SURFACE_ADDRESS 0x699c 131 # define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000 132 #define CIK_CUR_SIZE 0x69a0 133 #define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4 134 #define CIK_CUR_POSITION 0x69a8 135 #define CIK_CUR_HOT_SPOT 0x69ac 136 #define CIK_CUR_COLOR1 0x69b0 137 #define CIK_CUR_COLOR2 0x69b4 138 #define CIK_CUR_UPDATE 0x69b8 139 # define CIK_CURSOR_UPDATE_PENDING (1 << 0) 140 # define CIK_CURSOR_UPDATE_TAKEN (1 << 1) 141 # define CIK_CURSOR_UPDATE_LOCK (1 << 16) 142 # define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 143 144 #define CIK_ALPHA_CONTROL 0x6af0 145 # define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1) 146 147 #define CIK_LB_DATA_FORMAT 0x6b00 148 # define CIK_INTERLEAVE_EN (1 << 3) 149 150 #define CIK_LB_DESKTOP_HEIGHT 0x6b0c 151 152 #define SQ_IND_INDEX 0x8DE0 153 #define SQ_CMD 0x8DEC 154 #define SQ_IND_DATA 0x8DE4 155 156 /* 157 * The TCP_WATCHx_xxxx addresses that are shown here are in dwords, 158 * and that's why they are multiplied by 4 159 */ 160 #define TCP_WATCH0_ADDR_H (0x32A0*4) 161 #define TCP_WATCH1_ADDR_H (0x32A3*4) 162 #define TCP_WATCH2_ADDR_H (0x32A6*4) 163 #define TCP_WATCH3_ADDR_H (0x32A9*4) 164 #define TCP_WATCH0_ADDR_L (0x32A1*4) 165 #define TCP_WATCH1_ADDR_L (0x32A4*4) 166 #define TCP_WATCH2_ADDR_L (0x32A7*4) 167 #define TCP_WATCH3_ADDR_L (0x32AA*4) 168 #define TCP_WATCH0_CNTL (0x32A2*4) 169 #define TCP_WATCH1_CNTL (0x32A5*4) 170 #define TCP_WATCH2_CNTL (0x32A8*4) 171 #define TCP_WATCH3_CNTL (0x32AB*4) 172 173 #define CPC_INT_CNTL 0xC2D0 174 175 #define CP_HQD_IQ_RPTR 0xC970u 176 #define SDMA0_RLC0_RB_CNTL 0xD400u 177 #define SDMA_RB_VMID(x) (x << 24) 178 #define SDMA0_RLC0_RB_BASE 0xD404u 179 #define SDMA0_RLC0_RB_BASE_HI 0xD408u 180 #define SDMA0_RLC0_RB_RPTR 0xD40Cu 181 #define SDMA0_RLC0_RB_WPTR 0xD410u 182 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL 0xD414u 183 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0xD418u 184 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0xD41Cu 185 #define SDMA0_RLC0_RB_RPTR_ADDR_HI 0xD420u 186 #define SDMA0_RLC0_RB_RPTR_ADDR_LO 0xD424u 187 #define SDMA0_RLC0_IB_CNTL 0xD428u 188 #define SDMA0_RLC0_IB_RPTR 0xD42Cu 189 #define SDMA0_RLC0_IB_OFFSET 0xD430u 190 #define SDMA0_RLC0_IB_BASE_LO 0xD434u 191 #define SDMA0_RLC0_IB_BASE_HI 0xD438u 192 #define SDMA0_RLC0_IB_SIZE 0xD43Cu 193 #define SDMA0_RLC0_SKIP_CNTL 0xD440u 194 #define SDMA0_RLC0_CONTEXT_STATUS 0xD444u 195 #define SDMA_RLC_IDLE (1 << 2) 196 #define SDMA0_RLC0_DOORBELL 0xD448u 197 #define SDMA_OFFSET(x) (x << 0) 198 #define SDMA_DB_ENABLE (1 << 28) 199 #define SDMA0_RLC0_VIRTUAL_ADDR 0xD49Cu 200 #define SDMA_ATC (1 << 0) 201 #define SDMA_VA_PTR32 (1 << 4) 202 #define SDMA_VA_SHARED_BASE(x) (x << 8) 203 #define SDMA0_RLC0_APE1_CNTL 0xD4A0u 204 #define SDMA0_RLC0_DOORBELL_LOG 0xD4A4u 205 #define SDMA0_RLC0_WATERMARK 0xD4A8u 206 #define SDMA0_CNTL 0xD010 207 #define SDMA1_CNTL 0xD810 208 209 enum { 210 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 211 MAX_WATCH_ADDRESSES = 4 212 }; 213 214 enum { 215 ADDRESS_WATCH_REG_ADDR_HI = 0, 216 ADDRESS_WATCH_REG_ADDR_LO, 217 ADDRESS_WATCH_REG_CNTL, 218 ADDRESS_WATCH_REG_MAX 219 }; 220 221 enum { /* not defined in the CI/KV reg file */ 222 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 223 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 224 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 225 /* extend the mask to 26 bits in order to match the low address field */ 226 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 227 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 228 }; 229 230 union TCP_WATCH_CNTL_BITS { 231 struct { 232 uint32_t mask:24; 233 uint32_t vmid:4; 234 uint32_t atc:1; 235 uint32_t mode:2; 236 uint32_t valid:1; 237 } bitfields, bits; 238 uint32_t u32All; 239 signed int i32All; 240 float f32All; 241 }; 242 243 #endif 244
Indexes created Sat Sep 20 22:09:52 GMT 2025