1 /* $NetBSD: r100d.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __R100D_H__ 31 #define __R100D_H__ 32 33 #define CP_PACKET0 0x00000000 34 #define PACKET0_BASE_INDEX_SHIFT 0 35 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 36 #define PACKET0_COUNT_SHIFT 16 37 #define PACKET0_COUNT_MASK (0x3fff << 16) 38 #define CP_PACKET1 0x40000000 39 #define CP_PACKET2 0x80000000 40 #define PACKET2_PAD_SHIFT 0 41 #define PACKET2_PAD_MASK (0x3fffffff << 0) 42 #define CP_PACKET3 0xC0000000 43 #define PACKET3_IT_OPCODE_SHIFT 8 44 #define PACKET3_IT_OPCODE_MASK (0xff << 8) 45 #define PACKET3_COUNT_SHIFT 16 46 #define PACKET3_COUNT_MASK (0x3fff << 16) 47 /* PACKET3 op code */ 48 #define PACKET3_NOP 0x10 49 #define PACKET3_3D_DRAW_VBUF 0x28 50 #define PACKET3_3D_DRAW_IMMD 0x29 51 #define PACKET3_3D_DRAW_INDX 0x2A 52 #define PACKET3_3D_LOAD_VBPNTR 0x2F 53 #define PACKET3_3D_CLEAR_ZMASK 0x32 54 #define PACKET3_INDX_BUFFER 0x33 55 #define PACKET3_3D_DRAW_VBUF_2 0x34 56 #define PACKET3_3D_DRAW_IMMD_2 0x35 57 #define PACKET3_3D_DRAW_INDX_2 0x36 58 #define PACKET3_3D_CLEAR_HIZ 0x37 59 #define PACKET3_BITBLT_MULTI 0x9B 60 61 #define PACKET0(reg, n) (CP_PACKET0 | \ 62 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 63 REG_SET(PACKET0_COUNT, (n))) 64 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 65 #define PACKET3(op, n) (CP_PACKET3 | \ 66 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 67 REG_SET(PACKET3_COUNT, (n))) 68 69 /* Registers */ 70 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 71 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 72 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 73 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 74 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 75 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 76 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 77 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 78 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 79 #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 80 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 81 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 82 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 83 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 84 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 85 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 86 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 87 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 88 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 89 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 90 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 91 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 92 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 93 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 94 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 95 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 96 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 97 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 98 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 99 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 100 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 101 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 102 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 103 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 104 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 105 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 106 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 107 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 108 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 109 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 110 #define R_000030_BUS_CNTL 0x000030 111 #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 112 #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 113 #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 114 #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 115 #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 116 #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 117 #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 118 #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 119 #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 120 #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 121 #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 122 #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 123 #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 124 #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 125 #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 126 #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 127 #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 128 #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 129 #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 130 #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 131 #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 132 #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 133 #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 134 #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 135 #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 136 #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 137 #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 138 #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 139 #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 140 #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 141 #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 142 #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 143 #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 144 #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 145 #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 146 #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 147 #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 148 #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 149 #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 150 #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 151 #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 152 #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 153 #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 154 #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 155 #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 156 #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 157 #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 158 #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 159 #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 160 #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 161 #define C_000030_BUS_RETRY_WS 0xFFF0FFFF 162 #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 163 #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 164 #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 165 #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 166 #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 167 #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 168 #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 169 #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 170 #define C_000030_BUS_SUSPEND 0xFFBFFFFF 171 #define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 172 #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 173 #define C_000030_LAT_16X 0xFF7FFFFF 174 #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 175 #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 176 #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 177 #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 178 #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 179 #define C_000030_ENFRCWRDY 0xFDFFFFFF 180 #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 181 #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 182 #define C_000030_BUS_MSTR_WS 0xFBFFFFFF 183 #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 184 #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 185 #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 186 #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 187 #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 188 #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 189 #define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 190 #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 191 #define C_000030_SERR_EN 0xDFFFFFFF 192 #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 193 #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 194 #define C_000030_BUS_READ_BURST 0xBFFFFFFF 195 #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 196 #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 197 #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 198 #define R_000040_GEN_INT_CNTL 0x000040 199 #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 200 #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 201 #define C_000040_CRTC_VBLANK 0xFFFFFFFE 202 #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 203 #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 204 #define C_000040_CRTC_VLINE 0xFFFFFFFD 205 #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 206 #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 207 #define C_000040_CRTC_VSYNC 0xFFFFFFFB 208 #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 209 #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 210 #define C_000040_SNAPSHOT 0xFFFFFFF7 211 #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 212 #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 213 #define C_000040_FP_DETECT 0xFFFFFFEF 214 #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 215 #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 216 #define C_000040_CRTC2_VLINE 0xFFFFFFDF 217 #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 218 #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 219 #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 220 #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 221 #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 222 #define C_000040_CRTC2_VSYNC 0xFFFFFFBF 223 #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 224 #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 225 #define C_000040_SNAPSHOT2 0xFFFFFF7F 226 #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 227 #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 228 #define C_000040_CRTC2_VBLANK 0xFFFFFDFF 229 #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 230 #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 231 #define C_000040_FP2_DETECT 0xFFFFFBFF 232 #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 233 #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 234 #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 235 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 236 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 237 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 238 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 239 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 240 #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 241 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 242 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 243 #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 244 #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 245 #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 246 #define C_000040_I2C_INT_EN 0xFFFDFFFF 247 #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 248 #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 249 #define C_000040_GUI_IDLE 0xFFF7FFFF 250 #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 251 #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 252 #define C_000040_VIPH_INT_EN 0xFEFFFFFF 253 #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 254 #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 255 #define C_000040_SW_INT_EN 0xFDFFFFFF 256 #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 257 #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 258 #define C_000040_GEYSERVILLE 0xF7FFFFFF 259 #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 260 #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 261 #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 262 #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 263 #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 264 #define C_000040_DVI_I2C_INT 0xDFFFFFFF 265 #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 266 #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 267 #define C_000040_GUIDMA 0xBFFFFFFF 268 #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 269 #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 270 #define C_000040_VIDDMA 0x7FFFFFFF 271 #define R_000044_GEN_INT_STATUS 0x000044 272 #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 273 #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 274 #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 275 #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 276 #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 277 #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 278 #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 279 #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 280 #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 281 #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 282 #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 283 #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 284 #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 285 #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 286 #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 287 #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 288 #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 289 #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 290 #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 291 #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 292 #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 293 #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 294 #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 295 #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 296 #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 297 #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 298 #define C_000044_FP_DETECT_STAT 0xFFFFFFEF 299 #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 300 #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 301 #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 302 #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 303 #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 304 #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 305 #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 306 #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 307 #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 308 #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 309 #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 310 #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 311 #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 312 #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 313 #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 314 #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 315 #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 316 #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 317 #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 318 #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 319 #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 320 #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 321 #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 322 #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 323 #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 324 #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 325 #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 326 #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 327 #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 328 #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 329 #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 330 #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 331 #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 332 #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 333 #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 334 #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 335 #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 336 #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 337 #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 338 #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 339 #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 340 #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 341 #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 342 #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 343 #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 344 #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 345 #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 346 #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 347 #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 348 #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 349 #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 350 #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 351 #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 352 #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 353 #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 354 #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 355 #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 356 #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 357 #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 358 #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 359 #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 360 #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 361 #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 362 #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 363 #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 364 #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 365 #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 366 #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 367 #define C_000044_I2C_INT 0xFFFDFFFF 368 #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 369 #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 370 #define C_000044_I2C_INT_AK 0xFFFDFFFF 371 #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 372 #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 373 #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 374 #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 375 #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 376 #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 377 #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 378 #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 379 #define C_000044_VIPH_INT 0xFEFFFFFF 380 #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 381 #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 382 #define C_000044_SW_INT 0xFDFFFFFF 383 #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 384 #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 385 #define C_000044_SW_INT_AK 0xFDFFFFFF 386 #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 387 #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 388 #define C_000044_SW_INT_SET 0xFBFFFFFF 389 #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 390 #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 391 #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 392 #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 393 #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 394 #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 395 #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 396 #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 397 #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 398 #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 399 #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 400 #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 401 #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 402 #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 403 #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 404 #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 405 #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 406 #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 407 #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 408 #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 409 #define C_000044_GUIDMA_STAT 0xBFFFFFFF 410 #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 411 #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 412 #define C_000044_GUIDMA_AK 0xBFFFFFFF 413 #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 414 #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 415 #define C_000044_VIDDMA_STAT 0x7FFFFFFF 416 #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 417 #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 418 #define C_000044_VIDDMA_AK 0x7FFFFFFF 419 #define R_000050_CRTC_GEN_CNTL 0x000050 420 #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 421 #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 422 #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 423 #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 424 #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 425 #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 426 #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 427 #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 428 #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 429 #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 430 #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 431 #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 432 #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 433 #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 434 #define C_000050_CRTC_ICON_EN 0xFFFF7FFF 435 #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 436 #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 437 #define C_000050_CRTC_CUR_EN 0xFFFEFFFF 438 #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 439 #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 440 #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 441 #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 442 #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 443 #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 444 #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 445 #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 446 #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 447 #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 448 #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 449 #define C_000050_CRTC_EN 0xFDFFFFFF 450 #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 451 #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 452 #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 453 #define R_000054_CRTC_EXT_CNTL 0x000054 454 #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 455 #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 456 #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 457 #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 458 #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 459 #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 460 #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 461 #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 462 #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 463 #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 464 #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 465 #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 466 #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 467 #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 468 #define C_000054_VGA_TEXT_132 0xFFFFFFDF 469 #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 470 #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 471 #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 472 #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 473 #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 474 #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 475 #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 476 #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 477 #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 478 #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 479 #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 480 #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 481 #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 482 #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 483 #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 484 #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 485 #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 486 #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 487 #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 488 #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 489 #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 490 #define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 491 #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 492 #define C_000054_CRT_ON 0xFFFF7FFF 493 #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 494 #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 495 #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 496 #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 497 #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 498 #define C_000054_VGA_PACK_DIS 0xFFFBFFFF 499 #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 500 #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 501 #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 502 #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 503 #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 504 #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 505 #define R_000148_MC_FB_LOCATION 0x000148 506 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 507 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 508 #define C_000148_MC_FB_START 0xFFFF0000 509 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 510 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 511 #define C_000148_MC_FB_TOP 0x0000FFFF 512 #define R_00014C_MC_AGP_LOCATION 0x00014C 513 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 514 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 515 #define C_00014C_MC_AGP_START 0xFFFF0000 516 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 517 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 518 #define C_00014C_MC_AGP_TOP 0x0000FFFF 519 #define R_000170_AGP_BASE 0x000170 520 #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 521 #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 522 #define C_000170_AGP_BASE_ADDR 0x00000000 523 #define R_00023C_DISPLAY_BASE_ADDR 0x00023C 524 #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 525 #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 526 #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 527 #define R_000260_CUR_OFFSET 0x000260 528 #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 529 #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 530 #define C_000260_CUR_OFFSET 0xF8000000 531 #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 532 #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 533 #define C_000260_CUR_LOCK 0x7FFFFFFF 534 #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 535 #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 536 #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 537 #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 538 #define R_000360_CUR2_OFFSET 0x000360 539 #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 540 #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 541 #define C_000360_CUR2_OFFSET 0xF8000000 542 #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 543 #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 544 #define C_000360_CUR2_LOCK 0x7FFFFFFF 545 #define R_0003C2_GENMO_WT 0x0003C2 546 #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 547 #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 548 #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 549 #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 550 #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 551 #define C_0003C2_VGA_RAM_EN 0xFD 552 #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 553 #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 554 #define C_0003C2_VGA_CKSEL 0xF3 555 #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 556 #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 557 #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 558 #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 559 #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 560 #define C_0003C2_VGA_HSYNC_POL 0xBF 561 #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 562 #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 563 #define C_0003C2_VGA_VSYNC_POL 0x7F 564 #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 565 #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 566 #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 567 #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 568 #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 569 #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 570 #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 571 #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 572 #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 573 #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 574 #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 575 #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 576 #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 577 #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 578 #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 579 #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 580 #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 581 #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 582 #define C_0003F8_CRT2_ON 0xFFFFFF7F 583 #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 584 #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 585 #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 586 #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 587 #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 588 #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 589 #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 590 #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 591 #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 592 #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 593 #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 594 #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 595 #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 596 #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 597 #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 598 #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 599 #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 600 #define C_0003F8_CRTC2_EN 0xFDFFFFFF 601 #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 602 #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 603 #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 604 #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 605 #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 606 #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 607 #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 608 #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 609 #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 610 #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 611 #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 612 #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 613 #define R_000420_OV0_SCALE_CNTL 0x000420 614 #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 615 #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 616 #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 617 #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 618 #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 619 #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 620 #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 621 #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 622 #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 623 #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 624 #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 625 #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 626 #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 627 #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 628 #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 629 #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 630 #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 631 #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 632 #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 633 #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 634 #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 635 #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 636 #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 637 #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 638 #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 639 #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 640 #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 641 #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 642 #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 643 #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 644 #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 645 #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 646 #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 647 #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 648 #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 649 #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 650 #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 651 #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 652 #define C_000420_OV0_INT_EMU 0xDFFFFFFF 653 #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 654 #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 655 #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 656 #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 657 #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 658 #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 659 #define R_00070C_CP_RB_RPTR_ADDR 0x00070C 660 #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 661 #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 662 #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 663 #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 664 #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 665 #define C_00070C_RB_RPTR_ADDR 0x00000003 666 #define R_000740_CP_CSQ_CNTL 0x000740 667 #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 668 #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 669 #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 670 #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 671 #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 672 #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 673 #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 674 #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 675 #define C_000740_CSQ_MODE 0x0FFFFFFF 676 #define R_000770_SCRATCH_UMSK 0x000770 677 #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 678 #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 679 #define C_000770_SCRATCH_UMSK 0xFFFFFFC0 680 #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 681 #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 682 #define C_000770_SCRATCH_SWAP 0xFFFCFFFF 683 #define R_000774_SCRATCH_ADDR 0x000774 684 #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 685 #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 686 #define C_000774_SCRATCH_ADDR 0x0000001F 687 #define R_0007C0_CP_STAT 0x0007C0 688 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 689 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 690 #define C_0007C0_MRU_BUSY 0xFFFFFFFE 691 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 692 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 693 #define C_0007C0_MWU_BUSY 0xFFFFFFFD 694 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 695 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 696 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 697 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 698 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 699 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 700 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 701 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 702 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 703 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 704 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 705 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 706 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 707 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 708 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 709 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 710 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 711 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 712 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 713 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 714 #define C_0007C0_CSI_BUSY 0xFFFFDFFF 715 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 716 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 717 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 718 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 719 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 720 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 721 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 722 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 723 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 724 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 725 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 726 #define C_0007C0_CP_BUSY 0x7FFFFFFF 727 #define R_000E40_RBBM_STATUS 0x000E40 728 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 729 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 730 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 731 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 732 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 733 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 734 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 735 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 736 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 737 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 738 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 739 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 740 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 741 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 742 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 743 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 744 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 745 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 746 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 747 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 748 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 749 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 750 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 751 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 752 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 753 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 754 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 755 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 756 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 757 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 758 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 759 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 760 #define C_000E40_E2_BUSY 0xFFFDFFFF 761 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 762 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 763 #define C_000E40_RB2D_BUSY 0xFFFBFFFF 764 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 765 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 766 #define C_000E40_RB3D_BUSY 0xFFF7FFFF 767 #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 768 #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 769 #define C_000E40_SE_BUSY 0xFFEFFFFF 770 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 771 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 772 #define C_000E40_RE_BUSY 0xFFDFFFFF 773 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 774 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 775 #define C_000E40_TAM_BUSY 0xFFBFFFFF 776 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 777 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 778 #define C_000E40_TDM_BUSY 0xFF7FFFFF 779 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 780 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 781 #define C_000E40_PB_BUSY 0xFEFFFFFF 782 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 783 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 784 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 785 786 787 #define R_00000D_SCLK_CNTL 0x00000D 788 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 789 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 790 #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 791 #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 792 #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 793 #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 794 #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 795 #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 796 #define C_00000D_FORCE_CP 0xFFFEFFFF 797 #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 798 #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 799 #define C_00000D_FORCE_HDP 0xFFFDFFFF 800 #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 801 #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 802 #define C_00000D_FORCE_DISP 0xFFFBFFFF 803 #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 804 #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 805 #define C_00000D_FORCE_TOP 0xFFF7FFFF 806 #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 807 #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 808 #define C_00000D_FORCE_E2 0xFFEFFFFF 809 #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 810 #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 811 #define C_00000D_FORCE_SE 0xFFDFFFFF 812 #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 813 #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 814 #define C_00000D_FORCE_IDCT 0xFFBFFFFF 815 #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 816 #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 817 #define C_00000D_FORCE_VIP 0xFF7FFFFF 818 #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 819 #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 820 #define C_00000D_FORCE_RE 0xFEFFFFFF 821 #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 822 #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 823 #define C_00000D_FORCE_PB 0xFDFFFFFF 824 #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 825 #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 826 #define C_00000D_FORCE_TAM 0xFBFFFFFF 827 #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 828 #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 829 #define C_00000D_FORCE_TDM 0xF7FFFFFF 830 #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 831 #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 832 #define C_00000D_FORCE_RB 0xEFFFFFFF 833 834 /* PLL regs */ 835 #define SCLK_CNTL 0xd 836 #define FORCE_HDP (1 << 17) 837 #define CLK_PWRMGT_CNTL 0x14 838 #define GLOBAL_PMAN_EN (1 << 10) 839 #define DISP_PM (1 << 20) 840 #define PLL_PWRMGT_CNTL 0x15 841 #define MPLL_TURNOFF (1 << 0) 842 #define SPLL_TURNOFF (1 << 1) 843 #define PPLL_TURNOFF (1 << 2) 844 #define P2PLL_TURNOFF (1 << 3) 845 #define TVPLL_TURNOFF (1 << 4) 846 #define MOBILE_SU (1 << 16) 847 #define SU_SCLK_USE_BCLK (1 << 17) 848 #define SCLK_CNTL2 0x1e 849 #define REDUCED_SPEED_SCLK_MODE (1 << 16) 850 #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 851 #define MCLK_MISC 0x1f 852 #define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 853 #define SCLK_MORE_CNTL 0x35 854 #define REDUCED_SPEED_SCLK_EN (1 << 16) 855 #define IO_CG_VOLTAGE_DROP (1 << 17) 856 #define VOLTAGE_DELAY_SEL(x) ((x) << 20) 857 #define VOLTAGE_DROP_SYNC (1 << 19) 858 859 /* mmreg */ 860 #define DISP_PWR_MAN 0xd08 861 #define DISP_D3_GRPH_RST (1 << 18) 862 #define DISP_D3_SUBPIC_RST (1 << 19) 863 #define DISP_D3_OV0_RST (1 << 20) 864 #define DISP_D1D2_GRPH_RST (1 << 21) 865 #define DISP_D1D2_SUBPIC_RST (1 << 22) 866 #define DISP_D1D2_OV0_RST (1 << 23) 867 #define DISP_DVO_ENABLE_RST (1 << 24) 868 #define TV_ENABLE_RST (1 << 25) 869 #define AUTO_PWRUP_EN (1 << 26) 870 871 #endif 872
Indexes created Sat Sep 20 22:09:52 GMT 2025