1 /* $NetBSD: radeon_asic.c,v 1.5 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_asic.c,v 1.5 2021/12/18 23:45:43 riastradh Exp $"); 33 34 #include <linux/console.h> 35 #include <linux/pci.h> 36 #include <linux/vgaarb.h> 37 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/radeon_drm.h> 40 41 #include "atom.h" 42 #include "radeon.h" 43 #include "radeon_asic.h" 44 #include "radeon_reg.h" 45 46 /* 47 * Registers accessors functions. 48 */ 49 /** 50 * radeon_invalid_rreg - dummy reg read function 51 * 52 * @rdev: radeon device pointer 53 * @reg: offset of register 54 * 55 * Dummy register read function. Used for register blocks 56 * that certain asics don't have (all asics). 57 * Returns the value in the register. 58 */ 59 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 60 { 61 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 62 BUG_ON(1); 63 return 0; 64 } 65 66 /** 67 * radeon_invalid_wreg - dummy reg write function 68 * 69 * @rdev: radeon device pointer 70 * @reg: offset of register 71 * @v: value to write to the register 72 * 73 * Dummy register read function. Used for register blocks 74 * that certain asics don't have (all asics). 75 */ 76 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 77 { 78 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 79 reg, v); 80 BUG_ON(1); 81 } 82 83 /** 84 * radeon_register_accessor_init - sets up the register accessor callbacks 85 * 86 * @rdev: radeon device pointer 87 * 88 * Sets up the register accessor callbacks for various register 89 * apertures. Not all asics have all apertures (all asics). 90 */ 91 static void radeon_register_accessor_init(struct radeon_device *rdev) 92 { 93 rdev->mc_rreg = &radeon_invalid_rreg; 94 rdev->mc_wreg = &radeon_invalid_wreg; 95 rdev->pll_rreg = &radeon_invalid_rreg; 96 rdev->pll_wreg = &radeon_invalid_wreg; 97 rdev->pciep_rreg = &radeon_invalid_rreg; 98 rdev->pciep_wreg = &radeon_invalid_wreg; 99 100 /* Don't change order as we are overridding accessor. */ 101 if (rdev->family < CHIP_RV515) { 102 rdev->pcie_reg_mask = 0xff; 103 } else { 104 rdev->pcie_reg_mask = 0x7ff; 105 } 106 /* FIXME: not sure here */ 107 if (rdev->family <= CHIP_R580) { 108 rdev->pll_rreg = &r100_pll_rreg; 109 rdev->pll_wreg = &r100_pll_wreg; 110 } 111 if (rdev->family >= CHIP_R420) { 112 rdev->mc_rreg = &r420_mc_rreg; 113 rdev->mc_wreg = &r420_mc_wreg; 114 } 115 if (rdev->family >= CHIP_RV515) { 116 rdev->mc_rreg = &rv515_mc_rreg; 117 rdev->mc_wreg = &rv515_mc_wreg; 118 } 119 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 120 rdev->mc_rreg = &rs400_mc_rreg; 121 rdev->mc_wreg = &rs400_mc_wreg; 122 } 123 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 124 rdev->mc_rreg = &rs690_mc_rreg; 125 rdev->mc_wreg = &rs690_mc_wreg; 126 } 127 if (rdev->family == CHIP_RS600) { 128 rdev->mc_rreg = &rs600_mc_rreg; 129 rdev->mc_wreg = &rs600_mc_wreg; 130 } 131 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 132 rdev->mc_rreg = &rs780_mc_rreg; 133 rdev->mc_wreg = &rs780_mc_wreg; 134 } 135 136 if (rdev->family >= CHIP_BONAIRE) { 137 rdev->pciep_rreg = &cik_pciep_rreg; 138 rdev->pciep_wreg = &cik_pciep_wreg; 139 } else if (rdev->family >= CHIP_R600) { 140 rdev->pciep_rreg = &r600_pciep_rreg; 141 rdev->pciep_wreg = &r600_pciep_wreg; 142 } 143 } 144 145 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, 146 u32 reg, u32 *val) 147 { 148 return -EINVAL; 149 } 150 151 /* helper to disable agp */ 152 /** 153 * radeon_agp_disable - AGP disable helper function 154 * 155 * @rdev: radeon device pointer 156 * 157 * Removes AGP flags and changes the gart callbacks on AGP 158 * cards when using the internal gart rather than AGP (all asics). 159 */ 160 void radeon_agp_disable(struct radeon_device *rdev) 161 { 162 rdev->flags &= ~RADEON_IS_AGP; 163 if (rdev->family >= CHIP_R600) { 164 DRM_INFO("Forcing AGP to PCIE mode\n"); 165 rdev->flags |= RADEON_IS_PCIE; 166 } else if (rdev->family >= CHIP_RV515 || 167 rdev->family == CHIP_RV380 || 168 rdev->family == CHIP_RV410 || 169 rdev->family == CHIP_R423) { 170 DRM_INFO("Forcing AGP to PCIE mode\n"); 171 rdev->flags |= RADEON_IS_PCIE; 172 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 173 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 174 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 175 } else { 176 DRM_INFO("Forcing AGP to PCI mode\n"); 177 rdev->flags |= RADEON_IS_PCI; 178 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 179 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 180 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 181 } 182 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 183 } 184 185 /* 186 * ASIC 187 */ 188 189 static const struct radeon_asic_ring r100_gfx_ring = { 190 .ib_execute = &r100_ring_ib_execute, 191 .emit_fence = &r100_fence_ring_emit, 192 .emit_semaphore = &r100_semaphore_ring_emit, 193 .cs_parse = &r100_cs_parse, 194 .ring_start = &r100_ring_start, 195 .ring_test = &r100_ring_test, 196 .ib_test = &r100_ib_test, 197 .is_lockup = &r100_gpu_is_lockup, 198 .get_rptr = &r100_gfx_get_rptr, 199 .get_wptr = &r100_gfx_get_wptr, 200 .set_wptr = &r100_gfx_set_wptr, 201 }; 202 203 static struct radeon_asic r100_asic = { 204 .init = &r100_init, 205 .fini = &r100_fini, 206 .suspend = &r100_suspend, 207 .resume = &r100_resume, 208 .vga_set_state = &r100_vga_set_state, 209 .asic_reset = &r100_asic_reset, 210 .mmio_hdp_flush = NULL, 211 .gui_idle = &r100_gui_idle, 212 .mc_wait_for_idle = &r100_mc_wait_for_idle, 213 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 214 .gart = { 215 .tlb_flush = &r100_pci_gart_tlb_flush, 216 .get_page_entry = &r100_pci_gart_get_page_entry, 217 .set_page = &r100_pci_gart_set_page, 218 }, 219 .ring = { 220 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 221 }, 222 .irq = { 223 .set = &r100_irq_set, 224 .process = &r100_irq_process, 225 }, 226 .display = { 227 .bandwidth_update = &r100_bandwidth_update, 228 .get_vblank_counter = &r100_get_vblank_counter, 229 .wait_for_vblank = &r100_wait_for_vblank, 230 .set_backlight_level = &radeon_legacy_set_backlight_level, 231 .get_backlight_level = &radeon_legacy_get_backlight_level, 232 }, 233 .copy = { 234 .blit = &r100_copy_blit, 235 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 236 .dma = NULL, 237 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 238 .copy = &r100_copy_blit, 239 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 240 }, 241 .surface = { 242 .set_reg = r100_set_surface_reg, 243 .clear_reg = r100_clear_surface_reg, 244 }, 245 .hpd = { 246 .init = &r100_hpd_init, 247 .fini = &r100_hpd_fini, 248 .sense = &r100_hpd_sense, 249 .set_polarity = &r100_hpd_set_polarity, 250 }, 251 .pm = { 252 .misc = &r100_pm_misc, 253 .prepare = &r100_pm_prepare, 254 .finish = &r100_pm_finish, 255 .init_profile = &r100_pm_init_profile, 256 .get_dynpm_state = &r100_pm_get_dynpm_state, 257 .get_engine_clock = &radeon_legacy_get_engine_clock, 258 .set_engine_clock = &radeon_legacy_set_engine_clock, 259 .get_memory_clock = &radeon_legacy_get_memory_clock, 260 .set_memory_clock = NULL, 261 .get_pcie_lanes = NULL, 262 .set_pcie_lanes = NULL, 263 .set_clock_gating = &radeon_legacy_set_clock_gating, 264 }, 265 .pflip = { 266 .page_flip = &r100_page_flip, 267 .page_flip_pending = &r100_page_flip_pending, 268 }, 269 }; 270 271 static struct radeon_asic r200_asic = { 272 .init = &r100_init, 273 .fini = &r100_fini, 274 .suspend = &r100_suspend, 275 .resume = &r100_resume, 276 .vga_set_state = &r100_vga_set_state, 277 .asic_reset = &r100_asic_reset, 278 .mmio_hdp_flush = NULL, 279 .gui_idle = &r100_gui_idle, 280 .mc_wait_for_idle = &r100_mc_wait_for_idle, 281 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 282 .gart = { 283 .tlb_flush = &r100_pci_gart_tlb_flush, 284 .get_page_entry = &r100_pci_gart_get_page_entry, 285 .set_page = &r100_pci_gart_set_page, 286 }, 287 .ring = { 288 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 289 }, 290 .irq = { 291 .set = &r100_irq_set, 292 .process = &r100_irq_process, 293 }, 294 .display = { 295 .bandwidth_update = &r100_bandwidth_update, 296 .get_vblank_counter = &r100_get_vblank_counter, 297 .wait_for_vblank = &r100_wait_for_vblank, 298 .set_backlight_level = &radeon_legacy_set_backlight_level, 299 .get_backlight_level = &radeon_legacy_get_backlight_level, 300 }, 301 .copy = { 302 .blit = &r100_copy_blit, 303 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 304 .dma = &r200_copy_dma, 305 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 306 .copy = &r100_copy_blit, 307 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 308 }, 309 .surface = { 310 .set_reg = r100_set_surface_reg, 311 .clear_reg = r100_clear_surface_reg, 312 }, 313 .hpd = { 314 .init = &r100_hpd_init, 315 .fini = &r100_hpd_fini, 316 .sense = &r100_hpd_sense, 317 .set_polarity = &r100_hpd_set_polarity, 318 }, 319 .pm = { 320 .misc = &r100_pm_misc, 321 .prepare = &r100_pm_prepare, 322 .finish = &r100_pm_finish, 323 .init_profile = &r100_pm_init_profile, 324 .get_dynpm_state = &r100_pm_get_dynpm_state, 325 .get_engine_clock = &radeon_legacy_get_engine_clock, 326 .set_engine_clock = &radeon_legacy_set_engine_clock, 327 .get_memory_clock = &radeon_legacy_get_memory_clock, 328 .set_memory_clock = NULL, 329 .get_pcie_lanes = NULL, 330 .set_pcie_lanes = NULL, 331 .set_clock_gating = &radeon_legacy_set_clock_gating, 332 }, 333 .pflip = { 334 .page_flip = &r100_page_flip, 335 .page_flip_pending = &r100_page_flip_pending, 336 }, 337 }; 338 339 static const struct radeon_asic_ring r300_gfx_ring = { 340 .ib_execute = &r100_ring_ib_execute, 341 .emit_fence = &r300_fence_ring_emit, 342 .emit_semaphore = &r100_semaphore_ring_emit, 343 .cs_parse = &r300_cs_parse, 344 .ring_start = &r300_ring_start, 345 .ring_test = &r100_ring_test, 346 .ib_test = &r100_ib_test, 347 .is_lockup = &r100_gpu_is_lockup, 348 .get_rptr = &r100_gfx_get_rptr, 349 .get_wptr = &r100_gfx_get_wptr, 350 .set_wptr = &r100_gfx_set_wptr, 351 }; 352 353 static const struct radeon_asic_ring rv515_gfx_ring = { 354 .ib_execute = &r100_ring_ib_execute, 355 .emit_fence = &r300_fence_ring_emit, 356 .emit_semaphore = &r100_semaphore_ring_emit, 357 .cs_parse = &r300_cs_parse, 358 .ring_start = &rv515_ring_start, 359 .ring_test = &r100_ring_test, 360 .ib_test = &r100_ib_test, 361 .is_lockup = &r100_gpu_is_lockup, 362 .get_rptr = &r100_gfx_get_rptr, 363 .get_wptr = &r100_gfx_get_wptr, 364 .set_wptr = &r100_gfx_set_wptr, 365 }; 366 367 static struct radeon_asic r300_asic = { 368 .init = &r300_init, 369 .fini = &r300_fini, 370 .suspend = &r300_suspend, 371 .resume = &r300_resume, 372 .vga_set_state = &r100_vga_set_state, 373 .asic_reset = &r300_asic_reset, 374 .mmio_hdp_flush = NULL, 375 .gui_idle = &r100_gui_idle, 376 .mc_wait_for_idle = &r300_mc_wait_for_idle, 377 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 378 .gart = { 379 .tlb_flush = &r100_pci_gart_tlb_flush, 380 .get_page_entry = &r100_pci_gart_get_page_entry, 381 .set_page = &r100_pci_gart_set_page, 382 }, 383 .ring = { 384 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 385 }, 386 .irq = { 387 .set = &r100_irq_set, 388 .process = &r100_irq_process, 389 }, 390 .display = { 391 .bandwidth_update = &r100_bandwidth_update, 392 .get_vblank_counter = &r100_get_vblank_counter, 393 .wait_for_vblank = &r100_wait_for_vblank, 394 .set_backlight_level = &radeon_legacy_set_backlight_level, 395 .get_backlight_level = &radeon_legacy_get_backlight_level, 396 }, 397 .copy = { 398 .blit = &r100_copy_blit, 399 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 400 .dma = &r200_copy_dma, 401 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 402 .copy = &r100_copy_blit, 403 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 404 }, 405 .surface = { 406 .set_reg = r100_set_surface_reg, 407 .clear_reg = r100_clear_surface_reg, 408 }, 409 .hpd = { 410 .init = &r100_hpd_init, 411 .fini = &r100_hpd_fini, 412 .sense = &r100_hpd_sense, 413 .set_polarity = &r100_hpd_set_polarity, 414 }, 415 .pm = { 416 .misc = &r100_pm_misc, 417 .prepare = &r100_pm_prepare, 418 .finish = &r100_pm_finish, 419 .init_profile = &r100_pm_init_profile, 420 .get_dynpm_state = &r100_pm_get_dynpm_state, 421 .get_engine_clock = &radeon_legacy_get_engine_clock, 422 .set_engine_clock = &radeon_legacy_set_engine_clock, 423 .get_memory_clock = &radeon_legacy_get_memory_clock, 424 .set_memory_clock = NULL, 425 .get_pcie_lanes = &rv370_get_pcie_lanes, 426 .set_pcie_lanes = &rv370_set_pcie_lanes, 427 .set_clock_gating = &radeon_legacy_set_clock_gating, 428 }, 429 .pflip = { 430 .page_flip = &r100_page_flip, 431 .page_flip_pending = &r100_page_flip_pending, 432 }, 433 }; 434 435 static struct radeon_asic r300_asic_pcie = { 436 .init = &r300_init, 437 .fini = &r300_fini, 438 .suspend = &r300_suspend, 439 .resume = &r300_resume, 440 .vga_set_state = &r100_vga_set_state, 441 .asic_reset = &r300_asic_reset, 442 .mmio_hdp_flush = NULL, 443 .gui_idle = &r100_gui_idle, 444 .mc_wait_for_idle = &r300_mc_wait_for_idle, 445 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 446 .gart = { 447 .tlb_flush = &rv370_pcie_gart_tlb_flush, 448 .get_page_entry = &rv370_pcie_gart_get_page_entry, 449 .set_page = &rv370_pcie_gart_set_page, 450 }, 451 .ring = { 452 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 453 }, 454 .irq = { 455 .set = &r100_irq_set, 456 .process = &r100_irq_process, 457 }, 458 .display = { 459 .bandwidth_update = &r100_bandwidth_update, 460 .get_vblank_counter = &r100_get_vblank_counter, 461 .wait_for_vblank = &r100_wait_for_vblank, 462 .set_backlight_level = &radeon_legacy_set_backlight_level, 463 .get_backlight_level = &radeon_legacy_get_backlight_level, 464 }, 465 .copy = { 466 .blit = &r100_copy_blit, 467 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 468 .dma = &r200_copy_dma, 469 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 470 .copy = &r100_copy_blit, 471 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 472 }, 473 .surface = { 474 .set_reg = r100_set_surface_reg, 475 .clear_reg = r100_clear_surface_reg, 476 }, 477 .hpd = { 478 .init = &r100_hpd_init, 479 .fini = &r100_hpd_fini, 480 .sense = &r100_hpd_sense, 481 .set_polarity = &r100_hpd_set_polarity, 482 }, 483 .pm = { 484 .misc = &r100_pm_misc, 485 .prepare = &r100_pm_prepare, 486 .finish = &r100_pm_finish, 487 .init_profile = &r100_pm_init_profile, 488 .get_dynpm_state = &r100_pm_get_dynpm_state, 489 .get_engine_clock = &radeon_legacy_get_engine_clock, 490 .set_engine_clock = &radeon_legacy_set_engine_clock, 491 .get_memory_clock = &radeon_legacy_get_memory_clock, 492 .set_memory_clock = NULL, 493 .get_pcie_lanes = &rv370_get_pcie_lanes, 494 .set_pcie_lanes = &rv370_set_pcie_lanes, 495 .set_clock_gating = &radeon_legacy_set_clock_gating, 496 }, 497 .pflip = { 498 .page_flip = &r100_page_flip, 499 .page_flip_pending = &r100_page_flip_pending, 500 }, 501 }; 502 503 static struct radeon_asic r420_asic = { 504 .init = &r420_init, 505 .fini = &r420_fini, 506 .suspend = &r420_suspend, 507 .resume = &r420_resume, 508 .vga_set_state = &r100_vga_set_state, 509 .asic_reset = &r300_asic_reset, 510 .mmio_hdp_flush = NULL, 511 .gui_idle = &r100_gui_idle, 512 .mc_wait_for_idle = &r300_mc_wait_for_idle, 513 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 514 .gart = { 515 .tlb_flush = &rv370_pcie_gart_tlb_flush, 516 .get_page_entry = &rv370_pcie_gart_get_page_entry, 517 .set_page = &rv370_pcie_gart_set_page, 518 }, 519 .ring = { 520 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 521 }, 522 .irq = { 523 .set = &r100_irq_set, 524 .process = &r100_irq_process, 525 }, 526 .display = { 527 .bandwidth_update = &r100_bandwidth_update, 528 .get_vblank_counter = &r100_get_vblank_counter, 529 .wait_for_vblank = &r100_wait_for_vblank, 530 .set_backlight_level = &atombios_set_backlight_level, 531 .get_backlight_level = &atombios_get_backlight_level, 532 }, 533 .copy = { 534 .blit = &r100_copy_blit, 535 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 536 .dma = &r200_copy_dma, 537 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 538 .copy = &r100_copy_blit, 539 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 540 }, 541 .surface = { 542 .set_reg = r100_set_surface_reg, 543 .clear_reg = r100_clear_surface_reg, 544 }, 545 .hpd = { 546 .init = &r100_hpd_init, 547 .fini = &r100_hpd_fini, 548 .sense = &r100_hpd_sense, 549 .set_polarity = &r100_hpd_set_polarity, 550 }, 551 .pm = { 552 .misc = &r100_pm_misc, 553 .prepare = &r100_pm_prepare, 554 .finish = &r100_pm_finish, 555 .init_profile = &r420_pm_init_profile, 556 .get_dynpm_state = &r100_pm_get_dynpm_state, 557 .get_engine_clock = &radeon_atom_get_engine_clock, 558 .set_engine_clock = &radeon_atom_set_engine_clock, 559 .get_memory_clock = &radeon_atom_get_memory_clock, 560 .set_memory_clock = &radeon_atom_set_memory_clock, 561 .get_pcie_lanes = &rv370_get_pcie_lanes, 562 .set_pcie_lanes = &rv370_set_pcie_lanes, 563 .set_clock_gating = &radeon_atom_set_clock_gating, 564 }, 565 .pflip = { 566 .page_flip = &r100_page_flip, 567 .page_flip_pending = &r100_page_flip_pending, 568 }, 569 }; 570 571 static struct radeon_asic rs400_asic = { 572 .init = &rs400_init, 573 .fini = &rs400_fini, 574 .suspend = &rs400_suspend, 575 .resume = &rs400_resume, 576 .vga_set_state = &r100_vga_set_state, 577 .asic_reset = &r300_asic_reset, 578 .mmio_hdp_flush = NULL, 579 .gui_idle = &r100_gui_idle, 580 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 581 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 582 .gart = { 583 .tlb_flush = &rs400_gart_tlb_flush, 584 .get_page_entry = &rs400_gart_get_page_entry, 585 .set_page = &rs400_gart_set_page, 586 }, 587 .ring = { 588 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 589 }, 590 .irq = { 591 .set = &r100_irq_set, 592 .process = &r100_irq_process, 593 }, 594 .display = { 595 .bandwidth_update = &r100_bandwidth_update, 596 .get_vblank_counter = &r100_get_vblank_counter, 597 .wait_for_vblank = &r100_wait_for_vblank, 598 .set_backlight_level = &radeon_legacy_set_backlight_level, 599 .get_backlight_level = &radeon_legacy_get_backlight_level, 600 }, 601 .copy = { 602 .blit = &r100_copy_blit, 603 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 604 .dma = &r200_copy_dma, 605 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 606 .copy = &r100_copy_blit, 607 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 608 }, 609 .surface = { 610 .set_reg = r100_set_surface_reg, 611 .clear_reg = r100_clear_surface_reg, 612 }, 613 .hpd = { 614 .init = &r100_hpd_init, 615 .fini = &r100_hpd_fini, 616 .sense = &r100_hpd_sense, 617 .set_polarity = &r100_hpd_set_polarity, 618 }, 619 .pm = { 620 .misc = &r100_pm_misc, 621 .prepare = &r100_pm_prepare, 622 .finish = &r100_pm_finish, 623 .init_profile = &r100_pm_init_profile, 624 .get_dynpm_state = &r100_pm_get_dynpm_state, 625 .get_engine_clock = &radeon_legacy_get_engine_clock, 626 .set_engine_clock = &radeon_legacy_set_engine_clock, 627 .get_memory_clock = &radeon_legacy_get_memory_clock, 628 .set_memory_clock = NULL, 629 .get_pcie_lanes = NULL, 630 .set_pcie_lanes = NULL, 631 .set_clock_gating = &radeon_legacy_set_clock_gating, 632 }, 633 .pflip = { 634 .page_flip = &r100_page_flip, 635 .page_flip_pending = &r100_page_flip_pending, 636 }, 637 }; 638 639 static struct radeon_asic rs600_asic = { 640 .init = &rs600_init, 641 .fini = &rs600_fini, 642 .suspend = &rs600_suspend, 643 .resume = &rs600_resume, 644 .vga_set_state = &r100_vga_set_state, 645 .asic_reset = &rs600_asic_reset, 646 .mmio_hdp_flush = NULL, 647 .gui_idle = &r100_gui_idle, 648 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 649 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 650 .gart = { 651 .tlb_flush = &rs600_gart_tlb_flush, 652 .get_page_entry = &rs600_gart_get_page_entry, 653 .set_page = &rs600_gart_set_page, 654 }, 655 .ring = { 656 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 657 }, 658 .irq = { 659 .set = &rs600_irq_set, 660 .process = &rs600_irq_process, 661 }, 662 .display = { 663 .bandwidth_update = &rs600_bandwidth_update, 664 .get_vblank_counter = &rs600_get_vblank_counter, 665 .wait_for_vblank = &avivo_wait_for_vblank, 666 .set_backlight_level = &atombios_set_backlight_level, 667 .get_backlight_level = &atombios_get_backlight_level, 668 }, 669 .copy = { 670 .blit = &r100_copy_blit, 671 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 672 .dma = &r200_copy_dma, 673 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 674 .copy = &r100_copy_blit, 675 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 676 }, 677 .surface = { 678 .set_reg = r100_set_surface_reg, 679 .clear_reg = r100_clear_surface_reg, 680 }, 681 .hpd = { 682 .init = &rs600_hpd_init, 683 .fini = &rs600_hpd_fini, 684 .sense = &rs600_hpd_sense, 685 .set_polarity = &rs600_hpd_set_polarity, 686 }, 687 .pm = { 688 .misc = &rs600_pm_misc, 689 .prepare = &rs600_pm_prepare, 690 .finish = &rs600_pm_finish, 691 .init_profile = &r420_pm_init_profile, 692 .get_dynpm_state = &r100_pm_get_dynpm_state, 693 .get_engine_clock = &radeon_atom_get_engine_clock, 694 .set_engine_clock = &radeon_atom_set_engine_clock, 695 .get_memory_clock = &radeon_atom_get_memory_clock, 696 .set_memory_clock = &radeon_atom_set_memory_clock, 697 .get_pcie_lanes = NULL, 698 .set_pcie_lanes = NULL, 699 .set_clock_gating = &radeon_atom_set_clock_gating, 700 }, 701 .pflip = { 702 .page_flip = &rs600_page_flip, 703 .page_flip_pending = &rs600_page_flip_pending, 704 }, 705 }; 706 707 static struct radeon_asic rs690_asic = { 708 .init = &rs690_init, 709 .fini = &rs690_fini, 710 .suspend = &rs690_suspend, 711 .resume = &rs690_resume, 712 .vga_set_state = &r100_vga_set_state, 713 .asic_reset = &rs600_asic_reset, 714 .mmio_hdp_flush = NULL, 715 .gui_idle = &r100_gui_idle, 716 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 717 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 718 .gart = { 719 .tlb_flush = &rs400_gart_tlb_flush, 720 .get_page_entry = &rs400_gart_get_page_entry, 721 .set_page = &rs400_gart_set_page, 722 }, 723 .ring = { 724 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 725 }, 726 .irq = { 727 .set = &rs600_irq_set, 728 .process = &rs600_irq_process, 729 }, 730 .display = { 731 .get_vblank_counter = &rs600_get_vblank_counter, 732 .bandwidth_update = &rs690_bandwidth_update, 733 .wait_for_vblank = &avivo_wait_for_vblank, 734 .set_backlight_level = &atombios_set_backlight_level, 735 .get_backlight_level = &atombios_get_backlight_level, 736 }, 737 .copy = { 738 .blit = &r100_copy_blit, 739 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 740 .dma = &r200_copy_dma, 741 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 742 .copy = &r200_copy_dma, 743 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 744 }, 745 .surface = { 746 .set_reg = r100_set_surface_reg, 747 .clear_reg = r100_clear_surface_reg, 748 }, 749 .hpd = { 750 .init = &rs600_hpd_init, 751 .fini = &rs600_hpd_fini, 752 .sense = &rs600_hpd_sense, 753 .set_polarity = &rs600_hpd_set_polarity, 754 }, 755 .pm = { 756 .misc = &rs600_pm_misc, 757 .prepare = &rs600_pm_prepare, 758 .finish = &rs600_pm_finish, 759 .init_profile = &r420_pm_init_profile, 760 .get_dynpm_state = &r100_pm_get_dynpm_state, 761 .get_engine_clock = &radeon_atom_get_engine_clock, 762 .set_engine_clock = &radeon_atom_set_engine_clock, 763 .get_memory_clock = &radeon_atom_get_memory_clock, 764 .set_memory_clock = &radeon_atom_set_memory_clock, 765 .get_pcie_lanes = NULL, 766 .set_pcie_lanes = NULL, 767 .set_clock_gating = &radeon_atom_set_clock_gating, 768 }, 769 .pflip = { 770 .page_flip = &rs600_page_flip, 771 .page_flip_pending = &rs600_page_flip_pending, 772 }, 773 }; 774 775 static struct radeon_asic rv515_asic = { 776 .init = &rv515_init, 777 .fini = &rv515_fini, 778 .suspend = &rv515_suspend, 779 .resume = &rv515_resume, 780 .vga_set_state = &r100_vga_set_state, 781 .asic_reset = &rs600_asic_reset, 782 .mmio_hdp_flush = NULL, 783 .gui_idle = &r100_gui_idle, 784 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 785 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 786 .gart = { 787 .tlb_flush = &rv370_pcie_gart_tlb_flush, 788 .get_page_entry = &rv370_pcie_gart_get_page_entry, 789 .set_page = &rv370_pcie_gart_set_page, 790 }, 791 .ring = { 792 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 793 }, 794 .irq = { 795 .set = &rs600_irq_set, 796 .process = &rs600_irq_process, 797 }, 798 .display = { 799 .get_vblank_counter = &rs600_get_vblank_counter, 800 .bandwidth_update = &rv515_bandwidth_update, 801 .wait_for_vblank = &avivo_wait_for_vblank, 802 .set_backlight_level = &atombios_set_backlight_level, 803 .get_backlight_level = &atombios_get_backlight_level, 804 }, 805 .copy = { 806 .blit = &r100_copy_blit, 807 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 808 .dma = &r200_copy_dma, 809 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 810 .copy = &r100_copy_blit, 811 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 812 }, 813 .surface = { 814 .set_reg = r100_set_surface_reg, 815 .clear_reg = r100_clear_surface_reg, 816 }, 817 .hpd = { 818 .init = &rs600_hpd_init, 819 .fini = &rs600_hpd_fini, 820 .sense = &rs600_hpd_sense, 821 .set_polarity = &rs600_hpd_set_polarity, 822 }, 823 .pm = { 824 .misc = &rs600_pm_misc, 825 .prepare = &rs600_pm_prepare, 826 .finish = &rs600_pm_finish, 827 .init_profile = &r420_pm_init_profile, 828 .get_dynpm_state = &r100_pm_get_dynpm_state, 829 .get_engine_clock = &radeon_atom_get_engine_clock, 830 .set_engine_clock = &radeon_atom_set_engine_clock, 831 .get_memory_clock = &radeon_atom_get_memory_clock, 832 .set_memory_clock = &radeon_atom_set_memory_clock, 833 .get_pcie_lanes = &rv370_get_pcie_lanes, 834 .set_pcie_lanes = &rv370_set_pcie_lanes, 835 .set_clock_gating = &radeon_atom_set_clock_gating, 836 }, 837 .pflip = { 838 .page_flip = &rs600_page_flip, 839 .page_flip_pending = &rs600_page_flip_pending, 840 }, 841 }; 842 843 static struct radeon_asic r520_asic = { 844 .init = &r520_init, 845 .fini = &rv515_fini, 846 .suspend = &rv515_suspend, 847 .resume = &r520_resume, 848 .vga_set_state = &r100_vga_set_state, 849 .asic_reset = &rs600_asic_reset, 850 .mmio_hdp_flush = NULL, 851 .gui_idle = &r100_gui_idle, 852 .mc_wait_for_idle = &r520_mc_wait_for_idle, 853 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 854 .gart = { 855 .tlb_flush = &rv370_pcie_gart_tlb_flush, 856 .get_page_entry = &rv370_pcie_gart_get_page_entry, 857 .set_page = &rv370_pcie_gart_set_page, 858 }, 859 .ring = { 860 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 861 }, 862 .irq = { 863 .set = &rs600_irq_set, 864 .process = &rs600_irq_process, 865 }, 866 .display = { 867 .bandwidth_update = &rv515_bandwidth_update, 868 .get_vblank_counter = &rs600_get_vblank_counter, 869 .wait_for_vblank = &avivo_wait_for_vblank, 870 .set_backlight_level = &atombios_set_backlight_level, 871 .get_backlight_level = &atombios_get_backlight_level, 872 }, 873 .copy = { 874 .blit = &r100_copy_blit, 875 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 876 .dma = &r200_copy_dma, 877 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 878 .copy = &r100_copy_blit, 879 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 880 }, 881 .surface = { 882 .set_reg = r100_set_surface_reg, 883 .clear_reg = r100_clear_surface_reg, 884 }, 885 .hpd = { 886 .init = &rs600_hpd_init, 887 .fini = &rs600_hpd_fini, 888 .sense = &rs600_hpd_sense, 889 .set_polarity = &rs600_hpd_set_polarity, 890 }, 891 .pm = { 892 .misc = &rs600_pm_misc, 893 .prepare = &rs600_pm_prepare, 894 .finish = &rs600_pm_finish, 895 .init_profile = &r420_pm_init_profile, 896 .get_dynpm_state = &r100_pm_get_dynpm_state, 897 .get_engine_clock = &radeon_atom_get_engine_clock, 898 .set_engine_clock = &radeon_atom_set_engine_clock, 899 .get_memory_clock = &radeon_atom_get_memory_clock, 900 .set_memory_clock = &radeon_atom_set_memory_clock, 901 .get_pcie_lanes = &rv370_get_pcie_lanes, 902 .set_pcie_lanes = &rv370_set_pcie_lanes, 903 .set_clock_gating = &radeon_atom_set_clock_gating, 904 }, 905 .pflip = { 906 .page_flip = &rs600_page_flip, 907 .page_flip_pending = &rs600_page_flip_pending, 908 }, 909 }; 910 911 static const struct radeon_asic_ring r600_gfx_ring = { 912 .ib_execute = &r600_ring_ib_execute, 913 .emit_fence = &r600_fence_ring_emit, 914 .emit_semaphore = &r600_semaphore_ring_emit, 915 .cs_parse = &r600_cs_parse, 916 .ring_test = &r600_ring_test, 917 .ib_test = &r600_ib_test, 918 .is_lockup = &r600_gfx_is_lockup, 919 .get_rptr = &r600_gfx_get_rptr, 920 .get_wptr = &r600_gfx_get_wptr, 921 .set_wptr = &r600_gfx_set_wptr, 922 }; 923 924 static const struct radeon_asic_ring r600_dma_ring = { 925 .ib_execute = &r600_dma_ring_ib_execute, 926 .emit_fence = &r600_dma_fence_ring_emit, 927 .emit_semaphore = &r600_dma_semaphore_ring_emit, 928 .cs_parse = &r600_dma_cs_parse, 929 .ring_test = &r600_dma_ring_test, 930 .ib_test = &r600_dma_ib_test, 931 .is_lockup = &r600_dma_is_lockup, 932 .get_rptr = &r600_dma_get_rptr, 933 .get_wptr = &r600_dma_get_wptr, 934 .set_wptr = &r600_dma_set_wptr, 935 }; 936 937 static struct radeon_asic r600_asic = { 938 .init = &r600_init, 939 .fini = &r600_fini, 940 .suspend = &r600_suspend, 941 .resume = &r600_resume, 942 .vga_set_state = &r600_vga_set_state, 943 .asic_reset = &r600_asic_reset, 944 .mmio_hdp_flush = r600_mmio_hdp_flush, 945 .gui_idle = &r600_gui_idle, 946 .mc_wait_for_idle = &r600_mc_wait_for_idle, 947 .get_xclk = &r600_get_xclk, 948 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 949 .get_allowed_info_register = r600_get_allowed_info_register, 950 .gart = { 951 .tlb_flush = &r600_pcie_gart_tlb_flush, 952 .get_page_entry = &rs600_gart_get_page_entry, 953 .set_page = &rs600_gart_set_page, 954 }, 955 .ring = { 956 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 957 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 958 }, 959 .irq = { 960 .set = &r600_irq_set, 961 .process = &r600_irq_process, 962 }, 963 .display = { 964 .bandwidth_update = &rv515_bandwidth_update, 965 .get_vblank_counter = &rs600_get_vblank_counter, 966 .wait_for_vblank = &avivo_wait_for_vblank, 967 .set_backlight_level = &atombios_set_backlight_level, 968 .get_backlight_level = &atombios_get_backlight_level, 969 }, 970 .copy = { 971 .blit = &r600_copy_cpdma, 972 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 973 .dma = &r600_copy_dma, 974 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 975 .copy = &r600_copy_cpdma, 976 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 977 }, 978 .surface = { 979 .set_reg = r600_set_surface_reg, 980 .clear_reg = r600_clear_surface_reg, 981 }, 982 .hpd = { 983 .init = &r600_hpd_init, 984 .fini = &r600_hpd_fini, 985 .sense = &r600_hpd_sense, 986 .set_polarity = &r600_hpd_set_polarity, 987 }, 988 .pm = { 989 .misc = &r600_pm_misc, 990 .prepare = &rs600_pm_prepare, 991 .finish = &rs600_pm_finish, 992 .init_profile = &r600_pm_init_profile, 993 .get_dynpm_state = &r600_pm_get_dynpm_state, 994 .get_engine_clock = &radeon_atom_get_engine_clock, 995 .set_engine_clock = &radeon_atom_set_engine_clock, 996 .get_memory_clock = &radeon_atom_get_memory_clock, 997 .set_memory_clock = &radeon_atom_set_memory_clock, 998 .get_pcie_lanes = &r600_get_pcie_lanes, 999 .set_pcie_lanes = &r600_set_pcie_lanes, 1000 .set_clock_gating = NULL, 1001 .get_temperature = &rv6xx_get_temp, 1002 }, 1003 .pflip = { 1004 .page_flip = &rs600_page_flip, 1005 .page_flip_pending = &rs600_page_flip_pending, 1006 }, 1007 }; 1008 1009 static const struct radeon_asic_ring rv6xx_uvd_ring = { 1010 .ib_execute = &uvd_v1_0_ib_execute, 1011 .emit_fence = &uvd_v1_0_fence_emit, 1012 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1013 .cs_parse = &radeon_uvd_cs_parse, 1014 .ring_test = &uvd_v1_0_ring_test, 1015 .ib_test = &uvd_v1_0_ib_test, 1016 .is_lockup = &radeon_ring_test_lockup, 1017 .get_rptr = &uvd_v1_0_get_rptr, 1018 .get_wptr = &uvd_v1_0_get_wptr, 1019 .set_wptr = &uvd_v1_0_set_wptr, 1020 }; 1021 1022 static struct radeon_asic rv6xx_asic = { 1023 .init = &r600_init, 1024 .fini = &r600_fini, 1025 .suspend = &r600_suspend, 1026 .resume = &r600_resume, 1027 .vga_set_state = &r600_vga_set_state, 1028 .asic_reset = &r600_asic_reset, 1029 .mmio_hdp_flush = r600_mmio_hdp_flush, 1030 .gui_idle = &r600_gui_idle, 1031 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1032 .get_xclk = &r600_get_xclk, 1033 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1034 .get_allowed_info_register = r600_get_allowed_info_register, 1035 .gart = { 1036 .tlb_flush = &r600_pcie_gart_tlb_flush, 1037 .get_page_entry = &rs600_gart_get_page_entry, 1038 .set_page = &rs600_gart_set_page, 1039 }, 1040 .ring = { 1041 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1042 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1043 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1044 }, 1045 .irq = { 1046 .set = &r600_irq_set, 1047 .process = &r600_irq_process, 1048 }, 1049 .display = { 1050 .bandwidth_update = &rv515_bandwidth_update, 1051 .get_vblank_counter = &rs600_get_vblank_counter, 1052 .wait_for_vblank = &avivo_wait_for_vblank, 1053 .set_backlight_level = &atombios_set_backlight_level, 1054 .get_backlight_level = &atombios_get_backlight_level, 1055 }, 1056 .copy = { 1057 .blit = &r600_copy_cpdma, 1058 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1059 .dma = &r600_copy_dma, 1060 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1061 .copy = &r600_copy_cpdma, 1062 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1063 }, 1064 .surface = { 1065 .set_reg = r600_set_surface_reg, 1066 .clear_reg = r600_clear_surface_reg, 1067 }, 1068 .hpd = { 1069 .init = &r600_hpd_init, 1070 .fini = &r600_hpd_fini, 1071 .sense = &r600_hpd_sense, 1072 .set_polarity = &r600_hpd_set_polarity, 1073 }, 1074 .pm = { 1075 .misc = &r600_pm_misc, 1076 .prepare = &rs600_pm_prepare, 1077 .finish = &rs600_pm_finish, 1078 .init_profile = &r600_pm_init_profile, 1079 .get_dynpm_state = &r600_pm_get_dynpm_state, 1080 .get_engine_clock = &radeon_atom_get_engine_clock, 1081 .set_engine_clock = &radeon_atom_set_engine_clock, 1082 .get_memory_clock = &radeon_atom_get_memory_clock, 1083 .set_memory_clock = &radeon_atom_set_memory_clock, 1084 .get_pcie_lanes = &r600_get_pcie_lanes, 1085 .set_pcie_lanes = &r600_set_pcie_lanes, 1086 .set_clock_gating = NULL, 1087 .get_temperature = &rv6xx_get_temp, 1088 .set_uvd_clocks = &r600_set_uvd_clocks, 1089 }, 1090 .dpm = { 1091 .init = &rv6xx_dpm_init, 1092 .setup_asic = &rv6xx_setup_asic, 1093 .enable = &rv6xx_dpm_enable, 1094 .late_enable = &r600_dpm_late_enable, 1095 .disable = &rv6xx_dpm_disable, 1096 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1097 .set_power_state = &rv6xx_dpm_set_power_state, 1098 .post_set_power_state = &r600_dpm_post_set_power_state, 1099 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1100 .fini = &rv6xx_dpm_fini, 1101 .get_sclk = &rv6xx_dpm_get_sclk, 1102 .get_mclk = &rv6xx_dpm_get_mclk, 1103 .print_power_state = &rv6xx_dpm_print_power_state, 1104 #ifdef CONFIG_DEBUG_FS 1105 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1106 #endif 1107 .force_performance_level = &rv6xx_dpm_force_performance_level, 1108 .get_current_sclk = &rv6xx_dpm_get_current_sclk, 1109 .get_current_mclk = &rv6xx_dpm_get_current_mclk, 1110 }, 1111 .pflip = { 1112 .page_flip = &rs600_page_flip, 1113 .page_flip_pending = &rs600_page_flip_pending, 1114 }, 1115 }; 1116 1117 static struct radeon_asic rs780_asic = { 1118 .init = &r600_init, 1119 .fini = &r600_fini, 1120 .suspend = &r600_suspend, 1121 .resume = &r600_resume, 1122 .vga_set_state = &r600_vga_set_state, 1123 .asic_reset = &r600_asic_reset, 1124 .mmio_hdp_flush = r600_mmio_hdp_flush, 1125 .gui_idle = &r600_gui_idle, 1126 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1127 .get_xclk = &r600_get_xclk, 1128 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1129 .get_allowed_info_register = r600_get_allowed_info_register, 1130 .gart = { 1131 .tlb_flush = &r600_pcie_gart_tlb_flush, 1132 .get_page_entry = &rs600_gart_get_page_entry, 1133 .set_page = &rs600_gart_set_page, 1134 }, 1135 .ring = { 1136 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1137 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1138 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1139 }, 1140 .irq = { 1141 .set = &r600_irq_set, 1142 .process = &r600_irq_process, 1143 }, 1144 .display = { 1145 .bandwidth_update = &rs690_bandwidth_update, 1146 .get_vblank_counter = &rs600_get_vblank_counter, 1147 .wait_for_vblank = &avivo_wait_for_vblank, 1148 .set_backlight_level = &atombios_set_backlight_level, 1149 .get_backlight_level = &atombios_get_backlight_level, 1150 }, 1151 .copy = { 1152 .blit = &r600_copy_cpdma, 1153 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1154 .dma = &r600_copy_dma, 1155 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1156 .copy = &r600_copy_cpdma, 1157 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1158 }, 1159 .surface = { 1160 .set_reg = r600_set_surface_reg, 1161 .clear_reg = r600_clear_surface_reg, 1162 }, 1163 .hpd = { 1164 .init = &r600_hpd_init, 1165 .fini = &r600_hpd_fini, 1166 .sense = &r600_hpd_sense, 1167 .set_polarity = &r600_hpd_set_polarity, 1168 }, 1169 .pm = { 1170 .misc = &r600_pm_misc, 1171 .prepare = &rs600_pm_prepare, 1172 .finish = &rs600_pm_finish, 1173 .init_profile = &rs780_pm_init_profile, 1174 .get_dynpm_state = &r600_pm_get_dynpm_state, 1175 .get_engine_clock = &radeon_atom_get_engine_clock, 1176 .set_engine_clock = &radeon_atom_set_engine_clock, 1177 .get_memory_clock = NULL, 1178 .set_memory_clock = NULL, 1179 .get_pcie_lanes = NULL, 1180 .set_pcie_lanes = NULL, 1181 .set_clock_gating = NULL, 1182 .get_temperature = &rv6xx_get_temp, 1183 .set_uvd_clocks = &r600_set_uvd_clocks, 1184 }, 1185 .dpm = { 1186 .init = &rs780_dpm_init, 1187 .setup_asic = &rs780_dpm_setup_asic, 1188 .enable = &rs780_dpm_enable, 1189 .late_enable = &r600_dpm_late_enable, 1190 .disable = &rs780_dpm_disable, 1191 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1192 .set_power_state = &rs780_dpm_set_power_state, 1193 .post_set_power_state = &r600_dpm_post_set_power_state, 1194 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1195 .fini = &rs780_dpm_fini, 1196 .get_sclk = &rs780_dpm_get_sclk, 1197 .get_mclk = &rs780_dpm_get_mclk, 1198 .print_power_state = &rs780_dpm_print_power_state, 1199 #ifdef CONFIG_DEBUG_FS 1200 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1201 #endif 1202 .force_performance_level = &rs780_dpm_force_performance_level, 1203 .get_current_sclk = &rs780_dpm_get_current_sclk, 1204 .get_current_mclk = &rs780_dpm_get_current_mclk, 1205 }, 1206 .pflip = { 1207 .page_flip = &rs600_page_flip, 1208 .page_flip_pending = &rs600_page_flip_pending, 1209 }, 1210 }; 1211 1212 static const struct radeon_asic_ring rv770_uvd_ring = { 1213 .ib_execute = &uvd_v1_0_ib_execute, 1214 .emit_fence = &uvd_v2_2_fence_emit, 1215 .emit_semaphore = &uvd_v2_2_semaphore_emit, 1216 .cs_parse = &radeon_uvd_cs_parse, 1217 .ring_test = &uvd_v1_0_ring_test, 1218 .ib_test = &uvd_v1_0_ib_test, 1219 .is_lockup = &radeon_ring_test_lockup, 1220 .get_rptr = &uvd_v1_0_get_rptr, 1221 .get_wptr = &uvd_v1_0_get_wptr, 1222 .set_wptr = &uvd_v1_0_set_wptr, 1223 }; 1224 1225 static struct radeon_asic rv770_asic = { 1226 .init = &rv770_init, 1227 .fini = &rv770_fini, 1228 .suspend = &rv770_suspend, 1229 .resume = &rv770_resume, 1230 .asic_reset = &r600_asic_reset, 1231 .vga_set_state = &r600_vga_set_state, 1232 .mmio_hdp_flush = r600_mmio_hdp_flush, 1233 .gui_idle = &r600_gui_idle, 1234 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1235 .get_xclk = &rv770_get_xclk, 1236 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1237 .get_allowed_info_register = r600_get_allowed_info_register, 1238 .gart = { 1239 .tlb_flush = &r600_pcie_gart_tlb_flush, 1240 .get_page_entry = &rs600_gart_get_page_entry, 1241 .set_page = &rs600_gart_set_page, 1242 }, 1243 .ring = { 1244 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1245 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1246 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1247 }, 1248 .irq = { 1249 .set = &r600_irq_set, 1250 .process = &r600_irq_process, 1251 }, 1252 .display = { 1253 .bandwidth_update = &rv515_bandwidth_update, 1254 .get_vblank_counter = &rs600_get_vblank_counter, 1255 .wait_for_vblank = &avivo_wait_for_vblank, 1256 .set_backlight_level = &atombios_set_backlight_level, 1257 .get_backlight_level = &atombios_get_backlight_level, 1258 }, 1259 .copy = { 1260 .blit = &r600_copy_cpdma, 1261 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1262 .dma = &rv770_copy_dma, 1263 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1264 .copy = &rv770_copy_dma, 1265 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1266 }, 1267 .surface = { 1268 .set_reg = r600_set_surface_reg, 1269 .clear_reg = r600_clear_surface_reg, 1270 }, 1271 .hpd = { 1272 .init = &r600_hpd_init, 1273 .fini = &r600_hpd_fini, 1274 .sense = &r600_hpd_sense, 1275 .set_polarity = &r600_hpd_set_polarity, 1276 }, 1277 .pm = { 1278 .misc = &rv770_pm_misc, 1279 .prepare = &rs600_pm_prepare, 1280 .finish = &rs600_pm_finish, 1281 .init_profile = &r600_pm_init_profile, 1282 .get_dynpm_state = &r600_pm_get_dynpm_state, 1283 .get_engine_clock = &radeon_atom_get_engine_clock, 1284 .set_engine_clock = &radeon_atom_set_engine_clock, 1285 .get_memory_clock = &radeon_atom_get_memory_clock, 1286 .set_memory_clock = &radeon_atom_set_memory_clock, 1287 .get_pcie_lanes = &r600_get_pcie_lanes, 1288 .set_pcie_lanes = &r600_set_pcie_lanes, 1289 .set_clock_gating = &radeon_atom_set_clock_gating, 1290 .set_uvd_clocks = &rv770_set_uvd_clocks, 1291 .get_temperature = &rv770_get_temp, 1292 }, 1293 .dpm = { 1294 .init = &rv770_dpm_init, 1295 .setup_asic = &rv770_dpm_setup_asic, 1296 .enable = &rv770_dpm_enable, 1297 .late_enable = &rv770_dpm_late_enable, 1298 .disable = &rv770_dpm_disable, 1299 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1300 .set_power_state = &rv770_dpm_set_power_state, 1301 .post_set_power_state = &r600_dpm_post_set_power_state, 1302 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1303 .fini = &rv770_dpm_fini, 1304 .get_sclk = &rv770_dpm_get_sclk, 1305 .get_mclk = &rv770_dpm_get_mclk, 1306 .print_power_state = &rv770_dpm_print_power_state, 1307 #ifdef CONFIG_DEBUG_FS 1308 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1309 #endif 1310 .force_performance_level = &rv770_dpm_force_performance_level, 1311 .vblank_too_short = &rv770_dpm_vblank_too_short, 1312 .get_current_sclk = &rv770_dpm_get_current_sclk, 1313 .get_current_mclk = &rv770_dpm_get_current_mclk, 1314 }, 1315 .pflip = { 1316 .page_flip = &rv770_page_flip, 1317 .page_flip_pending = &rv770_page_flip_pending, 1318 }, 1319 }; 1320 1321 static const struct radeon_asic_ring evergreen_gfx_ring = { 1322 .ib_execute = &evergreen_ring_ib_execute, 1323 .emit_fence = &r600_fence_ring_emit, 1324 .emit_semaphore = &r600_semaphore_ring_emit, 1325 .cs_parse = &evergreen_cs_parse, 1326 .ring_test = &r600_ring_test, 1327 .ib_test = &r600_ib_test, 1328 .is_lockup = &evergreen_gfx_is_lockup, 1329 .get_rptr = &r600_gfx_get_rptr, 1330 .get_wptr = &r600_gfx_get_wptr, 1331 .set_wptr = &r600_gfx_set_wptr, 1332 }; 1333 1334 static const struct radeon_asic_ring evergreen_dma_ring = { 1335 .ib_execute = &evergreen_dma_ring_ib_execute, 1336 .emit_fence = &evergreen_dma_fence_ring_emit, 1337 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1338 .cs_parse = &evergreen_dma_cs_parse, 1339 .ring_test = &r600_dma_ring_test, 1340 .ib_test = &r600_dma_ib_test, 1341 .is_lockup = &evergreen_dma_is_lockup, 1342 .get_rptr = &r600_dma_get_rptr, 1343 .get_wptr = &r600_dma_get_wptr, 1344 .set_wptr = &r600_dma_set_wptr, 1345 }; 1346 1347 static struct radeon_asic evergreen_asic = { 1348 .init = &evergreen_init, 1349 .fini = &evergreen_fini, 1350 .suspend = &evergreen_suspend, 1351 .resume = &evergreen_resume, 1352 .asic_reset = &evergreen_asic_reset, 1353 .vga_set_state = &r600_vga_set_state, 1354 .mmio_hdp_flush = r600_mmio_hdp_flush, 1355 .gui_idle = &r600_gui_idle, 1356 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1357 .get_xclk = &rv770_get_xclk, 1358 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1359 .get_allowed_info_register = evergreen_get_allowed_info_register, 1360 .gart = { 1361 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1362 .get_page_entry = &rs600_gart_get_page_entry, 1363 .set_page = &rs600_gart_set_page, 1364 }, 1365 .ring = { 1366 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1367 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1368 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1369 }, 1370 .irq = { 1371 .set = &evergreen_irq_set, 1372 .process = &evergreen_irq_process, 1373 }, 1374 .display = { 1375 .bandwidth_update = &evergreen_bandwidth_update, 1376 .get_vblank_counter = &evergreen_get_vblank_counter, 1377 .wait_for_vblank = &dce4_wait_for_vblank, 1378 .set_backlight_level = &atombios_set_backlight_level, 1379 .get_backlight_level = &atombios_get_backlight_level, 1380 }, 1381 .copy = { 1382 .blit = &r600_copy_cpdma, 1383 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1384 .dma = &evergreen_copy_dma, 1385 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1386 .copy = &evergreen_copy_dma, 1387 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1388 }, 1389 .surface = { 1390 .set_reg = r600_set_surface_reg, 1391 .clear_reg = r600_clear_surface_reg, 1392 }, 1393 .hpd = { 1394 .init = &evergreen_hpd_init, 1395 .fini = &evergreen_hpd_fini, 1396 .sense = &evergreen_hpd_sense, 1397 .set_polarity = &evergreen_hpd_set_polarity, 1398 }, 1399 .pm = { 1400 .misc = &evergreen_pm_misc, 1401 .prepare = &evergreen_pm_prepare, 1402 .finish = &evergreen_pm_finish, 1403 .init_profile = &r600_pm_init_profile, 1404 .get_dynpm_state = &r600_pm_get_dynpm_state, 1405 .get_engine_clock = &radeon_atom_get_engine_clock, 1406 .set_engine_clock = &radeon_atom_set_engine_clock, 1407 .get_memory_clock = &radeon_atom_get_memory_clock, 1408 .set_memory_clock = &radeon_atom_set_memory_clock, 1409 .get_pcie_lanes = &r600_get_pcie_lanes, 1410 .set_pcie_lanes = &r600_set_pcie_lanes, 1411 .set_clock_gating = NULL, 1412 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1413 .get_temperature = &evergreen_get_temp, 1414 }, 1415 .dpm = { 1416 .init = &cypress_dpm_init, 1417 .setup_asic = &cypress_dpm_setup_asic, 1418 .enable = &cypress_dpm_enable, 1419 .late_enable = &rv770_dpm_late_enable, 1420 .disable = &cypress_dpm_disable, 1421 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1422 .set_power_state = &cypress_dpm_set_power_state, 1423 .post_set_power_state = &r600_dpm_post_set_power_state, 1424 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1425 .fini = &cypress_dpm_fini, 1426 .get_sclk = &rv770_dpm_get_sclk, 1427 .get_mclk = &rv770_dpm_get_mclk, 1428 .print_power_state = &rv770_dpm_print_power_state, 1429 #ifdef CONFIG_DEBUG_FS 1430 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1431 #endif 1432 .force_performance_level = &rv770_dpm_force_performance_level, 1433 .vblank_too_short = &cypress_dpm_vblank_too_short, 1434 .get_current_sclk = &rv770_dpm_get_current_sclk, 1435 .get_current_mclk = &rv770_dpm_get_current_mclk, 1436 }, 1437 .pflip = { 1438 .page_flip = &evergreen_page_flip, 1439 .page_flip_pending = &evergreen_page_flip_pending, 1440 }, 1441 }; 1442 1443 static struct radeon_asic sumo_asic = { 1444 .init = &evergreen_init, 1445 .fini = &evergreen_fini, 1446 .suspend = &evergreen_suspend, 1447 .resume = &evergreen_resume, 1448 .asic_reset = &evergreen_asic_reset, 1449 .vga_set_state = &r600_vga_set_state, 1450 .mmio_hdp_flush = r600_mmio_hdp_flush, 1451 .gui_idle = &r600_gui_idle, 1452 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1453 .get_xclk = &r600_get_xclk, 1454 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1455 .get_allowed_info_register = evergreen_get_allowed_info_register, 1456 .gart = { 1457 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1458 .get_page_entry = &rs600_gart_get_page_entry, 1459 .set_page = &rs600_gart_set_page, 1460 }, 1461 .ring = { 1462 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1463 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1464 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1465 }, 1466 .irq = { 1467 .set = &evergreen_irq_set, 1468 .process = &evergreen_irq_process, 1469 }, 1470 .display = { 1471 .bandwidth_update = &evergreen_bandwidth_update, 1472 .get_vblank_counter = &evergreen_get_vblank_counter, 1473 .wait_for_vblank = &dce4_wait_for_vblank, 1474 .set_backlight_level = &atombios_set_backlight_level, 1475 .get_backlight_level = &atombios_get_backlight_level, 1476 }, 1477 .copy = { 1478 .blit = &r600_copy_cpdma, 1479 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1480 .dma = &evergreen_copy_dma, 1481 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1482 .copy = &evergreen_copy_dma, 1483 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1484 }, 1485 .surface = { 1486 .set_reg = r600_set_surface_reg, 1487 .clear_reg = r600_clear_surface_reg, 1488 }, 1489 .hpd = { 1490 .init = &evergreen_hpd_init, 1491 .fini = &evergreen_hpd_fini, 1492 .sense = &evergreen_hpd_sense, 1493 .set_polarity = &evergreen_hpd_set_polarity, 1494 }, 1495 .pm = { 1496 .misc = &evergreen_pm_misc, 1497 .prepare = &evergreen_pm_prepare, 1498 .finish = &evergreen_pm_finish, 1499 .init_profile = &sumo_pm_init_profile, 1500 .get_dynpm_state = &r600_pm_get_dynpm_state, 1501 .get_engine_clock = &radeon_atom_get_engine_clock, 1502 .set_engine_clock = &radeon_atom_set_engine_clock, 1503 .get_memory_clock = NULL, 1504 .set_memory_clock = NULL, 1505 .get_pcie_lanes = NULL, 1506 .set_pcie_lanes = NULL, 1507 .set_clock_gating = NULL, 1508 .set_uvd_clocks = &sumo_set_uvd_clocks, 1509 .get_temperature = &sumo_get_temp, 1510 }, 1511 .dpm = { 1512 .init = &sumo_dpm_init, 1513 .setup_asic = &sumo_dpm_setup_asic, 1514 .enable = &sumo_dpm_enable, 1515 .late_enable = &sumo_dpm_late_enable, 1516 .disable = &sumo_dpm_disable, 1517 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1518 .set_power_state = &sumo_dpm_set_power_state, 1519 .post_set_power_state = &sumo_dpm_post_set_power_state, 1520 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1521 .fini = &sumo_dpm_fini, 1522 .get_sclk = &sumo_dpm_get_sclk, 1523 .get_mclk = &sumo_dpm_get_mclk, 1524 .print_power_state = &sumo_dpm_print_power_state, 1525 #ifdef CONFIG_DEBUG_FS 1526 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1527 #endif 1528 .force_performance_level = &sumo_dpm_force_performance_level, 1529 .get_current_sclk = &sumo_dpm_get_current_sclk, 1530 .get_current_mclk = &sumo_dpm_get_current_mclk, 1531 }, 1532 .pflip = { 1533 .page_flip = &evergreen_page_flip, 1534 .page_flip_pending = &evergreen_page_flip_pending, 1535 }, 1536 }; 1537 1538 static struct radeon_asic btc_asic = { 1539 .init = &evergreen_init, 1540 .fini = &evergreen_fini, 1541 .suspend = &evergreen_suspend, 1542 .resume = &evergreen_resume, 1543 .asic_reset = &evergreen_asic_reset, 1544 .vga_set_state = &r600_vga_set_state, 1545 .mmio_hdp_flush = r600_mmio_hdp_flush, 1546 .gui_idle = &r600_gui_idle, 1547 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1548 .get_xclk = &rv770_get_xclk, 1549 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1550 .get_allowed_info_register = evergreen_get_allowed_info_register, 1551 .gart = { 1552 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1553 .get_page_entry = &rs600_gart_get_page_entry, 1554 .set_page = &rs600_gart_set_page, 1555 }, 1556 .ring = { 1557 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1558 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1559 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1560 }, 1561 .irq = { 1562 .set = &evergreen_irq_set, 1563 .process = &evergreen_irq_process, 1564 }, 1565 .display = { 1566 .bandwidth_update = &evergreen_bandwidth_update, 1567 .get_vblank_counter = &evergreen_get_vblank_counter, 1568 .wait_for_vblank = &dce4_wait_for_vblank, 1569 .set_backlight_level = &atombios_set_backlight_level, 1570 .get_backlight_level = &atombios_get_backlight_level, 1571 }, 1572 .copy = { 1573 .blit = &r600_copy_cpdma, 1574 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1575 .dma = &evergreen_copy_dma, 1576 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1577 .copy = &evergreen_copy_dma, 1578 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1579 }, 1580 .surface = { 1581 .set_reg = r600_set_surface_reg, 1582 .clear_reg = r600_clear_surface_reg, 1583 }, 1584 .hpd = { 1585 .init = &evergreen_hpd_init, 1586 .fini = &evergreen_hpd_fini, 1587 .sense = &evergreen_hpd_sense, 1588 .set_polarity = &evergreen_hpd_set_polarity, 1589 }, 1590 .pm = { 1591 .misc = &evergreen_pm_misc, 1592 .prepare = &evergreen_pm_prepare, 1593 .finish = &evergreen_pm_finish, 1594 .init_profile = &btc_pm_init_profile, 1595 .get_dynpm_state = &r600_pm_get_dynpm_state, 1596 .get_engine_clock = &radeon_atom_get_engine_clock, 1597 .set_engine_clock = &radeon_atom_set_engine_clock, 1598 .get_memory_clock = &radeon_atom_get_memory_clock, 1599 .set_memory_clock = &radeon_atom_set_memory_clock, 1600 .get_pcie_lanes = &r600_get_pcie_lanes, 1601 .set_pcie_lanes = &r600_set_pcie_lanes, 1602 .set_clock_gating = NULL, 1603 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1604 .get_temperature = &evergreen_get_temp, 1605 }, 1606 .dpm = { 1607 .init = &btc_dpm_init, 1608 .setup_asic = &btc_dpm_setup_asic, 1609 .enable = &btc_dpm_enable, 1610 .late_enable = &rv770_dpm_late_enable, 1611 .disable = &btc_dpm_disable, 1612 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1613 .set_power_state = &btc_dpm_set_power_state, 1614 .post_set_power_state = &btc_dpm_post_set_power_state, 1615 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1616 .fini = &btc_dpm_fini, 1617 .get_sclk = &btc_dpm_get_sclk, 1618 .get_mclk = &btc_dpm_get_mclk, 1619 .print_power_state = &rv770_dpm_print_power_state, 1620 #ifdef CONFIG_DEBUG_FS 1621 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1622 #endif 1623 .force_performance_level = &rv770_dpm_force_performance_level, 1624 .vblank_too_short = &btc_dpm_vblank_too_short, 1625 .get_current_sclk = &btc_dpm_get_current_sclk, 1626 .get_current_mclk = &btc_dpm_get_current_mclk, 1627 }, 1628 .pflip = { 1629 .page_flip = &evergreen_page_flip, 1630 .page_flip_pending = &evergreen_page_flip_pending, 1631 }, 1632 }; 1633 1634 static const struct radeon_asic_ring cayman_gfx_ring = { 1635 .ib_execute = &cayman_ring_ib_execute, 1636 .ib_parse = &evergreen_ib_parse, 1637 .emit_fence = &cayman_fence_ring_emit, 1638 .emit_semaphore = &r600_semaphore_ring_emit, 1639 .cs_parse = &evergreen_cs_parse, 1640 .ring_test = &r600_ring_test, 1641 .ib_test = &r600_ib_test, 1642 .is_lockup = &cayman_gfx_is_lockup, 1643 .vm_flush = &cayman_vm_flush, 1644 .get_rptr = &cayman_gfx_get_rptr, 1645 .get_wptr = &cayman_gfx_get_wptr, 1646 .set_wptr = &cayman_gfx_set_wptr, 1647 }; 1648 1649 static const struct radeon_asic_ring cayman_dma_ring = { 1650 .ib_execute = &cayman_dma_ring_ib_execute, 1651 .ib_parse = &evergreen_dma_ib_parse, 1652 .emit_fence = &evergreen_dma_fence_ring_emit, 1653 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1654 .cs_parse = &evergreen_dma_cs_parse, 1655 .ring_test = &r600_dma_ring_test, 1656 .ib_test = &r600_dma_ib_test, 1657 .is_lockup = &cayman_dma_is_lockup, 1658 .vm_flush = &cayman_dma_vm_flush, 1659 .get_rptr = &cayman_dma_get_rptr, 1660 .get_wptr = &cayman_dma_get_wptr, 1661 .set_wptr = &cayman_dma_set_wptr 1662 }; 1663 1664 static const struct radeon_asic_ring cayman_uvd_ring = { 1665 .ib_execute = &uvd_v1_0_ib_execute, 1666 .emit_fence = &uvd_v2_2_fence_emit, 1667 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1668 .cs_parse = &radeon_uvd_cs_parse, 1669 .ring_test = &uvd_v1_0_ring_test, 1670 .ib_test = &uvd_v1_0_ib_test, 1671 .is_lockup = &radeon_ring_test_lockup, 1672 .get_rptr = &uvd_v1_0_get_rptr, 1673 .get_wptr = &uvd_v1_0_get_wptr, 1674 .set_wptr = &uvd_v1_0_set_wptr, 1675 }; 1676 1677 static struct radeon_asic cayman_asic = { 1678 .init = &cayman_init, 1679 .fini = &cayman_fini, 1680 .suspend = &cayman_suspend, 1681 .resume = &cayman_resume, 1682 .asic_reset = &cayman_asic_reset, 1683 .vga_set_state = &r600_vga_set_state, 1684 .mmio_hdp_flush = r600_mmio_hdp_flush, 1685 .gui_idle = &r600_gui_idle, 1686 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1687 .get_xclk = &rv770_get_xclk, 1688 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1689 .get_allowed_info_register = cayman_get_allowed_info_register, 1690 .gart = { 1691 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1692 .get_page_entry = &rs600_gart_get_page_entry, 1693 .set_page = &rs600_gart_set_page, 1694 }, 1695 .vm = { 1696 .init = &cayman_vm_init, 1697 .fini = &cayman_vm_fini, 1698 .copy_pages = &cayman_dma_vm_copy_pages, 1699 .write_pages = &cayman_dma_vm_write_pages, 1700 .set_pages = &cayman_dma_vm_set_pages, 1701 .pad_ib = &cayman_dma_vm_pad_ib, 1702 }, 1703 .ring = { 1704 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1705 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1706 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1707 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1708 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1709 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1710 }, 1711 .irq = { 1712 .set = &evergreen_irq_set, 1713 .process = &evergreen_irq_process, 1714 }, 1715 .display = { 1716 .bandwidth_update = &evergreen_bandwidth_update, 1717 .get_vblank_counter = &evergreen_get_vblank_counter, 1718 .wait_for_vblank = &dce4_wait_for_vblank, 1719 .set_backlight_level = &atombios_set_backlight_level, 1720 .get_backlight_level = &atombios_get_backlight_level, 1721 }, 1722 .copy = { 1723 .blit = &r600_copy_cpdma, 1724 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1725 .dma = &evergreen_copy_dma, 1726 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1727 .copy = &evergreen_copy_dma, 1728 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1729 }, 1730 .surface = { 1731 .set_reg = r600_set_surface_reg, 1732 .clear_reg = r600_clear_surface_reg, 1733 }, 1734 .hpd = { 1735 .init = &evergreen_hpd_init, 1736 .fini = &evergreen_hpd_fini, 1737 .sense = &evergreen_hpd_sense, 1738 .set_polarity = &evergreen_hpd_set_polarity, 1739 }, 1740 .pm = { 1741 .misc = &evergreen_pm_misc, 1742 .prepare = &evergreen_pm_prepare, 1743 .finish = &evergreen_pm_finish, 1744 .init_profile = &btc_pm_init_profile, 1745 .get_dynpm_state = &r600_pm_get_dynpm_state, 1746 .get_engine_clock = &radeon_atom_get_engine_clock, 1747 .set_engine_clock = &radeon_atom_set_engine_clock, 1748 .get_memory_clock = &radeon_atom_get_memory_clock, 1749 .set_memory_clock = &radeon_atom_set_memory_clock, 1750 .get_pcie_lanes = &r600_get_pcie_lanes, 1751 .set_pcie_lanes = &r600_set_pcie_lanes, 1752 .set_clock_gating = NULL, 1753 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1754 .get_temperature = &evergreen_get_temp, 1755 }, 1756 .dpm = { 1757 .init = &ni_dpm_init, 1758 .setup_asic = &ni_dpm_setup_asic, 1759 .enable = &ni_dpm_enable, 1760 .late_enable = &rv770_dpm_late_enable, 1761 .disable = &ni_dpm_disable, 1762 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1763 .set_power_state = &ni_dpm_set_power_state, 1764 .post_set_power_state = &ni_dpm_post_set_power_state, 1765 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1766 .fini = &ni_dpm_fini, 1767 .get_sclk = &ni_dpm_get_sclk, 1768 .get_mclk = &ni_dpm_get_mclk, 1769 .print_power_state = &ni_dpm_print_power_state, 1770 #ifdef CONFIG_DEBUG_FS 1771 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1772 #endif 1773 .force_performance_level = &ni_dpm_force_performance_level, 1774 .vblank_too_short = &ni_dpm_vblank_too_short, 1775 .get_current_sclk = &ni_dpm_get_current_sclk, 1776 .get_current_mclk = &ni_dpm_get_current_mclk, 1777 }, 1778 .pflip = { 1779 .page_flip = &evergreen_page_flip, 1780 .page_flip_pending = &evergreen_page_flip_pending, 1781 }, 1782 }; 1783 1784 static const struct radeon_asic_ring trinity_vce_ring = { 1785 .ib_execute = &radeon_vce_ib_execute, 1786 .emit_fence = &radeon_vce_fence_emit, 1787 .emit_semaphore = &radeon_vce_semaphore_emit, 1788 .cs_parse = &radeon_vce_cs_parse, 1789 .ring_test = &radeon_vce_ring_test, 1790 .ib_test = &radeon_vce_ib_test, 1791 .is_lockup = &radeon_ring_test_lockup, 1792 .get_rptr = &vce_v1_0_get_rptr, 1793 .get_wptr = &vce_v1_0_get_wptr, 1794 .set_wptr = &vce_v1_0_set_wptr, 1795 }; 1796 1797 static struct radeon_asic trinity_asic = { 1798 .init = &cayman_init, 1799 .fini = &cayman_fini, 1800 .suspend = &cayman_suspend, 1801 .resume = &cayman_resume, 1802 .asic_reset = &cayman_asic_reset, 1803 .vga_set_state = &r600_vga_set_state, 1804 .mmio_hdp_flush = r600_mmio_hdp_flush, 1805 .gui_idle = &r600_gui_idle, 1806 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1807 .get_xclk = &r600_get_xclk, 1808 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1809 .get_allowed_info_register = cayman_get_allowed_info_register, 1810 .gart = { 1811 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1812 .get_page_entry = &rs600_gart_get_page_entry, 1813 .set_page = &rs600_gart_set_page, 1814 }, 1815 .vm = { 1816 .init = &cayman_vm_init, 1817 .fini = &cayman_vm_fini, 1818 .copy_pages = &cayman_dma_vm_copy_pages, 1819 .write_pages = &cayman_dma_vm_write_pages, 1820 .set_pages = &cayman_dma_vm_set_pages, 1821 .pad_ib = &cayman_dma_vm_pad_ib, 1822 }, 1823 .ring = { 1824 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1825 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1826 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1827 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1828 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1829 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1830 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1831 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1832 }, 1833 .irq = { 1834 .set = &evergreen_irq_set, 1835 .process = &evergreen_irq_process, 1836 }, 1837 .display = { 1838 .bandwidth_update = &dce6_bandwidth_update, 1839 .get_vblank_counter = &evergreen_get_vblank_counter, 1840 .wait_for_vblank = &dce4_wait_for_vblank, 1841 .set_backlight_level = &atombios_set_backlight_level, 1842 .get_backlight_level = &atombios_get_backlight_level, 1843 }, 1844 .copy = { 1845 .blit = &r600_copy_cpdma, 1846 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1847 .dma = &evergreen_copy_dma, 1848 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1849 .copy = &evergreen_copy_dma, 1850 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1851 }, 1852 .surface = { 1853 .set_reg = r600_set_surface_reg, 1854 .clear_reg = r600_clear_surface_reg, 1855 }, 1856 .hpd = { 1857 .init = &evergreen_hpd_init, 1858 .fini = &evergreen_hpd_fini, 1859 .sense = &evergreen_hpd_sense, 1860 .set_polarity = &evergreen_hpd_set_polarity, 1861 }, 1862 .pm = { 1863 .misc = &evergreen_pm_misc, 1864 .prepare = &evergreen_pm_prepare, 1865 .finish = &evergreen_pm_finish, 1866 .init_profile = &sumo_pm_init_profile, 1867 .get_dynpm_state = &r600_pm_get_dynpm_state, 1868 .get_engine_clock = &radeon_atom_get_engine_clock, 1869 .set_engine_clock = &radeon_atom_set_engine_clock, 1870 .get_memory_clock = NULL, 1871 .set_memory_clock = NULL, 1872 .get_pcie_lanes = NULL, 1873 .set_pcie_lanes = NULL, 1874 .set_clock_gating = NULL, 1875 .set_uvd_clocks = &sumo_set_uvd_clocks, 1876 .set_vce_clocks = &tn_set_vce_clocks, 1877 .get_temperature = &tn_get_temp, 1878 }, 1879 .dpm = { 1880 .init = &trinity_dpm_init, 1881 .setup_asic = &trinity_dpm_setup_asic, 1882 .enable = &trinity_dpm_enable, 1883 .late_enable = &trinity_dpm_late_enable, 1884 .disable = &trinity_dpm_disable, 1885 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1886 .set_power_state = &trinity_dpm_set_power_state, 1887 .post_set_power_state = &trinity_dpm_post_set_power_state, 1888 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1889 .fini = &trinity_dpm_fini, 1890 .get_sclk = &trinity_dpm_get_sclk, 1891 .get_mclk = &trinity_dpm_get_mclk, 1892 .print_power_state = &trinity_dpm_print_power_state, 1893 #ifdef CONFIG_DEBUG_FS 1894 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1895 #endif 1896 .force_performance_level = &trinity_dpm_force_performance_level, 1897 .enable_bapm = &trinity_dpm_enable_bapm, 1898 .get_current_sclk = &trinity_dpm_get_current_sclk, 1899 .get_current_mclk = &trinity_dpm_get_current_mclk, 1900 }, 1901 .pflip = { 1902 .page_flip = &evergreen_page_flip, 1903 .page_flip_pending = &evergreen_page_flip_pending, 1904 }, 1905 }; 1906 1907 static const struct radeon_asic_ring si_gfx_ring = { 1908 .ib_execute = &si_ring_ib_execute, 1909 .ib_parse = &si_ib_parse, 1910 .emit_fence = &si_fence_ring_emit, 1911 .emit_semaphore = &r600_semaphore_ring_emit, 1912 .cs_parse = NULL, 1913 .ring_test = &r600_ring_test, 1914 .ib_test = &r600_ib_test, 1915 .is_lockup = &si_gfx_is_lockup, 1916 .vm_flush = &si_vm_flush, 1917 .get_rptr = &cayman_gfx_get_rptr, 1918 .get_wptr = &cayman_gfx_get_wptr, 1919 .set_wptr = &cayman_gfx_set_wptr, 1920 }; 1921 1922 static const struct radeon_asic_ring si_dma_ring = { 1923 .ib_execute = &cayman_dma_ring_ib_execute, 1924 .ib_parse = &evergreen_dma_ib_parse, 1925 .emit_fence = &evergreen_dma_fence_ring_emit, 1926 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1927 .cs_parse = NULL, 1928 .ring_test = &r600_dma_ring_test, 1929 .ib_test = &r600_dma_ib_test, 1930 .is_lockup = &si_dma_is_lockup, 1931 .vm_flush = &si_dma_vm_flush, 1932 .get_rptr = &cayman_dma_get_rptr, 1933 .get_wptr = &cayman_dma_get_wptr, 1934 .set_wptr = &cayman_dma_set_wptr, 1935 }; 1936 1937 static struct radeon_asic si_asic = { 1938 .init = &si_init, 1939 .fini = &si_fini, 1940 .suspend = &si_suspend, 1941 .resume = &si_resume, 1942 .asic_reset = &si_asic_reset, 1943 .vga_set_state = &r600_vga_set_state, 1944 .mmio_hdp_flush = r600_mmio_hdp_flush, 1945 .gui_idle = &r600_gui_idle, 1946 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1947 .get_xclk = &si_get_xclk, 1948 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1949 .get_allowed_info_register = si_get_allowed_info_register, 1950 .gart = { 1951 .tlb_flush = &si_pcie_gart_tlb_flush, 1952 .get_page_entry = &rs600_gart_get_page_entry, 1953 .set_page = &rs600_gart_set_page, 1954 }, 1955 .vm = { 1956 .init = &si_vm_init, 1957 .fini = &si_vm_fini, 1958 .copy_pages = &si_dma_vm_copy_pages, 1959 .write_pages = &si_dma_vm_write_pages, 1960 .set_pages = &si_dma_vm_set_pages, 1961 .pad_ib = &cayman_dma_vm_pad_ib, 1962 }, 1963 .ring = { 1964 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1965 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1966 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1967 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1968 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1969 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1970 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1971 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1972 }, 1973 .irq = { 1974 .set = &si_irq_set, 1975 .process = &si_irq_process, 1976 }, 1977 .display = { 1978 .bandwidth_update = &dce6_bandwidth_update, 1979 .get_vblank_counter = &evergreen_get_vblank_counter, 1980 .wait_for_vblank = &dce4_wait_for_vblank, 1981 .set_backlight_level = &atombios_set_backlight_level, 1982 .get_backlight_level = &atombios_get_backlight_level, 1983 }, 1984 .copy = { 1985 .blit = &r600_copy_cpdma, 1986 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1987 .dma = &si_copy_dma, 1988 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1989 .copy = &si_copy_dma, 1990 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1991 }, 1992 .surface = { 1993 .set_reg = r600_set_surface_reg, 1994 .clear_reg = r600_clear_surface_reg, 1995 }, 1996 .hpd = { 1997 .init = &evergreen_hpd_init, 1998 .fini = &evergreen_hpd_fini, 1999 .sense = &evergreen_hpd_sense, 2000 .set_polarity = &evergreen_hpd_set_polarity, 2001 }, 2002 .pm = { 2003 .misc = &evergreen_pm_misc, 2004 .prepare = &evergreen_pm_prepare, 2005 .finish = &evergreen_pm_finish, 2006 .init_profile = &sumo_pm_init_profile, 2007 .get_dynpm_state = &r600_pm_get_dynpm_state, 2008 .get_engine_clock = &radeon_atom_get_engine_clock, 2009 .set_engine_clock = &radeon_atom_set_engine_clock, 2010 .get_memory_clock = &radeon_atom_get_memory_clock, 2011 .set_memory_clock = &radeon_atom_set_memory_clock, 2012 .get_pcie_lanes = &r600_get_pcie_lanes, 2013 .set_pcie_lanes = &r600_set_pcie_lanes, 2014 .set_clock_gating = NULL, 2015 .set_uvd_clocks = &si_set_uvd_clocks, 2016 .set_vce_clocks = &si_set_vce_clocks, 2017 .get_temperature = &si_get_temp, 2018 }, 2019 .dpm = { 2020 .init = &si_dpm_init, 2021 .setup_asic = &si_dpm_setup_asic, 2022 .enable = &si_dpm_enable, 2023 .late_enable = &si_dpm_late_enable, 2024 .disable = &si_dpm_disable, 2025 .pre_set_power_state = &si_dpm_pre_set_power_state, 2026 .set_power_state = &si_dpm_set_power_state, 2027 .post_set_power_state = &si_dpm_post_set_power_state, 2028 .display_configuration_changed = &si_dpm_display_configuration_changed, 2029 .fini = &si_dpm_fini, 2030 .get_sclk = &ni_dpm_get_sclk, 2031 .get_mclk = &ni_dpm_get_mclk, 2032 .print_power_state = &ni_dpm_print_power_state, 2033 #ifdef CONFIG_DEBUG_FS 2034 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2035 #endif 2036 .force_performance_level = &si_dpm_force_performance_level, 2037 .vblank_too_short = &ni_dpm_vblank_too_short, 2038 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, 2039 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, 2040 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, 2041 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, 2042 .get_current_sclk = &si_dpm_get_current_sclk, 2043 .get_current_mclk = &si_dpm_get_current_mclk, 2044 }, 2045 .pflip = { 2046 .page_flip = &evergreen_page_flip, 2047 .page_flip_pending = &evergreen_page_flip_pending, 2048 }, 2049 }; 2050 2051 static const struct radeon_asic_ring ci_gfx_ring = { 2052 .ib_execute = &cik_ring_ib_execute, 2053 .ib_parse = &cik_ib_parse, 2054 .emit_fence = &cik_fence_gfx_ring_emit, 2055 .emit_semaphore = &cik_semaphore_ring_emit, 2056 .cs_parse = NULL, 2057 .ring_test = &cik_ring_test, 2058 .ib_test = &cik_ib_test, 2059 .is_lockup = &cik_gfx_is_lockup, 2060 .vm_flush = &cik_vm_flush, 2061 .get_rptr = &cik_gfx_get_rptr, 2062 .get_wptr = &cik_gfx_get_wptr, 2063 .set_wptr = &cik_gfx_set_wptr, 2064 }; 2065 2066 static const struct radeon_asic_ring ci_cp_ring = { 2067 .ib_execute = &cik_ring_ib_execute, 2068 .ib_parse = &cik_ib_parse, 2069 .emit_fence = &cik_fence_compute_ring_emit, 2070 .emit_semaphore = &cik_semaphore_ring_emit, 2071 .cs_parse = NULL, 2072 .ring_test = &cik_ring_test, 2073 .ib_test = &cik_ib_test, 2074 .is_lockup = &cik_gfx_is_lockup, 2075 .vm_flush = &cik_vm_flush, 2076 .get_rptr = &cik_compute_get_rptr, 2077 .get_wptr = &cik_compute_get_wptr, 2078 .set_wptr = &cik_compute_set_wptr, 2079 }; 2080 2081 static const struct radeon_asic_ring ci_dma_ring = { 2082 .ib_execute = &cik_sdma_ring_ib_execute, 2083 .ib_parse = &cik_ib_parse, 2084 .emit_fence = &cik_sdma_fence_ring_emit, 2085 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2086 .cs_parse = NULL, 2087 .ring_test = &cik_sdma_ring_test, 2088 .ib_test = &cik_sdma_ib_test, 2089 .is_lockup = &cik_sdma_is_lockup, 2090 .vm_flush = &cik_dma_vm_flush, 2091 .get_rptr = &cik_sdma_get_rptr, 2092 .get_wptr = &cik_sdma_get_wptr, 2093 .set_wptr = &cik_sdma_set_wptr, 2094 }; 2095 2096 static const struct radeon_asic_ring ci_vce_ring = { 2097 .ib_execute = &radeon_vce_ib_execute, 2098 .emit_fence = &radeon_vce_fence_emit, 2099 .emit_semaphore = &radeon_vce_semaphore_emit, 2100 .cs_parse = &radeon_vce_cs_parse, 2101 .ring_test = &radeon_vce_ring_test, 2102 .ib_test = &radeon_vce_ib_test, 2103 .is_lockup = &radeon_ring_test_lockup, 2104 .get_rptr = &vce_v1_0_get_rptr, 2105 .get_wptr = &vce_v1_0_get_wptr, 2106 .set_wptr = &vce_v1_0_set_wptr, 2107 }; 2108 2109 static struct radeon_asic ci_asic = { 2110 .init = &cik_init, 2111 .fini = &cik_fini, 2112 .suspend = &cik_suspend, 2113 .resume = &cik_resume, 2114 .asic_reset = &cik_asic_reset, 2115 .vga_set_state = &r600_vga_set_state, 2116 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2117 .gui_idle = &r600_gui_idle, 2118 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2119 .get_xclk = &cik_get_xclk, 2120 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2121 .get_allowed_info_register = cik_get_allowed_info_register, 2122 .gart = { 2123 .tlb_flush = &cik_pcie_gart_tlb_flush, 2124 .get_page_entry = &rs600_gart_get_page_entry, 2125 .set_page = &rs600_gart_set_page, 2126 }, 2127 .vm = { 2128 .init = &cik_vm_init, 2129 .fini = &cik_vm_fini, 2130 .copy_pages = &cik_sdma_vm_copy_pages, 2131 .write_pages = &cik_sdma_vm_write_pages, 2132 .set_pages = &cik_sdma_vm_set_pages, 2133 .pad_ib = &cik_sdma_vm_pad_ib, 2134 }, 2135 .ring = { 2136 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2137 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2138 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2139 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2140 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2141 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2142 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2143 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2144 }, 2145 .irq = { 2146 .set = &cik_irq_set, 2147 .process = &cik_irq_process, 2148 }, 2149 .display = { 2150 .bandwidth_update = &dce8_bandwidth_update, 2151 .get_vblank_counter = &evergreen_get_vblank_counter, 2152 .wait_for_vblank = &dce4_wait_for_vblank, 2153 .set_backlight_level = &atombios_set_backlight_level, 2154 .get_backlight_level = &atombios_get_backlight_level, 2155 }, 2156 .copy = { 2157 .blit = &cik_copy_cpdma, 2158 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2159 .dma = &cik_copy_dma, 2160 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2161 .copy = &cik_copy_dma, 2162 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2163 }, 2164 .surface = { 2165 .set_reg = r600_set_surface_reg, 2166 .clear_reg = r600_clear_surface_reg, 2167 }, 2168 .hpd = { 2169 .init = &evergreen_hpd_init, 2170 .fini = &evergreen_hpd_fini, 2171 .sense = &evergreen_hpd_sense, 2172 .set_polarity = &evergreen_hpd_set_polarity, 2173 }, 2174 .pm = { 2175 .misc = &evergreen_pm_misc, 2176 .prepare = &evergreen_pm_prepare, 2177 .finish = &evergreen_pm_finish, 2178 .init_profile = &sumo_pm_init_profile, 2179 .get_dynpm_state = &r600_pm_get_dynpm_state, 2180 .get_engine_clock = &radeon_atom_get_engine_clock, 2181 .set_engine_clock = &radeon_atom_set_engine_clock, 2182 .get_memory_clock = &radeon_atom_get_memory_clock, 2183 .set_memory_clock = &radeon_atom_set_memory_clock, 2184 .get_pcie_lanes = NULL, 2185 .set_pcie_lanes = NULL, 2186 .set_clock_gating = NULL, 2187 .set_uvd_clocks = &cik_set_uvd_clocks, 2188 .set_vce_clocks = &cik_set_vce_clocks, 2189 .get_temperature = &ci_get_temp, 2190 }, 2191 .dpm = { 2192 .init = &ci_dpm_init, 2193 .setup_asic = &ci_dpm_setup_asic, 2194 .enable = &ci_dpm_enable, 2195 .late_enable = &ci_dpm_late_enable, 2196 .disable = &ci_dpm_disable, 2197 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2198 .set_power_state = &ci_dpm_set_power_state, 2199 .post_set_power_state = &ci_dpm_post_set_power_state, 2200 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2201 .fini = &ci_dpm_fini, 2202 .get_sclk = &ci_dpm_get_sclk, 2203 .get_mclk = &ci_dpm_get_mclk, 2204 .print_power_state = &ci_dpm_print_power_state, 2205 #ifdef CONFIG_DEBUG_FS 2206 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2207 #endif 2208 .force_performance_level = &ci_dpm_force_performance_level, 2209 .vblank_too_short = &ci_dpm_vblank_too_short, 2210 .powergate_uvd = &ci_dpm_powergate_uvd, 2211 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, 2212 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, 2213 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, 2214 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, 2215 .get_current_sclk = &ci_dpm_get_current_sclk, 2216 .get_current_mclk = &ci_dpm_get_current_mclk, 2217 }, 2218 .pflip = { 2219 .page_flip = &evergreen_page_flip, 2220 .page_flip_pending = &evergreen_page_flip_pending, 2221 }, 2222 }; 2223 2224 static struct radeon_asic kv_asic = { 2225 .init = &cik_init, 2226 .fini = &cik_fini, 2227 .suspend = &cik_suspend, 2228 .resume = &cik_resume, 2229 .asic_reset = &cik_asic_reset, 2230 .vga_set_state = &r600_vga_set_state, 2231 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2232 .gui_idle = &r600_gui_idle, 2233 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2234 .get_xclk = &cik_get_xclk, 2235 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2236 .get_allowed_info_register = cik_get_allowed_info_register, 2237 .gart = { 2238 .tlb_flush = &cik_pcie_gart_tlb_flush, 2239 .get_page_entry = &rs600_gart_get_page_entry, 2240 .set_page = &rs600_gart_set_page, 2241 }, 2242 .vm = { 2243 .init = &cik_vm_init, 2244 .fini = &cik_vm_fini, 2245 .copy_pages = &cik_sdma_vm_copy_pages, 2246 .write_pages = &cik_sdma_vm_write_pages, 2247 .set_pages = &cik_sdma_vm_set_pages, 2248 .pad_ib = &cik_sdma_vm_pad_ib, 2249 }, 2250 .ring = { 2251 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2252 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2253 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2254 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2255 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2256 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2257 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2258 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2259 }, 2260 .irq = { 2261 .set = &cik_irq_set, 2262 .process = &cik_irq_process, 2263 }, 2264 .display = { 2265 .bandwidth_update = &dce8_bandwidth_update, 2266 .get_vblank_counter = &evergreen_get_vblank_counter, 2267 .wait_for_vblank = &dce4_wait_for_vblank, 2268 .set_backlight_level = &atombios_set_backlight_level, 2269 .get_backlight_level = &atombios_get_backlight_level, 2270 }, 2271 .copy = { 2272 .blit = &cik_copy_cpdma, 2273 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2274 .dma = &cik_copy_dma, 2275 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2276 .copy = &cik_copy_dma, 2277 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2278 }, 2279 .surface = { 2280 .set_reg = r600_set_surface_reg, 2281 .clear_reg = r600_clear_surface_reg, 2282 }, 2283 .hpd = { 2284 .init = &evergreen_hpd_init, 2285 .fini = &evergreen_hpd_fini, 2286 .sense = &evergreen_hpd_sense, 2287 .set_polarity = &evergreen_hpd_set_polarity, 2288 }, 2289 .pm = { 2290 .misc = &evergreen_pm_misc, 2291 .prepare = &evergreen_pm_prepare, 2292 .finish = &evergreen_pm_finish, 2293 .init_profile = &sumo_pm_init_profile, 2294 .get_dynpm_state = &r600_pm_get_dynpm_state, 2295 .get_engine_clock = &radeon_atom_get_engine_clock, 2296 .set_engine_clock = &radeon_atom_set_engine_clock, 2297 .get_memory_clock = &radeon_atom_get_memory_clock, 2298 .set_memory_clock = &radeon_atom_set_memory_clock, 2299 .get_pcie_lanes = NULL, 2300 .set_pcie_lanes = NULL, 2301 .set_clock_gating = NULL, 2302 .set_uvd_clocks = &cik_set_uvd_clocks, 2303 .set_vce_clocks = &cik_set_vce_clocks, 2304 .get_temperature = &kv_get_temp, 2305 }, 2306 .dpm = { 2307 .init = &kv_dpm_init, 2308 .setup_asic = &kv_dpm_setup_asic, 2309 .enable = &kv_dpm_enable, 2310 .late_enable = &kv_dpm_late_enable, 2311 .disable = &kv_dpm_disable, 2312 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2313 .set_power_state = &kv_dpm_set_power_state, 2314 .post_set_power_state = &kv_dpm_post_set_power_state, 2315 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2316 .fini = &kv_dpm_fini, 2317 .get_sclk = &kv_dpm_get_sclk, 2318 .get_mclk = &kv_dpm_get_mclk, 2319 .print_power_state = &kv_dpm_print_power_state, 2320 #ifdef CONFIG_DEBUG_FS 2321 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2322 #endif 2323 .force_performance_level = &kv_dpm_force_performance_level, 2324 .powergate_uvd = &kv_dpm_powergate_uvd, 2325 .enable_bapm = &kv_dpm_enable_bapm, 2326 .get_current_sclk = &kv_dpm_get_current_sclk, 2327 .get_current_mclk = &kv_dpm_get_current_mclk, 2328 }, 2329 .pflip = { 2330 .page_flip = &evergreen_page_flip, 2331 .page_flip_pending = &evergreen_page_flip_pending, 2332 }, 2333 }; 2334 2335 /** 2336 * radeon_asic_init - register asic specific callbacks 2337 * 2338 * @rdev: radeon device pointer 2339 * 2340 * Registers the appropriate asic specific callbacks for each 2341 * chip family. Also sets other asics specific info like the number 2342 * of crtcs and the register aperture accessors (all asics). 2343 * Returns 0 for success. 2344 */ 2345 int radeon_asic_init(struct radeon_device *rdev) 2346 { 2347 radeon_register_accessor_init(rdev); 2348 2349 /* set the number of crtcs */ 2350 if (rdev->flags & RADEON_SINGLE_CRTC) 2351 rdev->num_crtc = 1; 2352 else 2353 rdev->num_crtc = 2; 2354 2355 rdev->has_uvd = false; 2356 rdev->has_vce = false; 2357 2358 switch (rdev->family) { 2359 case CHIP_R100: 2360 case CHIP_RV100: 2361 case CHIP_RS100: 2362 case CHIP_RV200: 2363 case CHIP_RS200: 2364 rdev->asic = &r100_asic; 2365 break; 2366 case CHIP_R200: 2367 case CHIP_RV250: 2368 case CHIP_RS300: 2369 case CHIP_RV280: 2370 rdev->asic = &r200_asic; 2371 break; 2372 case CHIP_R300: 2373 case CHIP_R350: 2374 case CHIP_RV350: 2375 case CHIP_RV380: 2376 if (rdev->flags & RADEON_IS_PCIE) 2377 rdev->asic = &r300_asic_pcie; 2378 else 2379 rdev->asic = &r300_asic; 2380 break; 2381 case CHIP_R420: 2382 case CHIP_R423: 2383 case CHIP_RV410: 2384 rdev->asic = &r420_asic; 2385 /* handle macs */ 2386 if (rdev->bios == NULL) { 2387 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2388 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2389 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2390 rdev->asic->pm.set_memory_clock = NULL; 2391 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2392 } 2393 break; 2394 case CHIP_RS400: 2395 case CHIP_RS480: 2396 rdev->asic = &rs400_asic; 2397 break; 2398 case CHIP_RS600: 2399 rdev->asic = &rs600_asic; 2400 break; 2401 case CHIP_RS690: 2402 case CHIP_RS740: 2403 rdev->asic = &rs690_asic; 2404 break; 2405 case CHIP_RV515: 2406 rdev->asic = &rv515_asic; 2407 break; 2408 case CHIP_R520: 2409 case CHIP_RV530: 2410 case CHIP_RV560: 2411 case CHIP_RV570: 2412 case CHIP_R580: 2413 rdev->asic = &r520_asic; 2414 break; 2415 case CHIP_R600: 2416 rdev->asic = &r600_asic; 2417 break; 2418 case CHIP_RV610: 2419 case CHIP_RV630: 2420 case CHIP_RV620: 2421 case CHIP_RV635: 2422 case CHIP_RV670: 2423 rdev->asic = &rv6xx_asic; 2424 rdev->has_uvd = true; 2425 break; 2426 case CHIP_RS780: 2427 case CHIP_RS880: 2428 rdev->asic = &rs780_asic; 2429 /* 760G/780V/880V don't have UVD */ 2430 if ((rdev->pdev->device == 0x9616)|| 2431 (rdev->pdev->device == 0x9611)|| 2432 (rdev->pdev->device == 0x9613)|| 2433 (rdev->pdev->device == 0x9711)|| 2434 (rdev->pdev->device == 0x9713)) 2435 rdev->has_uvd = false; 2436 else 2437 rdev->has_uvd = true; 2438 break; 2439 case CHIP_RV770: 2440 case CHIP_RV730: 2441 case CHIP_RV710: 2442 case CHIP_RV740: 2443 rdev->asic = &rv770_asic; 2444 rdev->has_uvd = true; 2445 break; 2446 case CHIP_CEDAR: 2447 case CHIP_REDWOOD: 2448 case CHIP_JUNIPER: 2449 case CHIP_CYPRESS: 2450 case CHIP_HEMLOCK: 2451 /* set num crtcs */ 2452 if (rdev->family == CHIP_CEDAR) 2453 rdev->num_crtc = 4; 2454 else 2455 rdev->num_crtc = 6; 2456 rdev->asic = &evergreen_asic; 2457 rdev->has_uvd = true; 2458 break; 2459 case CHIP_PALM: 2460 case CHIP_SUMO: 2461 case CHIP_SUMO2: 2462 rdev->asic = &sumo_asic; 2463 rdev->has_uvd = true; 2464 break; 2465 case CHIP_BARTS: 2466 case CHIP_TURKS: 2467 case CHIP_CAICOS: 2468 /* set num crtcs */ 2469 if (rdev->family == CHIP_CAICOS) 2470 rdev->num_crtc = 4; 2471 else 2472 rdev->num_crtc = 6; 2473 rdev->asic = &btc_asic; 2474 rdev->has_uvd = true; 2475 break; 2476 case CHIP_CAYMAN: 2477 rdev->asic = &cayman_asic; 2478 /* set num crtcs */ 2479 rdev->num_crtc = 6; 2480 rdev->has_uvd = true; 2481 break; 2482 case CHIP_ARUBA: 2483 rdev->asic = &trinity_asic; 2484 /* set num crtcs */ 2485 rdev->num_crtc = 4; 2486 rdev->has_uvd = true; 2487 rdev->has_vce = true; 2488 rdev->cg_flags = 2489 RADEON_CG_SUPPORT_VCE_MGCG; 2490 break; 2491 case CHIP_TAHITI: 2492 case CHIP_PITCAIRN: 2493 case CHIP_VERDE: 2494 case CHIP_OLAND: 2495 case CHIP_HAINAN: 2496 rdev->asic = &si_asic; 2497 /* set num crtcs */ 2498 if (rdev->family == CHIP_HAINAN) 2499 rdev->num_crtc = 0; 2500 else if (rdev->family == CHIP_OLAND) 2501 rdev->num_crtc = 2; 2502 else 2503 rdev->num_crtc = 6; 2504 if (rdev->family == CHIP_HAINAN) { 2505 rdev->has_uvd = false; 2506 rdev->has_vce = false; 2507 } else { 2508 rdev->has_uvd = true; 2509 rdev->has_vce = true; 2510 } 2511 switch (rdev->family) { 2512 case CHIP_TAHITI: 2513 rdev->cg_flags = 2514 RADEON_CG_SUPPORT_GFX_MGCG | 2515 RADEON_CG_SUPPORT_GFX_MGLS | 2516 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2517 RADEON_CG_SUPPORT_GFX_CGLS | 2518 RADEON_CG_SUPPORT_GFX_CGTS | 2519 RADEON_CG_SUPPORT_GFX_CP_LS | 2520 RADEON_CG_SUPPORT_MC_MGCG | 2521 RADEON_CG_SUPPORT_SDMA_MGCG | 2522 RADEON_CG_SUPPORT_BIF_LS | 2523 RADEON_CG_SUPPORT_VCE_MGCG | 2524 RADEON_CG_SUPPORT_UVD_MGCG | 2525 RADEON_CG_SUPPORT_HDP_LS | 2526 RADEON_CG_SUPPORT_HDP_MGCG; 2527 rdev->pg_flags = 0; 2528 break; 2529 case CHIP_PITCAIRN: 2530 rdev->cg_flags = 2531 RADEON_CG_SUPPORT_GFX_MGCG | 2532 RADEON_CG_SUPPORT_GFX_MGLS | 2533 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2534 RADEON_CG_SUPPORT_GFX_CGLS | 2535 RADEON_CG_SUPPORT_GFX_CGTS | 2536 RADEON_CG_SUPPORT_GFX_CP_LS | 2537 RADEON_CG_SUPPORT_GFX_RLC_LS | 2538 RADEON_CG_SUPPORT_MC_LS | 2539 RADEON_CG_SUPPORT_MC_MGCG | 2540 RADEON_CG_SUPPORT_SDMA_MGCG | 2541 RADEON_CG_SUPPORT_BIF_LS | 2542 RADEON_CG_SUPPORT_VCE_MGCG | 2543 RADEON_CG_SUPPORT_UVD_MGCG | 2544 RADEON_CG_SUPPORT_HDP_LS | 2545 RADEON_CG_SUPPORT_HDP_MGCG; 2546 rdev->pg_flags = 0; 2547 break; 2548 case CHIP_VERDE: 2549 rdev->cg_flags = 2550 RADEON_CG_SUPPORT_GFX_MGCG | 2551 RADEON_CG_SUPPORT_GFX_MGLS | 2552 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2553 RADEON_CG_SUPPORT_GFX_CGLS | 2554 RADEON_CG_SUPPORT_GFX_CGTS | 2555 RADEON_CG_SUPPORT_GFX_CP_LS | 2556 RADEON_CG_SUPPORT_GFX_RLC_LS | 2557 RADEON_CG_SUPPORT_MC_LS | 2558 RADEON_CG_SUPPORT_MC_MGCG | 2559 RADEON_CG_SUPPORT_SDMA_MGCG | 2560 RADEON_CG_SUPPORT_BIF_LS | 2561 RADEON_CG_SUPPORT_VCE_MGCG | 2562 RADEON_CG_SUPPORT_UVD_MGCG | 2563 RADEON_CG_SUPPORT_HDP_LS | 2564 RADEON_CG_SUPPORT_HDP_MGCG; 2565 rdev->pg_flags = 0 | 2566 /*RADEON_PG_SUPPORT_GFX_PG | */ 2567 RADEON_PG_SUPPORT_SDMA; 2568 break; 2569 case CHIP_OLAND: 2570 rdev->cg_flags = 2571 RADEON_CG_SUPPORT_GFX_MGCG | 2572 RADEON_CG_SUPPORT_GFX_MGLS | 2573 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2574 RADEON_CG_SUPPORT_GFX_CGLS | 2575 RADEON_CG_SUPPORT_GFX_CGTS | 2576 RADEON_CG_SUPPORT_GFX_CP_LS | 2577 RADEON_CG_SUPPORT_GFX_RLC_LS | 2578 RADEON_CG_SUPPORT_MC_LS | 2579 RADEON_CG_SUPPORT_MC_MGCG | 2580 RADEON_CG_SUPPORT_SDMA_MGCG | 2581 RADEON_CG_SUPPORT_BIF_LS | 2582 RADEON_CG_SUPPORT_UVD_MGCG | 2583 RADEON_CG_SUPPORT_HDP_LS | 2584 RADEON_CG_SUPPORT_HDP_MGCG; 2585 rdev->pg_flags = 0; 2586 break; 2587 case CHIP_HAINAN: 2588 rdev->cg_flags = 2589 RADEON_CG_SUPPORT_GFX_MGCG | 2590 RADEON_CG_SUPPORT_GFX_MGLS | 2591 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2592 RADEON_CG_SUPPORT_GFX_CGLS | 2593 RADEON_CG_SUPPORT_GFX_CGTS | 2594 RADEON_CG_SUPPORT_GFX_CP_LS | 2595 RADEON_CG_SUPPORT_GFX_RLC_LS | 2596 RADEON_CG_SUPPORT_MC_LS | 2597 RADEON_CG_SUPPORT_MC_MGCG | 2598 RADEON_CG_SUPPORT_SDMA_MGCG | 2599 RADEON_CG_SUPPORT_BIF_LS | 2600 RADEON_CG_SUPPORT_HDP_LS | 2601 RADEON_CG_SUPPORT_HDP_MGCG; 2602 rdev->pg_flags = 0; 2603 break; 2604 default: 2605 rdev->cg_flags = 0; 2606 rdev->pg_flags = 0; 2607 break; 2608 } 2609 break; 2610 case CHIP_BONAIRE: 2611 case CHIP_HAWAII: 2612 rdev->asic = &ci_asic; 2613 rdev->num_crtc = 6; 2614 rdev->has_uvd = true; 2615 rdev->has_vce = true; 2616 if (rdev->family == CHIP_BONAIRE) { 2617 rdev->cg_flags = 2618 RADEON_CG_SUPPORT_GFX_MGCG | 2619 RADEON_CG_SUPPORT_GFX_MGLS | 2620 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2621 RADEON_CG_SUPPORT_GFX_CGLS | 2622 RADEON_CG_SUPPORT_GFX_CGTS | 2623 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2624 RADEON_CG_SUPPORT_GFX_CP_LS | 2625 RADEON_CG_SUPPORT_MC_LS | 2626 RADEON_CG_SUPPORT_MC_MGCG | 2627 RADEON_CG_SUPPORT_SDMA_MGCG | 2628 RADEON_CG_SUPPORT_SDMA_LS | 2629 RADEON_CG_SUPPORT_BIF_LS | 2630 RADEON_CG_SUPPORT_VCE_MGCG | 2631 RADEON_CG_SUPPORT_UVD_MGCG | 2632 RADEON_CG_SUPPORT_HDP_LS | 2633 RADEON_CG_SUPPORT_HDP_MGCG; 2634 rdev->pg_flags = 0; 2635 } else { 2636 rdev->cg_flags = 2637 RADEON_CG_SUPPORT_GFX_MGCG | 2638 RADEON_CG_SUPPORT_GFX_MGLS | 2639 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2640 RADEON_CG_SUPPORT_GFX_CGLS | 2641 RADEON_CG_SUPPORT_GFX_CGTS | 2642 RADEON_CG_SUPPORT_GFX_CP_LS | 2643 RADEON_CG_SUPPORT_MC_LS | 2644 RADEON_CG_SUPPORT_MC_MGCG | 2645 RADEON_CG_SUPPORT_SDMA_MGCG | 2646 RADEON_CG_SUPPORT_SDMA_LS | 2647 RADEON_CG_SUPPORT_BIF_LS | 2648 RADEON_CG_SUPPORT_VCE_MGCG | 2649 RADEON_CG_SUPPORT_UVD_MGCG | 2650 RADEON_CG_SUPPORT_HDP_LS | 2651 RADEON_CG_SUPPORT_HDP_MGCG; 2652 rdev->pg_flags = 0; 2653 } 2654 break; 2655 case CHIP_KAVERI: 2656 case CHIP_KABINI: 2657 case CHIP_MULLINS: 2658 rdev->asic = &kv_asic; 2659 /* set num crtcs */ 2660 if (rdev->family == CHIP_KAVERI) { 2661 rdev->num_crtc = 4; 2662 rdev->cg_flags = 2663 RADEON_CG_SUPPORT_GFX_MGCG | 2664 RADEON_CG_SUPPORT_GFX_MGLS | 2665 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2666 RADEON_CG_SUPPORT_GFX_CGLS | 2667 RADEON_CG_SUPPORT_GFX_CGTS | 2668 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2669 RADEON_CG_SUPPORT_GFX_CP_LS | 2670 RADEON_CG_SUPPORT_SDMA_MGCG | 2671 RADEON_CG_SUPPORT_SDMA_LS | 2672 RADEON_CG_SUPPORT_BIF_LS | 2673 RADEON_CG_SUPPORT_VCE_MGCG | 2674 RADEON_CG_SUPPORT_UVD_MGCG | 2675 RADEON_CG_SUPPORT_HDP_LS | 2676 RADEON_CG_SUPPORT_HDP_MGCG; 2677 rdev->pg_flags = 0; 2678 /*RADEON_PG_SUPPORT_GFX_PG | 2679 RADEON_PG_SUPPORT_GFX_SMG | 2680 RADEON_PG_SUPPORT_GFX_DMG | 2681 RADEON_PG_SUPPORT_UVD | 2682 RADEON_PG_SUPPORT_VCE | 2683 RADEON_PG_SUPPORT_CP | 2684 RADEON_PG_SUPPORT_GDS | 2685 RADEON_PG_SUPPORT_RLC_SMU_HS | 2686 RADEON_PG_SUPPORT_ACP | 2687 RADEON_PG_SUPPORT_SAMU;*/ 2688 } else { 2689 rdev->num_crtc = 2; 2690 rdev->cg_flags = 2691 RADEON_CG_SUPPORT_GFX_MGCG | 2692 RADEON_CG_SUPPORT_GFX_MGLS | 2693 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2694 RADEON_CG_SUPPORT_GFX_CGLS | 2695 RADEON_CG_SUPPORT_GFX_CGTS | 2696 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2697 RADEON_CG_SUPPORT_GFX_CP_LS | 2698 RADEON_CG_SUPPORT_SDMA_MGCG | 2699 RADEON_CG_SUPPORT_SDMA_LS | 2700 RADEON_CG_SUPPORT_BIF_LS | 2701 RADEON_CG_SUPPORT_VCE_MGCG | 2702 RADEON_CG_SUPPORT_UVD_MGCG | 2703 RADEON_CG_SUPPORT_HDP_LS | 2704 RADEON_CG_SUPPORT_HDP_MGCG; 2705 rdev->pg_flags = 0; 2706 /*RADEON_PG_SUPPORT_GFX_PG | 2707 RADEON_PG_SUPPORT_GFX_SMG | 2708 RADEON_PG_SUPPORT_UVD | 2709 RADEON_PG_SUPPORT_VCE | 2710 RADEON_PG_SUPPORT_CP | 2711 RADEON_PG_SUPPORT_GDS | 2712 RADEON_PG_SUPPORT_RLC_SMU_HS | 2713 RADEON_PG_SUPPORT_SAMU;*/ 2714 } 2715 rdev->has_uvd = true; 2716 rdev->has_vce = true; 2717 break; 2718 default: 2719 /* FIXME: not supported yet */ 2720 return -EINVAL; 2721 } 2722 2723 if (rdev->flags & RADEON_IS_IGP) { 2724 rdev->asic->pm.get_memory_clock = NULL; 2725 rdev->asic->pm.set_memory_clock = NULL; 2726 } 2727 2728 if (!radeon_uvd) 2729 rdev->has_uvd = false; 2730 if (!radeon_vce) 2731 rdev->has_vce = false; 2732 2733 return 0; 2734 } 2735 2736
Indexes created Sat Sep 20 22:09:52 GMT 2025