radeon_asic.c revision 1.1.1.3
1 /* $NetBSD: radeon_asic.c,v 1.1.1.3 2021/12/18 20:15:45 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_asic.c,v 1.1.1.3 2021/12/18 20:15:45 riastradh Exp $"); 33 34 #include <linux/console.h> 35 #include <linux/pci.h> 36 #include <linux/vgaarb.h> 37 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/radeon_drm.h> 40 41 #include "atom.h" 42 #include "radeon.h" 43 #include "radeon_asic.h" 44 #include "radeon_reg.h" 45 46 /* 47 * Registers accessors functions. 48 */ 49 /** 50 * radeon_invalid_rreg - dummy reg read function 51 * 52 * @rdev: radeon device pointer 53 * @reg: offset of register 54 * 55 * Dummy register read function. Used for register blocks 56 * that certain asics don't have (all asics). 57 * Returns the value in the register. 58 */ 59 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 60 { 61 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 62 BUG_ON(1); 63 return 0; 64 } 65 66 /** 67 * radeon_invalid_wreg - dummy reg write function 68 * 69 * @rdev: radeon device pointer 70 * @reg: offset of register 71 * @v: value to write to the register 72 * 73 * Dummy register read function. Used for register blocks 74 * that certain asics don't have (all asics). 75 */ 76 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 77 { 78 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 79 reg, v); 80 BUG_ON(1); 81 } 82 83 /** 84 * radeon_register_accessor_init - sets up the register accessor callbacks 85 * 86 * @rdev: radeon device pointer 87 * 88 * Sets up the register accessor callbacks for various register 89 * apertures. Not all asics have all apertures (all asics). 90 */ 91 static void radeon_register_accessor_init(struct radeon_device *rdev) 92 { 93 rdev->mc_rreg = &radeon_invalid_rreg; 94 rdev->mc_wreg = &radeon_invalid_wreg; 95 rdev->pll_rreg = &radeon_invalid_rreg; 96 rdev->pll_wreg = &radeon_invalid_wreg; 97 rdev->pciep_rreg = &radeon_invalid_rreg; 98 rdev->pciep_wreg = &radeon_invalid_wreg; 99 100 /* Don't change order as we are overridding accessor. */ 101 if (rdev->family < CHIP_RV515) { 102 rdev->pcie_reg_mask = 0xff; 103 } else { 104 rdev->pcie_reg_mask = 0x7ff; 105 } 106 /* FIXME: not sure here */ 107 if (rdev->family <= CHIP_R580) { 108 rdev->pll_rreg = &r100_pll_rreg; 109 rdev->pll_wreg = &r100_pll_wreg; 110 } 111 if (rdev->family >= CHIP_R420) { 112 rdev->mc_rreg = &r420_mc_rreg; 113 rdev->mc_wreg = &r420_mc_wreg; 114 } 115 if (rdev->family >= CHIP_RV515) { 116 rdev->mc_rreg = &rv515_mc_rreg; 117 rdev->mc_wreg = &rv515_mc_wreg; 118 } 119 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 120 rdev->mc_rreg = &rs400_mc_rreg; 121 rdev->mc_wreg = &rs400_mc_wreg; 122 } 123 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 124 rdev->mc_rreg = &rs690_mc_rreg; 125 rdev->mc_wreg = &rs690_mc_wreg; 126 } 127 if (rdev->family == CHIP_RS600) { 128 rdev->mc_rreg = &rs600_mc_rreg; 129 rdev->mc_wreg = &rs600_mc_wreg; 130 } 131 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 132 rdev->mc_rreg = &rs780_mc_rreg; 133 rdev->mc_wreg = &rs780_mc_wreg; 134 } 135 136 if (rdev->family >= CHIP_BONAIRE) { 137 rdev->pciep_rreg = &cik_pciep_rreg; 138 rdev->pciep_wreg = &cik_pciep_wreg; 139 } else if (rdev->family >= CHIP_R600) { 140 rdev->pciep_rreg = &r600_pciep_rreg; 141 rdev->pciep_wreg = &r600_pciep_wreg; 142 } 143 } 144 145 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, 146 u32 reg, u32 *val) 147 { 148 return -EINVAL; 149 } 150 151 /* helper to disable agp */ 152 /** 153 * radeon_agp_disable - AGP disable helper function 154 * 155 * @rdev: radeon device pointer 156 * 157 * Removes AGP flags and changes the gart callbacks on AGP 158 * cards when using the internal gart rather than AGP (all asics). 159 */ 160 void radeon_agp_disable(struct radeon_device *rdev) 161 { 162 rdev->flags &= ~RADEON_IS_AGP; 163 if (rdev->family >= CHIP_R600) { 164 DRM_INFO("Forcing AGP to PCIE mode\n"); 165 rdev->flags |= RADEON_IS_PCIE; 166 } else if (rdev->family >= CHIP_RV515 || 167 rdev->family == CHIP_RV380 || 168 rdev->family == CHIP_RV410 || 169 rdev->family == CHIP_R423) { 170 DRM_INFO("Forcing AGP to PCIE mode\n"); 171 rdev->flags |= RADEON_IS_PCIE; 172 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 173 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 174 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 175 } else { 176 DRM_INFO("Forcing AGP to PCI mode\n"); 177 rdev->flags |= RADEON_IS_PCI; 178 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 179 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 180 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 181 } 182 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 183 } 184 185 /* 186 * ASIC 187 */ 188 189 static const struct radeon_asic_ring r100_gfx_ring = { 190 .ib_execute = &r100_ring_ib_execute, 191 .emit_fence = &r100_fence_ring_emit, 192 .emit_semaphore = &r100_semaphore_ring_emit, 193 .cs_parse = &r100_cs_parse, 194 .ring_start = &r100_ring_start, 195 .ring_test = &r100_ring_test, 196 .ib_test = &r100_ib_test, 197 .is_lockup = &r100_gpu_is_lockup, 198 .get_rptr = &r100_gfx_get_rptr, 199 .get_wptr = &r100_gfx_get_wptr, 200 .set_wptr = &r100_gfx_set_wptr, 201 }; 202 203 static struct radeon_asic r100_asic = { 204 .init = &r100_init, 205 .fini = &r100_fini, 206 .suspend = &r100_suspend, 207 .resume = &r100_resume, 208 .vga_set_state = &r100_vga_set_state, 209 .asic_reset = &r100_asic_reset, 210 .mmio_hdp_flush = NULL, 211 .gui_idle = &r100_gui_idle, 212 .mc_wait_for_idle = &r100_mc_wait_for_idle, 213 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 214 .gart = { 215 .tlb_flush = &r100_pci_gart_tlb_flush, 216 .get_page_entry = &r100_pci_gart_get_page_entry, 217 .set_page = &r100_pci_gart_set_page, 218 }, 219 .ring = { 220 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 221 }, 222 .irq = { 223 .set = &r100_irq_set, 224 .process = &r100_irq_process, 225 }, 226 .display = { 227 .bandwidth_update = &r100_bandwidth_update, 228 .get_vblank_counter = &r100_get_vblank_counter, 229 .wait_for_vblank = &r100_wait_for_vblank, 230 .set_backlight_level = &radeon_legacy_set_backlight_level, 231 .get_backlight_level = &radeon_legacy_get_backlight_level, 232 }, 233 .copy = { 234 .blit = &r100_copy_blit, 235 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 236 .dma = NULL, 237 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 238 .copy = &r100_copy_blit, 239 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 240 }, 241 .surface = { 242 .set_reg = r100_set_surface_reg, 243 .clear_reg = r100_clear_surface_reg, 244 }, 245 .hpd = { 246 .init = &r100_hpd_init, 247 .fini = &r100_hpd_fini, 248 .sense = &r100_hpd_sense, 249 .set_polarity = &r100_hpd_set_polarity, 250 }, 251 .pm = { 252 .misc = &r100_pm_misc, 253 .prepare = &r100_pm_prepare, 254 .finish = &r100_pm_finish, 255 .init_profile = &r100_pm_init_profile, 256 .get_dynpm_state = &r100_pm_get_dynpm_state, 257 .get_engine_clock = &radeon_legacy_get_engine_clock, 258 .set_engine_clock = &radeon_legacy_set_engine_clock, 259 .get_memory_clock = &radeon_legacy_get_memory_clock, 260 .set_memory_clock = NULL, 261 .get_pcie_lanes = NULL, 262 .set_pcie_lanes = NULL, 263 .set_clock_gating = &radeon_legacy_set_clock_gating, 264 }, 265 .pflip = { 266 .page_flip = &r100_page_flip, 267 .page_flip_pending = &r100_page_flip_pending, 268 }, 269 }; 270 271 static struct radeon_asic r200_asic = { 272 .init = &r100_init, 273 .fini = &r100_fini, 274 .suspend = &r100_suspend, 275 .resume = &r100_resume, 276 .vga_set_state = &r100_vga_set_state, 277 .asic_reset = &r100_asic_reset, 278 .mmio_hdp_flush = NULL, 279 .gui_idle = &r100_gui_idle, 280 .mc_wait_for_idle = &r100_mc_wait_for_idle, 281 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 282 .gart = { 283 .tlb_flush = &r100_pci_gart_tlb_flush, 284 .get_page_entry = &r100_pci_gart_get_page_entry, 285 .set_page = &r100_pci_gart_set_page, 286 }, 287 .ring = { 288 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 289 }, 290 .irq = { 291 .set = &r100_irq_set, 292 .process = &r100_irq_process, 293 }, 294 .display = { 295 .bandwidth_update = &r100_bandwidth_update, 296 .get_vblank_counter = &r100_get_vblank_counter, 297 .wait_for_vblank = &r100_wait_for_vblank, 298 .set_backlight_level = &radeon_legacy_set_backlight_level, 299 .get_backlight_level = &radeon_legacy_get_backlight_level, 300 }, 301 .copy = { 302 .blit = &r100_copy_blit, 303 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 304 .dma = &r200_copy_dma, 305 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 306 .copy = &r100_copy_blit, 307 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 308 }, 309 .surface = { 310 .set_reg = r100_set_surface_reg, 311 .clear_reg = r100_clear_surface_reg, 312 }, 313 .hpd = { 314 .init = &r100_hpd_init, 315 .fini = &r100_hpd_fini, 316 .sense = &r100_hpd_sense, 317 .set_polarity = &r100_hpd_set_polarity, 318 }, 319 .pm = { 320 .misc = &r100_pm_misc, 321 .prepare = &r100_pm_prepare, 322 .finish = &r100_pm_finish, 323 .init_profile = &r100_pm_init_profile, 324 .get_dynpm_state = &r100_pm_get_dynpm_state, 325 .get_engine_clock = &radeon_legacy_get_engine_clock, 326 .set_engine_clock = &radeon_legacy_set_engine_clock, 327 .get_memory_clock = &radeon_legacy_get_memory_clock, 328 .set_memory_clock = NULL, 329 .get_pcie_lanes = NULL, 330 .set_pcie_lanes = NULL, 331 .set_clock_gating = &radeon_legacy_set_clock_gating, 332 }, 333 .pflip = { 334 .page_flip = &r100_page_flip, 335 .page_flip_pending = &r100_page_flip_pending, 336 }, 337 }; 338 339 static const struct radeon_asic_ring r300_gfx_ring = { 340 .ib_execute = &r100_ring_ib_execute, 341 .emit_fence = &r300_fence_ring_emit, 342 .emit_semaphore = &r100_semaphore_ring_emit, 343 .cs_parse = &r300_cs_parse, 344 .ring_start = &r300_ring_start, 345 .ring_test = &r100_ring_test, 346 .ib_test = &r100_ib_test, 347 .is_lockup = &r100_gpu_is_lockup, 348 .get_rptr = &r100_gfx_get_rptr, 349 .get_wptr = &r100_gfx_get_wptr, 350 .set_wptr = &r100_gfx_set_wptr, 351 }; 352 353 static const struct radeon_asic_ring rv515_gfx_ring = { 354 .ib_execute = &r100_ring_ib_execute, 355 .emit_fence = &r300_fence_ring_emit, 356 .emit_semaphore = &r100_semaphore_ring_emit, 357 .cs_parse = &r300_cs_parse, 358 .ring_start = &rv515_ring_start, 359 .ring_test = &r100_ring_test, 360 .ib_test = &r100_ib_test, 361 .is_lockup = &r100_gpu_is_lockup, 362 .get_rptr = &r100_gfx_get_rptr, 363 .get_wptr = &r100_gfx_get_wptr, 364 .set_wptr = &r100_gfx_set_wptr, 365 }; 366 367 static struct radeon_asic r300_asic = { 368 .init = &r300_init, 369 .fini = &r300_fini, 370 .suspend = &r300_suspend, 371 .resume = &r300_resume, 372 .vga_set_state = &r100_vga_set_state, 373 .asic_reset = &r300_asic_reset, 374 .mmio_hdp_flush = NULL, 375 .gui_idle = &r100_gui_idle, 376 .mc_wait_for_idle = &r300_mc_wait_for_idle, 377 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 378 .gart = { 379 .tlb_flush = &r100_pci_gart_tlb_flush, 380 .get_page_entry = &r100_pci_gart_get_page_entry, 381 .set_page = &r100_pci_gart_set_page, 382 }, 383 .ring = { 384 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 385 }, 386 .irq = { 387 .set = &r100_irq_set, 388 .process = &r100_irq_process, 389 }, 390 .display = { 391 .bandwidth_update = &r100_bandwidth_update, 392 .get_vblank_counter = &r100_get_vblank_counter, 393 .wait_for_vblank = &r100_wait_for_vblank, 394 .set_backlight_level = &radeon_legacy_set_backlight_level, 395 .get_backlight_level = &radeon_legacy_get_backlight_level, 396 }, 397 .copy = { 398 .blit = &r100_copy_blit, 399 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 400 .dma = &r200_copy_dma, 401 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 402 .copy = &r100_copy_blit, 403 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 404 }, 405 .surface = { 406 .set_reg = r100_set_surface_reg, 407 .clear_reg = r100_clear_surface_reg, 408 }, 409 .hpd = { 410 .init = &r100_hpd_init, 411 .fini = &r100_hpd_fini, 412 .sense = &r100_hpd_sense, 413 .set_polarity = &r100_hpd_set_polarity, 414 }, 415 .pm = { 416 .misc = &r100_pm_misc, 417 .prepare = &r100_pm_prepare, 418 .finish = &r100_pm_finish, 419 .init_profile = &r100_pm_init_profile, 420 .get_dynpm_state = &r100_pm_get_dynpm_state, 421 .get_engine_clock = &radeon_legacy_get_engine_clock, 422 .set_engine_clock = &radeon_legacy_set_engine_clock, 423 .get_memory_clock = &radeon_legacy_get_memory_clock, 424 .set_memory_clock = NULL, 425 .get_pcie_lanes = &rv370_get_pcie_lanes, 426 .set_pcie_lanes = &rv370_set_pcie_lanes, 427 .set_clock_gating = &radeon_legacy_set_clock_gating, 428 }, 429 .pflip = { 430 .page_flip = &r100_page_flip, 431 .page_flip_pending = &r100_page_flip_pending, 432 }, 433 }; 434 435 static struct radeon_asic r300_asic_pcie = { 436 .init = &r300_init, 437 .fini = &r300_fini, 438 .suspend = &r300_suspend, 439 .resume = &r300_resume, 440 .vga_set_state = &r100_vga_set_state, 441 .asic_reset = &r300_asic_reset, 442 .mmio_hdp_flush = NULL, 443 .gui_idle = &r100_gui_idle, 444 .mc_wait_for_idle = &r300_mc_wait_for_idle, 445 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 446 .gart = { 447 .tlb_flush = &rv370_pcie_gart_tlb_flush, 448 .get_page_entry = &rv370_pcie_gart_get_page_entry, 449 .set_page = &rv370_pcie_gart_set_page, 450 }, 451 .ring = { 452 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 453 }, 454 .irq = { 455 .set = &r100_irq_set, 456 .process = &r100_irq_process, 457 }, 458 .display = { 459 .bandwidth_update = &r100_bandwidth_update, 460 .get_vblank_counter = &r100_get_vblank_counter, 461 .wait_for_vblank = &r100_wait_for_vblank, 462 .set_backlight_level = &radeon_legacy_set_backlight_level, 463 .get_backlight_level = &radeon_legacy_get_backlight_level, 464 }, 465 .copy = { 466 .blit = &r100_copy_blit, 467 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 468 .dma = &r200_copy_dma, 469 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 470 .copy = &r100_copy_blit, 471 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 472 }, 473 .surface = { 474 .set_reg = r100_set_surface_reg, 475 .clear_reg = r100_clear_surface_reg, 476 }, 477 .hpd = { 478 .init = &r100_hpd_init, 479 .fini = &r100_hpd_fini, 480 .sense = &r100_hpd_sense, 481 .set_polarity = &r100_hpd_set_polarity, 482 }, 483 .pm = { 484 .misc = &r100_pm_misc, 485 .prepare = &r100_pm_prepare, 486 .finish = &r100_pm_finish, 487 .init_profile = &r100_pm_init_profile, 488 .get_dynpm_state = &r100_pm_get_dynpm_state, 489 .get_engine_clock = &radeon_legacy_get_engine_clock, 490 .set_engine_clock = &radeon_legacy_set_engine_clock, 491 .get_memory_clock = &radeon_legacy_get_memory_clock, 492 .set_memory_clock = NULL, 493 .get_pcie_lanes = &rv370_get_pcie_lanes, 494 .set_pcie_lanes = &rv370_set_pcie_lanes, 495 .set_clock_gating = &radeon_legacy_set_clock_gating, 496 }, 497 .pflip = { 498 .page_flip = &r100_page_flip, 499 .page_flip_pending = &r100_page_flip_pending, 500 }, 501 }; 502 503 static struct radeon_asic r420_asic = { 504 .init = &r420_init, 505 .fini = &r420_fini, 506 .suspend = &r420_suspend, 507 .resume = &r420_resume, 508 .vga_set_state = &r100_vga_set_state, 509 .asic_reset = &r300_asic_reset, 510 .mmio_hdp_flush = NULL, 511 .gui_idle = &r100_gui_idle, 512 .mc_wait_for_idle = &r300_mc_wait_for_idle, 513 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 514 .gart = { 515 .tlb_flush = &rv370_pcie_gart_tlb_flush, 516 .get_page_entry = &rv370_pcie_gart_get_page_entry, 517 .set_page = &rv370_pcie_gart_set_page, 518 }, 519 .ring = { 520 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 521 }, 522 .irq = { 523 .set = &r100_irq_set, 524 .process = &r100_irq_process, 525 }, 526 .display = { 527 .bandwidth_update = &r100_bandwidth_update, 528 .get_vblank_counter = &r100_get_vblank_counter, 529 .wait_for_vblank = &r100_wait_for_vblank, 530 .set_backlight_level = &atombios_set_backlight_level, 531 .get_backlight_level = &atombios_get_backlight_level, 532 }, 533 .copy = { 534 .blit = &r100_copy_blit, 535 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 536 .dma = &r200_copy_dma, 537 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 538 .copy = &r100_copy_blit, 539 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 540 }, 541 .surface = { 542 .set_reg = r100_set_surface_reg, 543 .clear_reg = r100_clear_surface_reg, 544 }, 545 .hpd = { 546 .init = &r100_hpd_init, 547 .fini = &r100_hpd_fini, 548 .sense = &r100_hpd_sense, 549 .set_polarity = &r100_hpd_set_polarity, 550 }, 551 .pm = { 552 .misc = &r100_pm_misc, 553 .prepare = &r100_pm_prepare, 554 .finish = &r100_pm_finish, 555 .init_profile = &r420_pm_init_profile, 556 .get_dynpm_state = &r100_pm_get_dynpm_state, 557 .get_engine_clock = &radeon_atom_get_engine_clock, 558 .set_engine_clock = &radeon_atom_set_engine_clock, 559 .get_memory_clock = &radeon_atom_get_memory_clock, 560 .set_memory_clock = &radeon_atom_set_memory_clock, 561 .get_pcie_lanes = &rv370_get_pcie_lanes, 562 .set_pcie_lanes = &rv370_set_pcie_lanes, 563 .set_clock_gating = &radeon_atom_set_clock_gating, 564 }, 565 .pflip = { 566 .page_flip = &r100_page_flip, 567 .page_flip_pending = &r100_page_flip_pending, 568 }, 569 }; 570 571 static struct radeon_asic rs400_asic = { 572 .init = &rs400_init, 573 .fini = &rs400_fini, 574 .suspend = &rs400_suspend, 575 .resume = &rs400_resume, 576 .vga_set_state = &r100_vga_set_state, 577 .asic_reset = &r300_asic_reset, 578 .mmio_hdp_flush = NULL, 579 .gui_idle = &r100_gui_idle, 580 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 581 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 582 .gart = { 583 .tlb_flush = &rs400_gart_tlb_flush, 584 .get_page_entry = &rs400_gart_get_page_entry, 585 .set_page = &rs400_gart_set_page, 586 }, 587 .ring = { 588 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 589 }, 590 .irq = { 591 .set = &r100_irq_set, 592 .process = &r100_irq_process, 593 }, 594 .display = { 595 .bandwidth_update = &r100_bandwidth_update, 596 .get_vblank_counter = &r100_get_vblank_counter, 597 .wait_for_vblank = &r100_wait_for_vblank, 598 .set_backlight_level = &radeon_legacy_set_backlight_level, 599 .get_backlight_level = &radeon_legacy_get_backlight_level, 600 }, 601 .copy = { 602 .blit = &r100_copy_blit, 603 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 604 .dma = &r200_copy_dma, 605 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 606 .copy = &r100_copy_blit, 607 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 608 }, 609 .surface = { 610 .set_reg = r100_set_surface_reg, 611 .clear_reg = r100_clear_surface_reg, 612 }, 613 .hpd = { 614 .init = &r100_hpd_init, 615 .fini = &r100_hpd_fini, 616 .sense = &r100_hpd_sense, 617 .set_polarity = &r100_hpd_set_polarity, 618 }, 619 .pm = { 620 .misc = &r100_pm_misc, 621 .prepare = &r100_pm_prepare, 622 .finish = &r100_pm_finish, 623 .init_profile = &r100_pm_init_profile, 624 .get_dynpm_state = &r100_pm_get_dynpm_state, 625 .get_engine_clock = &radeon_legacy_get_engine_clock, 626 .set_engine_clock = &radeon_legacy_set_engine_clock, 627 .get_memory_clock = &radeon_legacy_get_memory_clock, 628 .set_memory_clock = NULL, 629 .get_pcie_lanes = NULL, 630 .set_pcie_lanes = NULL, 631 .set_clock_gating = &radeon_legacy_set_clock_gating, 632 }, 633 .pflip = { 634 .page_flip = &r100_page_flip, 635 .page_flip_pending = &r100_page_flip_pending, 636 }, 637 }; 638 639 static struct radeon_asic rs600_asic = { 640 .init = &rs600_init, 641 .fini = &rs600_fini, 642 .suspend = &rs600_suspend, 643 .resume = &rs600_resume, 644 .vga_set_state = &r100_vga_set_state, 645 .asic_reset = &rs600_asic_reset, 646 .mmio_hdp_flush = NULL, 647 .gui_idle = &r100_gui_idle, 648 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 649 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 650 .gart = { 651 .tlb_flush = &rs600_gart_tlb_flush, 652 .get_page_entry = &rs600_gart_get_page_entry, 653 .set_page = &rs600_gart_set_page, 654 }, 655 .ring = { 656 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 657 }, 658 .irq = { 659 .set = &rs600_irq_set, 660 .process = &rs600_irq_process, 661 }, 662 .display = { 663 .bandwidth_update = &rs600_bandwidth_update, 664 .get_vblank_counter = &rs600_get_vblank_counter, 665 .wait_for_vblank = &avivo_wait_for_vblank, 666 .set_backlight_level = &atombios_set_backlight_level, 667 .get_backlight_level = &atombios_get_backlight_level, 668 }, 669 .copy = { 670 .blit = &r100_copy_blit, 671 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 672 .dma = &r200_copy_dma, 673 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 674 .copy = &r100_copy_blit, 675 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 676 }, 677 .surface = { 678 .set_reg = r100_set_surface_reg, 679 .clear_reg = r100_clear_surface_reg, 680 }, 681 .hpd = { 682 .init = &rs600_hpd_init, 683 .fini = &rs600_hpd_fini, 684 .sense = &rs600_hpd_sense, 685 .set_polarity = &rs600_hpd_set_polarity, 686 }, 687 .pm = { 688 .misc = &rs600_pm_misc, 689 .prepare = &rs600_pm_prepare, 690 .finish = &rs600_pm_finish, 691 .init_profile = &r420_pm_init_profile, 692 .get_dynpm_state = &r100_pm_get_dynpm_state, 693 .get_engine_clock = &radeon_atom_get_engine_clock, 694 .set_engine_clock = &radeon_atom_set_engine_clock, 695 .get_memory_clock = &radeon_atom_get_memory_clock, 696 .set_memory_clock = &radeon_atom_set_memory_clock, 697 .get_pcie_lanes = NULL, 698 .set_pcie_lanes = NULL, 699 .set_clock_gating = &radeon_atom_set_clock_gating, 700 }, 701 .pflip = { 702 .page_flip = &rs600_page_flip, 703 .page_flip_pending = &rs600_page_flip_pending, 704 }, 705 }; 706 707 static struct radeon_asic rs690_asic = { 708 .init = &rs690_init, 709 .fini = &rs690_fini, 710 .suspend = &rs690_suspend, 711 .resume = &rs690_resume, 712 .vga_set_state = &r100_vga_set_state, 713 .asic_reset = &rs600_asic_reset, 714 .mmio_hdp_flush = NULL, 715 .gui_idle = &r100_gui_idle, 716 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 717 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 718 .gart = { 719 .tlb_flush = &rs400_gart_tlb_flush, 720 .get_page_entry = &rs400_gart_get_page_entry, 721 .set_page = &rs400_gart_set_page, 722 }, 723 .ring = { 724 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 725 }, 726 .irq = { 727 .set = &rs600_irq_set, 728 .process = &rs600_irq_process, 729 }, 730 .display = { 731 .get_vblank_counter = &rs600_get_vblank_counter, 732 .bandwidth_update = &rs690_bandwidth_update, 733 .wait_for_vblank = &avivo_wait_for_vblank, 734 .set_backlight_level = &atombios_set_backlight_level, 735 .get_backlight_level = &atombios_get_backlight_level, 736 }, 737 .copy = { 738 .blit = &r100_copy_blit, 739 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 740 .dma = &r200_copy_dma, 741 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 742 .copy = &r200_copy_dma, 743 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 744 }, 745 .surface = { 746 .set_reg = r100_set_surface_reg, 747 .clear_reg = r100_clear_surface_reg, 748 }, 749 .hpd = { 750 .init = &rs600_hpd_init, 751 .fini = &rs600_hpd_fini, 752 .sense = &rs600_hpd_sense, 753 .set_polarity = &rs600_hpd_set_polarity, 754 }, 755 .pm = { 756 .misc = &rs600_pm_misc, 757 .prepare = &rs600_pm_prepare, 758 .finish = &rs600_pm_finish, 759 .init_profile = &r420_pm_init_profile, 760 .get_dynpm_state = &r100_pm_get_dynpm_state, 761 .get_engine_clock = &radeon_atom_get_engine_clock, 762 .set_engine_clock = &radeon_atom_set_engine_clock, 763 .get_memory_clock = &radeon_atom_get_memory_clock, 764 .set_memory_clock = &radeon_atom_set_memory_clock, 765 .get_pcie_lanes = NULL, 766 .set_pcie_lanes = NULL, 767 .set_clock_gating = &radeon_atom_set_clock_gating, 768 }, 769 .pflip = { 770 .page_flip = &rs600_page_flip, 771 .page_flip_pending = &rs600_page_flip_pending, 772 }, 773 }; 774 775 static struct radeon_asic rv515_asic = { 776 .init = &rv515_init, 777 .fini = &rv515_fini, 778 .suspend = &rv515_suspend, 779 .resume = &rv515_resume, 780 .vga_set_state = &r100_vga_set_state, 781 .asic_reset = &rs600_asic_reset, 782 .mmio_hdp_flush = NULL, 783 .gui_idle = &r100_gui_idle, 784 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 785 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 786 .gart = { 787 .tlb_flush = &rv370_pcie_gart_tlb_flush, 788 .get_page_entry = &rv370_pcie_gart_get_page_entry, 789 .set_page = &rv370_pcie_gart_set_page, 790 }, 791 .ring = { 792 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 793 }, 794 .irq = { 795 .set = &rs600_irq_set, 796 .process = &rs600_irq_process, 797 }, 798 .display = { 799 .get_vblank_counter = &rs600_get_vblank_counter, 800 .bandwidth_update = &rv515_bandwidth_update, 801 .wait_for_vblank = &avivo_wait_for_vblank, 802 .set_backlight_level = &atombios_set_backlight_level, 803 .get_backlight_level = &atombios_get_backlight_level, 804 }, 805 .copy = { 806 .blit = &r100_copy_blit, 807 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 808 .dma = &r200_copy_dma, 809 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 810 .copy = &r100_copy_blit, 811 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 812 }, 813 .surface = { 814 .set_reg = r100_set_surface_reg, 815 .clear_reg = r100_clear_surface_reg, 816 }, 817 .hpd = { 818 .init = &rs600_hpd_init, 819 .fini = &rs600_hpd_fini, 820 .sense = &rs600_hpd_sense, 821 .set_polarity = &rs600_hpd_set_polarity, 822 }, 823 .pm = { 824 .misc = &rs600_pm_misc, 825 .prepare = &rs600_pm_prepare, 826 .finish = &rs600_pm_finish, 827 .init_profile = &r420_pm_init_profile, 828 .get_dynpm_state = &r100_pm_get_dynpm_state, 829 .get_engine_clock = &radeon_atom_get_engine_clock, 830 .set_engine_clock = &radeon_atom_set_engine_clock, 831 .get_memory_clock = &radeon_atom_get_memory_clock, 832 .set_memory_clock = &radeon_atom_set_memory_clock, 833 .get_pcie_lanes = &rv370_get_pcie_lanes, 834 .set_pcie_lanes = &rv370_set_pcie_lanes, 835 .set_clock_gating = &radeon_atom_set_clock_gating, 836 }, 837 .pflip = { 838 .page_flip = &rs600_page_flip, 839 .page_flip_pending = &rs600_page_flip_pending, 840 }, 841 }; 842 843 static struct radeon_asic r520_asic = { 844 .init = &r520_init, 845 .fini = &rv515_fini, 846 .suspend = &rv515_suspend, 847 .resume = &r520_resume, 848 .vga_set_state = &r100_vga_set_state, 849 .asic_reset = &rs600_asic_reset, 850 .mmio_hdp_flush = NULL, 851 .gui_idle = &r100_gui_idle, 852 .mc_wait_for_idle = &r520_mc_wait_for_idle, 853 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 854 .gart = { 855 .tlb_flush = &rv370_pcie_gart_tlb_flush, 856 .get_page_entry = &rv370_pcie_gart_get_page_entry, 857 .set_page = &rv370_pcie_gart_set_page, 858 }, 859 .ring = { 860 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 861 }, 862 .irq = { 863 .set = &rs600_irq_set, 864 .process = &rs600_irq_process, 865 }, 866 .display = { 867 .bandwidth_update = &rv515_bandwidth_update, 868 .get_vblank_counter = &rs600_get_vblank_counter, 869 .wait_for_vblank = &avivo_wait_for_vblank, 870 .set_backlight_level = &atombios_set_backlight_level, 871 .get_backlight_level = &atombios_get_backlight_level, 872 }, 873 .copy = { 874 .blit = &r100_copy_blit, 875 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 876 .dma = &r200_copy_dma, 877 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 878 .copy = &r100_copy_blit, 879 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 880 }, 881 .surface = { 882 .set_reg = r100_set_surface_reg, 883 .clear_reg = r100_clear_surface_reg, 884 }, 885 .hpd = { 886 .init = &rs600_hpd_init, 887 .fini = &rs600_hpd_fini, 888 .sense = &rs600_hpd_sense, 889 .set_polarity = &rs600_hpd_set_polarity, 890 }, 891 .pm = { 892 .misc = &rs600_pm_misc, 893 .prepare = &rs600_pm_prepare, 894 .finish = &rs600_pm_finish, 895 .init_profile = &r420_pm_init_profile, 896 .get_dynpm_state = &r100_pm_get_dynpm_state, 897 .get_engine_clock = &radeon_atom_get_engine_clock, 898 .set_engine_clock = &radeon_atom_set_engine_clock, 899 .get_memory_clock = &radeon_atom_get_memory_clock, 900 .set_memory_clock = &radeon_atom_set_memory_clock, 901 .get_pcie_lanes = &rv370_get_pcie_lanes, 902 .set_pcie_lanes = &rv370_set_pcie_lanes, 903 .set_clock_gating = &radeon_atom_set_clock_gating, 904 }, 905 .pflip = { 906 .page_flip = &rs600_page_flip, 907 .page_flip_pending = &rs600_page_flip_pending, 908 }, 909 }; 910 911 static const struct radeon_asic_ring r600_gfx_ring = { 912 .ib_execute = &r600_ring_ib_execute, 913 .emit_fence = &r600_fence_ring_emit, 914 .emit_semaphore = &r600_semaphore_ring_emit, 915 .cs_parse = &r600_cs_parse, 916 .ring_test = &r600_ring_test, 917 .ib_test = &r600_ib_test, 918 .is_lockup = &r600_gfx_is_lockup, 919 .get_rptr = &r600_gfx_get_rptr, 920 .get_wptr = &r600_gfx_get_wptr, 921 .set_wptr = &r600_gfx_set_wptr, 922 }; 923 924 static const struct radeon_asic_ring r600_dma_ring = { 925 .ib_execute = &r600_dma_ring_ib_execute, 926 .emit_fence = &r600_dma_fence_ring_emit, 927 .emit_semaphore = &r600_dma_semaphore_ring_emit, 928 .cs_parse = &r600_dma_cs_parse, 929 .ring_test = &r600_dma_ring_test, 930 .ib_test = &r600_dma_ib_test, 931 .is_lockup = &r600_dma_is_lockup, 932 .get_rptr = &r600_dma_get_rptr, 933 .get_wptr = &r600_dma_get_wptr, 934 .set_wptr = &r600_dma_set_wptr, 935 }; 936 937 static struct radeon_asic r600_asic = { 938 .init = &r600_init, 939 .fini = &r600_fini, 940 .suspend = &r600_suspend, 941 .resume = &r600_resume, 942 .vga_set_state = &r600_vga_set_state, 943 .asic_reset = &r600_asic_reset, 944 .mmio_hdp_flush = r600_mmio_hdp_flush, 945 .gui_idle = &r600_gui_idle, 946 .mc_wait_for_idle = &r600_mc_wait_for_idle, 947 .get_xclk = &r600_get_xclk, 948 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 949 .get_allowed_info_register = r600_get_allowed_info_register, 950 .gart = { 951 .tlb_flush = &r600_pcie_gart_tlb_flush, 952 .get_page_entry = &rs600_gart_get_page_entry, 953 .set_page = &rs600_gart_set_page, 954 }, 955 .ring = { 956 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 957 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 958 }, 959 .irq = { 960 .set = &r600_irq_set, 961 .process = &r600_irq_process, 962 }, 963 .display = { 964 .bandwidth_update = &rv515_bandwidth_update, 965 .get_vblank_counter = &rs600_get_vblank_counter, 966 .wait_for_vblank = &avivo_wait_for_vblank, 967 .set_backlight_level = &atombios_set_backlight_level, 968 .get_backlight_level = &atombios_get_backlight_level, 969 }, 970 .copy = { 971 .blit = &r600_copy_cpdma, 972 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 973 .dma = &r600_copy_dma, 974 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 975 .copy = &r600_copy_cpdma, 976 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 977 }, 978 .surface = { 979 .set_reg = r600_set_surface_reg, 980 .clear_reg = r600_clear_surface_reg, 981 }, 982 .hpd = { 983 .init = &r600_hpd_init, 984 .fini = &r600_hpd_fini, 985 .sense = &r600_hpd_sense, 986 .set_polarity = &r600_hpd_set_polarity, 987 }, 988 .pm = { 989 .misc = &r600_pm_misc, 990 .prepare = &rs600_pm_prepare, 991 .finish = &rs600_pm_finish, 992 .init_profile = &r600_pm_init_profile, 993 .get_dynpm_state = &r600_pm_get_dynpm_state, 994 .get_engine_clock = &radeon_atom_get_engine_clock, 995 .set_engine_clock = &radeon_atom_set_engine_clock, 996 .get_memory_clock = &radeon_atom_get_memory_clock, 997 .set_memory_clock = &radeon_atom_set_memory_clock, 998 .get_pcie_lanes = &r600_get_pcie_lanes, 999 .set_pcie_lanes = &r600_set_pcie_lanes, 1000 .set_clock_gating = NULL, 1001 .get_temperature = &rv6xx_get_temp, 1002 }, 1003 .pflip = { 1004 .page_flip = &rs600_page_flip, 1005 .page_flip_pending = &rs600_page_flip_pending, 1006 }, 1007 }; 1008 1009 static const struct radeon_asic_ring rv6xx_uvd_ring = { 1010 .ib_execute = &uvd_v1_0_ib_execute, 1011 .emit_fence = &uvd_v1_0_fence_emit, 1012 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1013 .cs_parse = &radeon_uvd_cs_parse, 1014 .ring_test = &uvd_v1_0_ring_test, 1015 .ib_test = &uvd_v1_0_ib_test, 1016 .is_lockup = &radeon_ring_test_lockup, 1017 .get_rptr = &uvd_v1_0_get_rptr, 1018 .get_wptr = &uvd_v1_0_get_wptr, 1019 .set_wptr = &uvd_v1_0_set_wptr, 1020 }; 1021 1022 static struct radeon_asic rv6xx_asic = { 1023 .init = &r600_init, 1024 .fini = &r600_fini, 1025 .suspend = &r600_suspend, 1026 .resume = &r600_resume, 1027 .vga_set_state = &r600_vga_set_state, 1028 .asic_reset = &r600_asic_reset, 1029 .mmio_hdp_flush = r600_mmio_hdp_flush, 1030 .gui_idle = &r600_gui_idle, 1031 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1032 .get_xclk = &r600_get_xclk, 1033 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1034 .get_allowed_info_register = r600_get_allowed_info_register, 1035 .gart = { 1036 .tlb_flush = &r600_pcie_gart_tlb_flush, 1037 .get_page_entry = &rs600_gart_get_page_entry, 1038 .set_page = &rs600_gart_set_page, 1039 }, 1040 .ring = { 1041 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1042 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1043 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1044 }, 1045 .irq = { 1046 .set = &r600_irq_set, 1047 .process = &r600_irq_process, 1048 }, 1049 .display = { 1050 .bandwidth_update = &rv515_bandwidth_update, 1051 .get_vblank_counter = &rs600_get_vblank_counter, 1052 .wait_for_vblank = &avivo_wait_for_vblank, 1053 .set_backlight_level = &atombios_set_backlight_level, 1054 .get_backlight_level = &atombios_get_backlight_level, 1055 }, 1056 .copy = { 1057 .blit = &r600_copy_cpdma, 1058 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1059 .dma = &r600_copy_dma, 1060 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1061 .copy = &r600_copy_cpdma, 1062 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1063 }, 1064 .surface = { 1065 .set_reg = r600_set_surface_reg, 1066 .clear_reg = r600_clear_surface_reg, 1067 }, 1068 .hpd = { 1069 .init = &r600_hpd_init, 1070 .fini = &r600_hpd_fini, 1071 .sense = &r600_hpd_sense, 1072 .set_polarity = &r600_hpd_set_polarity, 1073 }, 1074 .pm = { 1075 .misc = &r600_pm_misc, 1076 .prepare = &rs600_pm_prepare, 1077 .finish = &rs600_pm_finish, 1078 .init_profile = &r600_pm_init_profile, 1079 .get_dynpm_state = &r600_pm_get_dynpm_state, 1080 .get_engine_clock = &radeon_atom_get_engine_clock, 1081 .set_engine_clock = &radeon_atom_set_engine_clock, 1082 .get_memory_clock = &radeon_atom_get_memory_clock, 1083 .set_memory_clock = &radeon_atom_set_memory_clock, 1084 .get_pcie_lanes = &r600_get_pcie_lanes, 1085 .set_pcie_lanes = &r600_set_pcie_lanes, 1086 .set_clock_gating = NULL, 1087 .get_temperature = &rv6xx_get_temp, 1088 .set_uvd_clocks = &r600_set_uvd_clocks, 1089 }, 1090 .dpm = { 1091 .init = &rv6xx_dpm_init, 1092 .setup_asic = &rv6xx_setup_asic, 1093 .enable = &rv6xx_dpm_enable, 1094 .late_enable = &r600_dpm_late_enable, 1095 .disable = &rv6xx_dpm_disable, 1096 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1097 .set_power_state = &rv6xx_dpm_set_power_state, 1098 .post_set_power_state = &r600_dpm_post_set_power_state, 1099 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1100 .fini = &rv6xx_dpm_fini, 1101 .get_sclk = &rv6xx_dpm_get_sclk, 1102 .get_mclk = &rv6xx_dpm_get_mclk, 1103 .print_power_state = &rv6xx_dpm_print_power_state, 1104 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1105 .force_performance_level = &rv6xx_dpm_force_performance_level, 1106 .get_current_sclk = &rv6xx_dpm_get_current_sclk, 1107 .get_current_mclk = &rv6xx_dpm_get_current_mclk, 1108 }, 1109 .pflip = { 1110 .page_flip = &rs600_page_flip, 1111 .page_flip_pending = &rs600_page_flip_pending, 1112 }, 1113 }; 1114 1115 static struct radeon_asic rs780_asic = { 1116 .init = &r600_init, 1117 .fini = &r600_fini, 1118 .suspend = &r600_suspend, 1119 .resume = &r600_resume, 1120 .vga_set_state = &r600_vga_set_state, 1121 .asic_reset = &r600_asic_reset, 1122 .mmio_hdp_flush = r600_mmio_hdp_flush, 1123 .gui_idle = &r600_gui_idle, 1124 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1125 .get_xclk = &r600_get_xclk, 1126 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1127 .get_allowed_info_register = r600_get_allowed_info_register, 1128 .gart = { 1129 .tlb_flush = &r600_pcie_gart_tlb_flush, 1130 .get_page_entry = &rs600_gart_get_page_entry, 1131 .set_page = &rs600_gart_set_page, 1132 }, 1133 .ring = { 1134 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1135 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1136 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1137 }, 1138 .irq = { 1139 .set = &r600_irq_set, 1140 .process = &r600_irq_process, 1141 }, 1142 .display = { 1143 .bandwidth_update = &rs690_bandwidth_update, 1144 .get_vblank_counter = &rs600_get_vblank_counter, 1145 .wait_for_vblank = &avivo_wait_for_vblank, 1146 .set_backlight_level = &atombios_set_backlight_level, 1147 .get_backlight_level = &atombios_get_backlight_level, 1148 }, 1149 .copy = { 1150 .blit = &r600_copy_cpdma, 1151 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1152 .dma = &r600_copy_dma, 1153 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1154 .copy = &r600_copy_cpdma, 1155 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1156 }, 1157 .surface = { 1158 .set_reg = r600_set_surface_reg, 1159 .clear_reg = r600_clear_surface_reg, 1160 }, 1161 .hpd = { 1162 .init = &r600_hpd_init, 1163 .fini = &r600_hpd_fini, 1164 .sense = &r600_hpd_sense, 1165 .set_polarity = &r600_hpd_set_polarity, 1166 }, 1167 .pm = { 1168 .misc = &r600_pm_misc, 1169 .prepare = &rs600_pm_prepare, 1170 .finish = &rs600_pm_finish, 1171 .init_profile = &rs780_pm_init_profile, 1172 .get_dynpm_state = &r600_pm_get_dynpm_state, 1173 .get_engine_clock = &radeon_atom_get_engine_clock, 1174 .set_engine_clock = &radeon_atom_set_engine_clock, 1175 .get_memory_clock = NULL, 1176 .set_memory_clock = NULL, 1177 .get_pcie_lanes = NULL, 1178 .set_pcie_lanes = NULL, 1179 .set_clock_gating = NULL, 1180 .get_temperature = &rv6xx_get_temp, 1181 .set_uvd_clocks = &r600_set_uvd_clocks, 1182 }, 1183 .dpm = { 1184 .init = &rs780_dpm_init, 1185 .setup_asic = &rs780_dpm_setup_asic, 1186 .enable = &rs780_dpm_enable, 1187 .late_enable = &r600_dpm_late_enable, 1188 .disable = &rs780_dpm_disable, 1189 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1190 .set_power_state = &rs780_dpm_set_power_state, 1191 .post_set_power_state = &r600_dpm_post_set_power_state, 1192 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1193 .fini = &rs780_dpm_fini, 1194 .get_sclk = &rs780_dpm_get_sclk, 1195 .get_mclk = &rs780_dpm_get_mclk, 1196 .print_power_state = &rs780_dpm_print_power_state, 1197 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1198 .force_performance_level = &rs780_dpm_force_performance_level, 1199 .get_current_sclk = &rs780_dpm_get_current_sclk, 1200 .get_current_mclk = &rs780_dpm_get_current_mclk, 1201 }, 1202 .pflip = { 1203 .page_flip = &rs600_page_flip, 1204 .page_flip_pending = &rs600_page_flip_pending, 1205 }, 1206 }; 1207 1208 static const struct radeon_asic_ring rv770_uvd_ring = { 1209 .ib_execute = &uvd_v1_0_ib_execute, 1210 .emit_fence = &uvd_v2_2_fence_emit, 1211 .emit_semaphore = &uvd_v2_2_semaphore_emit, 1212 .cs_parse = &radeon_uvd_cs_parse, 1213 .ring_test = &uvd_v1_0_ring_test, 1214 .ib_test = &uvd_v1_0_ib_test, 1215 .is_lockup = &radeon_ring_test_lockup, 1216 .get_rptr = &uvd_v1_0_get_rptr, 1217 .get_wptr = &uvd_v1_0_get_wptr, 1218 .set_wptr = &uvd_v1_0_set_wptr, 1219 }; 1220 1221 static struct radeon_asic rv770_asic = { 1222 .init = &rv770_init, 1223 .fini = &rv770_fini, 1224 .suspend = &rv770_suspend, 1225 .resume = &rv770_resume, 1226 .asic_reset = &r600_asic_reset, 1227 .vga_set_state = &r600_vga_set_state, 1228 .mmio_hdp_flush = r600_mmio_hdp_flush, 1229 .gui_idle = &r600_gui_idle, 1230 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1231 .get_xclk = &rv770_get_xclk, 1232 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1233 .get_allowed_info_register = r600_get_allowed_info_register, 1234 .gart = { 1235 .tlb_flush = &r600_pcie_gart_tlb_flush, 1236 .get_page_entry = &rs600_gart_get_page_entry, 1237 .set_page = &rs600_gart_set_page, 1238 }, 1239 .ring = { 1240 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1241 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1242 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1243 }, 1244 .irq = { 1245 .set = &r600_irq_set, 1246 .process = &r600_irq_process, 1247 }, 1248 .display = { 1249 .bandwidth_update = &rv515_bandwidth_update, 1250 .get_vblank_counter = &rs600_get_vblank_counter, 1251 .wait_for_vblank = &avivo_wait_for_vblank, 1252 .set_backlight_level = &atombios_set_backlight_level, 1253 .get_backlight_level = &atombios_get_backlight_level, 1254 }, 1255 .copy = { 1256 .blit = &r600_copy_cpdma, 1257 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1258 .dma = &rv770_copy_dma, 1259 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1260 .copy = &rv770_copy_dma, 1261 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1262 }, 1263 .surface = { 1264 .set_reg = r600_set_surface_reg, 1265 .clear_reg = r600_clear_surface_reg, 1266 }, 1267 .hpd = { 1268 .init = &r600_hpd_init, 1269 .fini = &r600_hpd_fini, 1270 .sense = &r600_hpd_sense, 1271 .set_polarity = &r600_hpd_set_polarity, 1272 }, 1273 .pm = { 1274 .misc = &rv770_pm_misc, 1275 .prepare = &rs600_pm_prepare, 1276 .finish = &rs600_pm_finish, 1277 .init_profile = &r600_pm_init_profile, 1278 .get_dynpm_state = &r600_pm_get_dynpm_state, 1279 .get_engine_clock = &radeon_atom_get_engine_clock, 1280 .set_engine_clock = &radeon_atom_set_engine_clock, 1281 .get_memory_clock = &radeon_atom_get_memory_clock, 1282 .set_memory_clock = &radeon_atom_set_memory_clock, 1283 .get_pcie_lanes = &r600_get_pcie_lanes, 1284 .set_pcie_lanes = &r600_set_pcie_lanes, 1285 .set_clock_gating = &radeon_atom_set_clock_gating, 1286 .set_uvd_clocks = &rv770_set_uvd_clocks, 1287 .get_temperature = &rv770_get_temp, 1288 }, 1289 .dpm = { 1290 .init = &rv770_dpm_init, 1291 .setup_asic = &rv770_dpm_setup_asic, 1292 .enable = &rv770_dpm_enable, 1293 .late_enable = &rv770_dpm_late_enable, 1294 .disable = &rv770_dpm_disable, 1295 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1296 .set_power_state = &rv770_dpm_set_power_state, 1297 .post_set_power_state = &r600_dpm_post_set_power_state, 1298 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1299 .fini = &rv770_dpm_fini, 1300 .get_sclk = &rv770_dpm_get_sclk, 1301 .get_mclk = &rv770_dpm_get_mclk, 1302 .print_power_state = &rv770_dpm_print_power_state, 1303 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1304 .force_performance_level = &rv770_dpm_force_performance_level, 1305 .vblank_too_short = &rv770_dpm_vblank_too_short, 1306 .get_current_sclk = &rv770_dpm_get_current_sclk, 1307 .get_current_mclk = &rv770_dpm_get_current_mclk, 1308 }, 1309 .pflip = { 1310 .page_flip = &rv770_page_flip, 1311 .page_flip_pending = &rv770_page_flip_pending, 1312 }, 1313 }; 1314 1315 static const struct radeon_asic_ring evergreen_gfx_ring = { 1316 .ib_execute = &evergreen_ring_ib_execute, 1317 .emit_fence = &r600_fence_ring_emit, 1318 .emit_semaphore = &r600_semaphore_ring_emit, 1319 .cs_parse = &evergreen_cs_parse, 1320 .ring_test = &r600_ring_test, 1321 .ib_test = &r600_ib_test, 1322 .is_lockup = &evergreen_gfx_is_lockup, 1323 .get_rptr = &r600_gfx_get_rptr, 1324 .get_wptr = &r600_gfx_get_wptr, 1325 .set_wptr = &r600_gfx_set_wptr, 1326 }; 1327 1328 static const struct radeon_asic_ring evergreen_dma_ring = { 1329 .ib_execute = &evergreen_dma_ring_ib_execute, 1330 .emit_fence = &evergreen_dma_fence_ring_emit, 1331 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1332 .cs_parse = &evergreen_dma_cs_parse, 1333 .ring_test = &r600_dma_ring_test, 1334 .ib_test = &r600_dma_ib_test, 1335 .is_lockup = &evergreen_dma_is_lockup, 1336 .get_rptr = &r600_dma_get_rptr, 1337 .get_wptr = &r600_dma_get_wptr, 1338 .set_wptr = &r600_dma_set_wptr, 1339 }; 1340 1341 static struct radeon_asic evergreen_asic = { 1342 .init = &evergreen_init, 1343 .fini = &evergreen_fini, 1344 .suspend = &evergreen_suspend, 1345 .resume = &evergreen_resume, 1346 .asic_reset = &evergreen_asic_reset, 1347 .vga_set_state = &r600_vga_set_state, 1348 .mmio_hdp_flush = r600_mmio_hdp_flush, 1349 .gui_idle = &r600_gui_idle, 1350 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1351 .get_xclk = &rv770_get_xclk, 1352 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1353 .get_allowed_info_register = evergreen_get_allowed_info_register, 1354 .gart = { 1355 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1356 .get_page_entry = &rs600_gart_get_page_entry, 1357 .set_page = &rs600_gart_set_page, 1358 }, 1359 .ring = { 1360 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1361 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1362 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1363 }, 1364 .irq = { 1365 .set = &evergreen_irq_set, 1366 .process = &evergreen_irq_process, 1367 }, 1368 .display = { 1369 .bandwidth_update = &evergreen_bandwidth_update, 1370 .get_vblank_counter = &evergreen_get_vblank_counter, 1371 .wait_for_vblank = &dce4_wait_for_vblank, 1372 .set_backlight_level = &atombios_set_backlight_level, 1373 .get_backlight_level = &atombios_get_backlight_level, 1374 }, 1375 .copy = { 1376 .blit = &r600_copy_cpdma, 1377 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1378 .dma = &evergreen_copy_dma, 1379 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1380 .copy = &evergreen_copy_dma, 1381 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1382 }, 1383 .surface = { 1384 .set_reg = r600_set_surface_reg, 1385 .clear_reg = r600_clear_surface_reg, 1386 }, 1387 .hpd = { 1388 .init = &evergreen_hpd_init, 1389 .fini = &evergreen_hpd_fini, 1390 .sense = &evergreen_hpd_sense, 1391 .set_polarity = &evergreen_hpd_set_polarity, 1392 }, 1393 .pm = { 1394 .misc = &evergreen_pm_misc, 1395 .prepare = &evergreen_pm_prepare, 1396 .finish = &evergreen_pm_finish, 1397 .init_profile = &r600_pm_init_profile, 1398 .get_dynpm_state = &r600_pm_get_dynpm_state, 1399 .get_engine_clock = &radeon_atom_get_engine_clock, 1400 .set_engine_clock = &radeon_atom_set_engine_clock, 1401 .get_memory_clock = &radeon_atom_get_memory_clock, 1402 .set_memory_clock = &radeon_atom_set_memory_clock, 1403 .get_pcie_lanes = &r600_get_pcie_lanes, 1404 .set_pcie_lanes = &r600_set_pcie_lanes, 1405 .set_clock_gating = NULL, 1406 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1407 .get_temperature = &evergreen_get_temp, 1408 }, 1409 .dpm = { 1410 .init = &cypress_dpm_init, 1411 .setup_asic = &cypress_dpm_setup_asic, 1412 .enable = &cypress_dpm_enable, 1413 .late_enable = &rv770_dpm_late_enable, 1414 .disable = &cypress_dpm_disable, 1415 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1416 .set_power_state = &cypress_dpm_set_power_state, 1417 .post_set_power_state = &r600_dpm_post_set_power_state, 1418 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1419 .fini = &cypress_dpm_fini, 1420 .get_sclk = &rv770_dpm_get_sclk, 1421 .get_mclk = &rv770_dpm_get_mclk, 1422 .print_power_state = &rv770_dpm_print_power_state, 1423 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1424 .force_performance_level = &rv770_dpm_force_performance_level, 1425 .vblank_too_short = &cypress_dpm_vblank_too_short, 1426 .get_current_sclk = &rv770_dpm_get_current_sclk, 1427 .get_current_mclk = &rv770_dpm_get_current_mclk, 1428 }, 1429 .pflip = { 1430 .page_flip = &evergreen_page_flip, 1431 .page_flip_pending = &evergreen_page_flip_pending, 1432 }, 1433 }; 1434 1435 static struct radeon_asic sumo_asic = { 1436 .init = &evergreen_init, 1437 .fini = &evergreen_fini, 1438 .suspend = &evergreen_suspend, 1439 .resume = &evergreen_resume, 1440 .asic_reset = &evergreen_asic_reset, 1441 .vga_set_state = &r600_vga_set_state, 1442 .mmio_hdp_flush = r600_mmio_hdp_flush, 1443 .gui_idle = &r600_gui_idle, 1444 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1445 .get_xclk = &r600_get_xclk, 1446 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1447 .get_allowed_info_register = evergreen_get_allowed_info_register, 1448 .gart = { 1449 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1450 .get_page_entry = &rs600_gart_get_page_entry, 1451 .set_page = &rs600_gart_set_page, 1452 }, 1453 .ring = { 1454 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1455 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1456 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1457 }, 1458 .irq = { 1459 .set = &evergreen_irq_set, 1460 .process = &evergreen_irq_process, 1461 }, 1462 .display = { 1463 .bandwidth_update = &evergreen_bandwidth_update, 1464 .get_vblank_counter = &evergreen_get_vblank_counter, 1465 .wait_for_vblank = &dce4_wait_for_vblank, 1466 .set_backlight_level = &atombios_set_backlight_level, 1467 .get_backlight_level = &atombios_get_backlight_level, 1468 }, 1469 .copy = { 1470 .blit = &r600_copy_cpdma, 1471 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1472 .dma = &evergreen_copy_dma, 1473 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1474 .copy = &evergreen_copy_dma, 1475 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1476 }, 1477 .surface = { 1478 .set_reg = r600_set_surface_reg, 1479 .clear_reg = r600_clear_surface_reg, 1480 }, 1481 .hpd = { 1482 .init = &evergreen_hpd_init, 1483 .fini = &evergreen_hpd_fini, 1484 .sense = &evergreen_hpd_sense, 1485 .set_polarity = &evergreen_hpd_set_polarity, 1486 }, 1487 .pm = { 1488 .misc = &evergreen_pm_misc, 1489 .prepare = &evergreen_pm_prepare, 1490 .finish = &evergreen_pm_finish, 1491 .init_profile = &sumo_pm_init_profile, 1492 .get_dynpm_state = &r600_pm_get_dynpm_state, 1493 .get_engine_clock = &radeon_atom_get_engine_clock, 1494 .set_engine_clock = &radeon_atom_set_engine_clock, 1495 .get_memory_clock = NULL, 1496 .set_memory_clock = NULL, 1497 .get_pcie_lanes = NULL, 1498 .set_pcie_lanes = NULL, 1499 .set_clock_gating = NULL, 1500 .set_uvd_clocks = &sumo_set_uvd_clocks, 1501 .get_temperature = &sumo_get_temp, 1502 }, 1503 .dpm = { 1504 .init = &sumo_dpm_init, 1505 .setup_asic = &sumo_dpm_setup_asic, 1506 .enable = &sumo_dpm_enable, 1507 .late_enable = &sumo_dpm_late_enable, 1508 .disable = &sumo_dpm_disable, 1509 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1510 .set_power_state = &sumo_dpm_set_power_state, 1511 .post_set_power_state = &sumo_dpm_post_set_power_state, 1512 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1513 .fini = &sumo_dpm_fini, 1514 .get_sclk = &sumo_dpm_get_sclk, 1515 .get_mclk = &sumo_dpm_get_mclk, 1516 .print_power_state = &sumo_dpm_print_power_state, 1517 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1518 .force_performance_level = &sumo_dpm_force_performance_level, 1519 .get_current_sclk = &sumo_dpm_get_current_sclk, 1520 .get_current_mclk = &sumo_dpm_get_current_mclk, 1521 }, 1522 .pflip = { 1523 .page_flip = &evergreen_page_flip, 1524 .page_flip_pending = &evergreen_page_flip_pending, 1525 }, 1526 }; 1527 1528 static struct radeon_asic btc_asic = { 1529 .init = &evergreen_init, 1530 .fini = &evergreen_fini, 1531 .suspend = &evergreen_suspend, 1532 .resume = &evergreen_resume, 1533 .asic_reset = &evergreen_asic_reset, 1534 .vga_set_state = &r600_vga_set_state, 1535 .mmio_hdp_flush = r600_mmio_hdp_flush, 1536 .gui_idle = &r600_gui_idle, 1537 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1538 .get_xclk = &rv770_get_xclk, 1539 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1540 .get_allowed_info_register = evergreen_get_allowed_info_register, 1541 .gart = { 1542 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1543 .get_page_entry = &rs600_gart_get_page_entry, 1544 .set_page = &rs600_gart_set_page, 1545 }, 1546 .ring = { 1547 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1548 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1549 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1550 }, 1551 .irq = { 1552 .set = &evergreen_irq_set, 1553 .process = &evergreen_irq_process, 1554 }, 1555 .display = { 1556 .bandwidth_update = &evergreen_bandwidth_update, 1557 .get_vblank_counter = &evergreen_get_vblank_counter, 1558 .wait_for_vblank = &dce4_wait_for_vblank, 1559 .set_backlight_level = &atombios_set_backlight_level, 1560 .get_backlight_level = &atombios_get_backlight_level, 1561 }, 1562 .copy = { 1563 .blit = &r600_copy_cpdma, 1564 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1565 .dma = &evergreen_copy_dma, 1566 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1567 .copy = &evergreen_copy_dma, 1568 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1569 }, 1570 .surface = { 1571 .set_reg = r600_set_surface_reg, 1572 .clear_reg = r600_clear_surface_reg, 1573 }, 1574 .hpd = { 1575 .init = &evergreen_hpd_init, 1576 .fini = &evergreen_hpd_fini, 1577 .sense = &evergreen_hpd_sense, 1578 .set_polarity = &evergreen_hpd_set_polarity, 1579 }, 1580 .pm = { 1581 .misc = &evergreen_pm_misc, 1582 .prepare = &evergreen_pm_prepare, 1583 .finish = &evergreen_pm_finish, 1584 .init_profile = &btc_pm_init_profile, 1585 .get_dynpm_state = &r600_pm_get_dynpm_state, 1586 .get_engine_clock = &radeon_atom_get_engine_clock, 1587 .set_engine_clock = &radeon_atom_set_engine_clock, 1588 .get_memory_clock = &radeon_atom_get_memory_clock, 1589 .set_memory_clock = &radeon_atom_set_memory_clock, 1590 .get_pcie_lanes = &r600_get_pcie_lanes, 1591 .set_pcie_lanes = &r600_set_pcie_lanes, 1592 .set_clock_gating = NULL, 1593 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1594 .get_temperature = &evergreen_get_temp, 1595 }, 1596 .dpm = { 1597 .init = &btc_dpm_init, 1598 .setup_asic = &btc_dpm_setup_asic, 1599 .enable = &btc_dpm_enable, 1600 .late_enable = &rv770_dpm_late_enable, 1601 .disable = &btc_dpm_disable, 1602 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1603 .set_power_state = &btc_dpm_set_power_state, 1604 .post_set_power_state = &btc_dpm_post_set_power_state, 1605 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1606 .fini = &btc_dpm_fini, 1607 .get_sclk = &btc_dpm_get_sclk, 1608 .get_mclk = &btc_dpm_get_mclk, 1609 .print_power_state = &rv770_dpm_print_power_state, 1610 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1611 .force_performance_level = &rv770_dpm_force_performance_level, 1612 .vblank_too_short = &btc_dpm_vblank_too_short, 1613 .get_current_sclk = &btc_dpm_get_current_sclk, 1614 .get_current_mclk = &btc_dpm_get_current_mclk, 1615 }, 1616 .pflip = { 1617 .page_flip = &evergreen_page_flip, 1618 .page_flip_pending = &evergreen_page_flip_pending, 1619 }, 1620 }; 1621 1622 static const struct radeon_asic_ring cayman_gfx_ring = { 1623 .ib_execute = &cayman_ring_ib_execute, 1624 .ib_parse = &evergreen_ib_parse, 1625 .emit_fence = &cayman_fence_ring_emit, 1626 .emit_semaphore = &r600_semaphore_ring_emit, 1627 .cs_parse = &evergreen_cs_parse, 1628 .ring_test = &r600_ring_test, 1629 .ib_test = &r600_ib_test, 1630 .is_lockup = &cayman_gfx_is_lockup, 1631 .vm_flush = &cayman_vm_flush, 1632 .get_rptr = &cayman_gfx_get_rptr, 1633 .get_wptr = &cayman_gfx_get_wptr, 1634 .set_wptr = &cayman_gfx_set_wptr, 1635 }; 1636 1637 static const struct radeon_asic_ring cayman_dma_ring = { 1638 .ib_execute = &cayman_dma_ring_ib_execute, 1639 .ib_parse = &evergreen_dma_ib_parse, 1640 .emit_fence = &evergreen_dma_fence_ring_emit, 1641 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1642 .cs_parse = &evergreen_dma_cs_parse, 1643 .ring_test = &r600_dma_ring_test, 1644 .ib_test = &r600_dma_ib_test, 1645 .is_lockup = &cayman_dma_is_lockup, 1646 .vm_flush = &cayman_dma_vm_flush, 1647 .get_rptr = &cayman_dma_get_rptr, 1648 .get_wptr = &cayman_dma_get_wptr, 1649 .set_wptr = &cayman_dma_set_wptr 1650 }; 1651 1652 static const struct radeon_asic_ring cayman_uvd_ring = { 1653 .ib_execute = &uvd_v1_0_ib_execute, 1654 .emit_fence = &uvd_v2_2_fence_emit, 1655 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1656 .cs_parse = &radeon_uvd_cs_parse, 1657 .ring_test = &uvd_v1_0_ring_test, 1658 .ib_test = &uvd_v1_0_ib_test, 1659 .is_lockup = &radeon_ring_test_lockup, 1660 .get_rptr = &uvd_v1_0_get_rptr, 1661 .get_wptr = &uvd_v1_0_get_wptr, 1662 .set_wptr = &uvd_v1_0_set_wptr, 1663 }; 1664 1665 static struct radeon_asic cayman_asic = { 1666 .init = &cayman_init, 1667 .fini = &cayman_fini, 1668 .suspend = &cayman_suspend, 1669 .resume = &cayman_resume, 1670 .asic_reset = &cayman_asic_reset, 1671 .vga_set_state = &r600_vga_set_state, 1672 .mmio_hdp_flush = r600_mmio_hdp_flush, 1673 .gui_idle = &r600_gui_idle, 1674 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1675 .get_xclk = &rv770_get_xclk, 1676 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1677 .get_allowed_info_register = cayman_get_allowed_info_register, 1678 .gart = { 1679 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1680 .get_page_entry = &rs600_gart_get_page_entry, 1681 .set_page = &rs600_gart_set_page, 1682 }, 1683 .vm = { 1684 .init = &cayman_vm_init, 1685 .fini = &cayman_vm_fini, 1686 .copy_pages = &cayman_dma_vm_copy_pages, 1687 .write_pages = &cayman_dma_vm_write_pages, 1688 .set_pages = &cayman_dma_vm_set_pages, 1689 .pad_ib = &cayman_dma_vm_pad_ib, 1690 }, 1691 .ring = { 1692 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1693 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1694 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1695 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1696 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1697 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1698 }, 1699 .irq = { 1700 .set = &evergreen_irq_set, 1701 .process = &evergreen_irq_process, 1702 }, 1703 .display = { 1704 .bandwidth_update = &evergreen_bandwidth_update, 1705 .get_vblank_counter = &evergreen_get_vblank_counter, 1706 .wait_for_vblank = &dce4_wait_for_vblank, 1707 .set_backlight_level = &atombios_set_backlight_level, 1708 .get_backlight_level = &atombios_get_backlight_level, 1709 }, 1710 .copy = { 1711 .blit = &r600_copy_cpdma, 1712 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1713 .dma = &evergreen_copy_dma, 1714 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1715 .copy = &evergreen_copy_dma, 1716 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1717 }, 1718 .surface = { 1719 .set_reg = r600_set_surface_reg, 1720 .clear_reg = r600_clear_surface_reg, 1721 }, 1722 .hpd = { 1723 .init = &evergreen_hpd_init, 1724 .fini = &evergreen_hpd_fini, 1725 .sense = &evergreen_hpd_sense, 1726 .set_polarity = &evergreen_hpd_set_polarity, 1727 }, 1728 .pm = { 1729 .misc = &evergreen_pm_misc, 1730 .prepare = &evergreen_pm_prepare, 1731 .finish = &evergreen_pm_finish, 1732 .init_profile = &btc_pm_init_profile, 1733 .get_dynpm_state = &r600_pm_get_dynpm_state, 1734 .get_engine_clock = &radeon_atom_get_engine_clock, 1735 .set_engine_clock = &radeon_atom_set_engine_clock, 1736 .get_memory_clock = &radeon_atom_get_memory_clock, 1737 .set_memory_clock = &radeon_atom_set_memory_clock, 1738 .get_pcie_lanes = &r600_get_pcie_lanes, 1739 .set_pcie_lanes = &r600_set_pcie_lanes, 1740 .set_clock_gating = NULL, 1741 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1742 .get_temperature = &evergreen_get_temp, 1743 }, 1744 .dpm = { 1745 .init = &ni_dpm_init, 1746 .setup_asic = &ni_dpm_setup_asic, 1747 .enable = &ni_dpm_enable, 1748 .late_enable = &rv770_dpm_late_enable, 1749 .disable = &ni_dpm_disable, 1750 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1751 .set_power_state = &ni_dpm_set_power_state, 1752 .post_set_power_state = &ni_dpm_post_set_power_state, 1753 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1754 .fini = &ni_dpm_fini, 1755 .get_sclk = &ni_dpm_get_sclk, 1756 .get_mclk = &ni_dpm_get_mclk, 1757 .print_power_state = &ni_dpm_print_power_state, 1758 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1759 .force_performance_level = &ni_dpm_force_performance_level, 1760 .vblank_too_short = &ni_dpm_vblank_too_short, 1761 .get_current_sclk = &ni_dpm_get_current_sclk, 1762 .get_current_mclk = &ni_dpm_get_current_mclk, 1763 }, 1764 .pflip = { 1765 .page_flip = &evergreen_page_flip, 1766 .page_flip_pending = &evergreen_page_flip_pending, 1767 }, 1768 }; 1769 1770 static const struct radeon_asic_ring trinity_vce_ring = { 1771 .ib_execute = &radeon_vce_ib_execute, 1772 .emit_fence = &radeon_vce_fence_emit, 1773 .emit_semaphore = &radeon_vce_semaphore_emit, 1774 .cs_parse = &radeon_vce_cs_parse, 1775 .ring_test = &radeon_vce_ring_test, 1776 .ib_test = &radeon_vce_ib_test, 1777 .is_lockup = &radeon_ring_test_lockup, 1778 .get_rptr = &vce_v1_0_get_rptr, 1779 .get_wptr = &vce_v1_0_get_wptr, 1780 .set_wptr = &vce_v1_0_set_wptr, 1781 }; 1782 1783 static struct radeon_asic trinity_asic = { 1784 .init = &cayman_init, 1785 .fini = &cayman_fini, 1786 .suspend = &cayman_suspend, 1787 .resume = &cayman_resume, 1788 .asic_reset = &cayman_asic_reset, 1789 .vga_set_state = &r600_vga_set_state, 1790 .mmio_hdp_flush = r600_mmio_hdp_flush, 1791 .gui_idle = &r600_gui_idle, 1792 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1793 .get_xclk = &r600_get_xclk, 1794 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1795 .get_allowed_info_register = cayman_get_allowed_info_register, 1796 .gart = { 1797 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1798 .get_page_entry = &rs600_gart_get_page_entry, 1799 .set_page = &rs600_gart_set_page, 1800 }, 1801 .vm = { 1802 .init = &cayman_vm_init, 1803 .fini = &cayman_vm_fini, 1804 .copy_pages = &cayman_dma_vm_copy_pages, 1805 .write_pages = &cayman_dma_vm_write_pages, 1806 .set_pages = &cayman_dma_vm_set_pages, 1807 .pad_ib = &cayman_dma_vm_pad_ib, 1808 }, 1809 .ring = { 1810 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1811 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1812 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1813 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1814 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1815 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1816 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1817 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1818 }, 1819 .irq = { 1820 .set = &evergreen_irq_set, 1821 .process = &evergreen_irq_process, 1822 }, 1823 .display = { 1824 .bandwidth_update = &dce6_bandwidth_update, 1825 .get_vblank_counter = &evergreen_get_vblank_counter, 1826 .wait_for_vblank = &dce4_wait_for_vblank, 1827 .set_backlight_level = &atombios_set_backlight_level, 1828 .get_backlight_level = &atombios_get_backlight_level, 1829 }, 1830 .copy = { 1831 .blit = &r600_copy_cpdma, 1832 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1833 .dma = &evergreen_copy_dma, 1834 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1835 .copy = &evergreen_copy_dma, 1836 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1837 }, 1838 .surface = { 1839 .set_reg = r600_set_surface_reg, 1840 .clear_reg = r600_clear_surface_reg, 1841 }, 1842 .hpd = { 1843 .init = &evergreen_hpd_init, 1844 .fini = &evergreen_hpd_fini, 1845 .sense = &evergreen_hpd_sense, 1846 .set_polarity = &evergreen_hpd_set_polarity, 1847 }, 1848 .pm = { 1849 .misc = &evergreen_pm_misc, 1850 .prepare = &evergreen_pm_prepare, 1851 .finish = &evergreen_pm_finish, 1852 .init_profile = &sumo_pm_init_profile, 1853 .get_dynpm_state = &r600_pm_get_dynpm_state, 1854 .get_engine_clock = &radeon_atom_get_engine_clock, 1855 .set_engine_clock = &radeon_atom_set_engine_clock, 1856 .get_memory_clock = NULL, 1857 .set_memory_clock = NULL, 1858 .get_pcie_lanes = NULL, 1859 .set_pcie_lanes = NULL, 1860 .set_clock_gating = NULL, 1861 .set_uvd_clocks = &sumo_set_uvd_clocks, 1862 .set_vce_clocks = &tn_set_vce_clocks, 1863 .get_temperature = &tn_get_temp, 1864 }, 1865 .dpm = { 1866 .init = &trinity_dpm_init, 1867 .setup_asic = &trinity_dpm_setup_asic, 1868 .enable = &trinity_dpm_enable, 1869 .late_enable = &trinity_dpm_late_enable, 1870 .disable = &trinity_dpm_disable, 1871 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1872 .set_power_state = &trinity_dpm_set_power_state, 1873 .post_set_power_state = &trinity_dpm_post_set_power_state, 1874 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1875 .fini = &trinity_dpm_fini, 1876 .get_sclk = &trinity_dpm_get_sclk, 1877 .get_mclk = &trinity_dpm_get_mclk, 1878 .print_power_state = &trinity_dpm_print_power_state, 1879 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1880 .force_performance_level = &trinity_dpm_force_performance_level, 1881 .enable_bapm = &trinity_dpm_enable_bapm, 1882 .get_current_sclk = &trinity_dpm_get_current_sclk, 1883 .get_current_mclk = &trinity_dpm_get_current_mclk, 1884 }, 1885 .pflip = { 1886 .page_flip = &evergreen_page_flip, 1887 .page_flip_pending = &evergreen_page_flip_pending, 1888 }, 1889 }; 1890 1891 static const struct radeon_asic_ring si_gfx_ring = { 1892 .ib_execute = &si_ring_ib_execute, 1893 .ib_parse = &si_ib_parse, 1894 .emit_fence = &si_fence_ring_emit, 1895 .emit_semaphore = &r600_semaphore_ring_emit, 1896 .cs_parse = NULL, 1897 .ring_test = &r600_ring_test, 1898 .ib_test = &r600_ib_test, 1899 .is_lockup = &si_gfx_is_lockup, 1900 .vm_flush = &si_vm_flush, 1901 .get_rptr = &cayman_gfx_get_rptr, 1902 .get_wptr = &cayman_gfx_get_wptr, 1903 .set_wptr = &cayman_gfx_set_wptr, 1904 }; 1905 1906 static const struct radeon_asic_ring si_dma_ring = { 1907 .ib_execute = &cayman_dma_ring_ib_execute, 1908 .ib_parse = &evergreen_dma_ib_parse, 1909 .emit_fence = &evergreen_dma_fence_ring_emit, 1910 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1911 .cs_parse = NULL, 1912 .ring_test = &r600_dma_ring_test, 1913 .ib_test = &r600_dma_ib_test, 1914 .is_lockup = &si_dma_is_lockup, 1915 .vm_flush = &si_dma_vm_flush, 1916 .get_rptr = &cayman_dma_get_rptr, 1917 .get_wptr = &cayman_dma_get_wptr, 1918 .set_wptr = &cayman_dma_set_wptr, 1919 }; 1920 1921 static struct radeon_asic si_asic = { 1922 .init = &si_init, 1923 .fini = &si_fini, 1924 .suspend = &si_suspend, 1925 .resume = &si_resume, 1926 .asic_reset = &si_asic_reset, 1927 .vga_set_state = &r600_vga_set_state, 1928 .mmio_hdp_flush = r600_mmio_hdp_flush, 1929 .gui_idle = &r600_gui_idle, 1930 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1931 .get_xclk = &si_get_xclk, 1932 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1933 .get_allowed_info_register = si_get_allowed_info_register, 1934 .gart = { 1935 .tlb_flush = &si_pcie_gart_tlb_flush, 1936 .get_page_entry = &rs600_gart_get_page_entry, 1937 .set_page = &rs600_gart_set_page, 1938 }, 1939 .vm = { 1940 .init = &si_vm_init, 1941 .fini = &si_vm_fini, 1942 .copy_pages = &si_dma_vm_copy_pages, 1943 .write_pages = &si_dma_vm_write_pages, 1944 .set_pages = &si_dma_vm_set_pages, 1945 .pad_ib = &cayman_dma_vm_pad_ib, 1946 }, 1947 .ring = { 1948 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1949 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1950 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1951 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1952 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1953 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1954 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1955 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1956 }, 1957 .irq = { 1958 .set = &si_irq_set, 1959 .process = &si_irq_process, 1960 }, 1961 .display = { 1962 .bandwidth_update = &dce6_bandwidth_update, 1963 .get_vblank_counter = &evergreen_get_vblank_counter, 1964 .wait_for_vblank = &dce4_wait_for_vblank, 1965 .set_backlight_level = &atombios_set_backlight_level, 1966 .get_backlight_level = &atombios_get_backlight_level, 1967 }, 1968 .copy = { 1969 .blit = &r600_copy_cpdma, 1970 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1971 .dma = &si_copy_dma, 1972 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1973 .copy = &si_copy_dma, 1974 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1975 }, 1976 .surface = { 1977 .set_reg = r600_set_surface_reg, 1978 .clear_reg = r600_clear_surface_reg, 1979 }, 1980 .hpd = { 1981 .init = &evergreen_hpd_init, 1982 .fini = &evergreen_hpd_fini, 1983 .sense = &evergreen_hpd_sense, 1984 .set_polarity = &evergreen_hpd_set_polarity, 1985 }, 1986 .pm = { 1987 .misc = &evergreen_pm_misc, 1988 .prepare = &evergreen_pm_prepare, 1989 .finish = &evergreen_pm_finish, 1990 .init_profile = &sumo_pm_init_profile, 1991 .get_dynpm_state = &r600_pm_get_dynpm_state, 1992 .get_engine_clock = &radeon_atom_get_engine_clock, 1993 .set_engine_clock = &radeon_atom_set_engine_clock, 1994 .get_memory_clock = &radeon_atom_get_memory_clock, 1995 .set_memory_clock = &radeon_atom_set_memory_clock, 1996 .get_pcie_lanes = &r600_get_pcie_lanes, 1997 .set_pcie_lanes = &r600_set_pcie_lanes, 1998 .set_clock_gating = NULL, 1999 .set_uvd_clocks = &si_set_uvd_clocks, 2000 .set_vce_clocks = &si_set_vce_clocks, 2001 .get_temperature = &si_get_temp, 2002 }, 2003 .dpm = { 2004 .init = &si_dpm_init, 2005 .setup_asic = &si_dpm_setup_asic, 2006 .enable = &si_dpm_enable, 2007 .late_enable = &si_dpm_late_enable, 2008 .disable = &si_dpm_disable, 2009 .pre_set_power_state = &si_dpm_pre_set_power_state, 2010 .set_power_state = &si_dpm_set_power_state, 2011 .post_set_power_state = &si_dpm_post_set_power_state, 2012 .display_configuration_changed = &si_dpm_display_configuration_changed, 2013 .fini = &si_dpm_fini, 2014 .get_sclk = &ni_dpm_get_sclk, 2015 .get_mclk = &ni_dpm_get_mclk, 2016 .print_power_state = &ni_dpm_print_power_state, 2017 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2018 .force_performance_level = &si_dpm_force_performance_level, 2019 .vblank_too_short = &ni_dpm_vblank_too_short, 2020 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, 2021 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, 2022 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, 2023 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, 2024 .get_current_sclk = &si_dpm_get_current_sclk, 2025 .get_current_mclk = &si_dpm_get_current_mclk, 2026 }, 2027 .pflip = { 2028 .page_flip = &evergreen_page_flip, 2029 .page_flip_pending = &evergreen_page_flip_pending, 2030 }, 2031 }; 2032 2033 static const struct radeon_asic_ring ci_gfx_ring = { 2034 .ib_execute = &cik_ring_ib_execute, 2035 .ib_parse = &cik_ib_parse, 2036 .emit_fence = &cik_fence_gfx_ring_emit, 2037 .emit_semaphore = &cik_semaphore_ring_emit, 2038 .cs_parse = NULL, 2039 .ring_test = &cik_ring_test, 2040 .ib_test = &cik_ib_test, 2041 .is_lockup = &cik_gfx_is_lockup, 2042 .vm_flush = &cik_vm_flush, 2043 .get_rptr = &cik_gfx_get_rptr, 2044 .get_wptr = &cik_gfx_get_wptr, 2045 .set_wptr = &cik_gfx_set_wptr, 2046 }; 2047 2048 static const struct radeon_asic_ring ci_cp_ring = { 2049 .ib_execute = &cik_ring_ib_execute, 2050 .ib_parse = &cik_ib_parse, 2051 .emit_fence = &cik_fence_compute_ring_emit, 2052 .emit_semaphore = &cik_semaphore_ring_emit, 2053 .cs_parse = NULL, 2054 .ring_test = &cik_ring_test, 2055 .ib_test = &cik_ib_test, 2056 .is_lockup = &cik_gfx_is_lockup, 2057 .vm_flush = &cik_vm_flush, 2058 .get_rptr = &cik_compute_get_rptr, 2059 .get_wptr = &cik_compute_get_wptr, 2060 .set_wptr = &cik_compute_set_wptr, 2061 }; 2062 2063 static const struct radeon_asic_ring ci_dma_ring = { 2064 .ib_execute = &cik_sdma_ring_ib_execute, 2065 .ib_parse = &cik_ib_parse, 2066 .emit_fence = &cik_sdma_fence_ring_emit, 2067 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2068 .cs_parse = NULL, 2069 .ring_test = &cik_sdma_ring_test, 2070 .ib_test = &cik_sdma_ib_test, 2071 .is_lockup = &cik_sdma_is_lockup, 2072 .vm_flush = &cik_dma_vm_flush, 2073 .get_rptr = &cik_sdma_get_rptr, 2074 .get_wptr = &cik_sdma_get_wptr, 2075 .set_wptr = &cik_sdma_set_wptr, 2076 }; 2077 2078 static const struct radeon_asic_ring ci_vce_ring = { 2079 .ib_execute = &radeon_vce_ib_execute, 2080 .emit_fence = &radeon_vce_fence_emit, 2081 .emit_semaphore = &radeon_vce_semaphore_emit, 2082 .cs_parse = &radeon_vce_cs_parse, 2083 .ring_test = &radeon_vce_ring_test, 2084 .ib_test = &radeon_vce_ib_test, 2085 .is_lockup = &radeon_ring_test_lockup, 2086 .get_rptr = &vce_v1_0_get_rptr, 2087 .get_wptr = &vce_v1_0_get_wptr, 2088 .set_wptr = &vce_v1_0_set_wptr, 2089 }; 2090 2091 static struct radeon_asic ci_asic = { 2092 .init = &cik_init, 2093 .fini = &cik_fini, 2094 .suspend = &cik_suspend, 2095 .resume = &cik_resume, 2096 .asic_reset = &cik_asic_reset, 2097 .vga_set_state = &r600_vga_set_state, 2098 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2099 .gui_idle = &r600_gui_idle, 2100 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2101 .get_xclk = &cik_get_xclk, 2102 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2103 .get_allowed_info_register = cik_get_allowed_info_register, 2104 .gart = { 2105 .tlb_flush = &cik_pcie_gart_tlb_flush, 2106 .get_page_entry = &rs600_gart_get_page_entry, 2107 .set_page = &rs600_gart_set_page, 2108 }, 2109 .vm = { 2110 .init = &cik_vm_init, 2111 .fini = &cik_vm_fini, 2112 .copy_pages = &cik_sdma_vm_copy_pages, 2113 .write_pages = &cik_sdma_vm_write_pages, 2114 .set_pages = &cik_sdma_vm_set_pages, 2115 .pad_ib = &cik_sdma_vm_pad_ib, 2116 }, 2117 .ring = { 2118 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2119 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2120 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2121 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2122 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2123 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2124 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2125 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2126 }, 2127 .irq = { 2128 .set = &cik_irq_set, 2129 .process = &cik_irq_process, 2130 }, 2131 .display = { 2132 .bandwidth_update = &dce8_bandwidth_update, 2133 .get_vblank_counter = &evergreen_get_vblank_counter, 2134 .wait_for_vblank = &dce4_wait_for_vblank, 2135 .set_backlight_level = &atombios_set_backlight_level, 2136 .get_backlight_level = &atombios_get_backlight_level, 2137 }, 2138 .copy = { 2139 .blit = &cik_copy_cpdma, 2140 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2141 .dma = &cik_copy_dma, 2142 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2143 .copy = &cik_copy_dma, 2144 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2145 }, 2146 .surface = { 2147 .set_reg = r600_set_surface_reg, 2148 .clear_reg = r600_clear_surface_reg, 2149 }, 2150 .hpd = { 2151 .init = &evergreen_hpd_init, 2152 .fini = &evergreen_hpd_fini, 2153 .sense = &evergreen_hpd_sense, 2154 .set_polarity = &evergreen_hpd_set_polarity, 2155 }, 2156 .pm = { 2157 .misc = &evergreen_pm_misc, 2158 .prepare = &evergreen_pm_prepare, 2159 .finish = &evergreen_pm_finish, 2160 .init_profile = &sumo_pm_init_profile, 2161 .get_dynpm_state = &r600_pm_get_dynpm_state, 2162 .get_engine_clock = &radeon_atom_get_engine_clock, 2163 .set_engine_clock = &radeon_atom_set_engine_clock, 2164 .get_memory_clock = &radeon_atom_get_memory_clock, 2165 .set_memory_clock = &radeon_atom_set_memory_clock, 2166 .get_pcie_lanes = NULL, 2167 .set_pcie_lanes = NULL, 2168 .set_clock_gating = NULL, 2169 .set_uvd_clocks = &cik_set_uvd_clocks, 2170 .set_vce_clocks = &cik_set_vce_clocks, 2171 .get_temperature = &ci_get_temp, 2172 }, 2173 .dpm = { 2174 .init = &ci_dpm_init, 2175 .setup_asic = &ci_dpm_setup_asic, 2176 .enable = &ci_dpm_enable, 2177 .late_enable = &ci_dpm_late_enable, 2178 .disable = &ci_dpm_disable, 2179 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2180 .set_power_state = &ci_dpm_set_power_state, 2181 .post_set_power_state = &ci_dpm_post_set_power_state, 2182 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2183 .fini = &ci_dpm_fini, 2184 .get_sclk = &ci_dpm_get_sclk, 2185 .get_mclk = &ci_dpm_get_mclk, 2186 .print_power_state = &ci_dpm_print_power_state, 2187 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2188 .force_performance_level = &ci_dpm_force_performance_level, 2189 .vblank_too_short = &ci_dpm_vblank_too_short, 2190 .powergate_uvd = &ci_dpm_powergate_uvd, 2191 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, 2192 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, 2193 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, 2194 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, 2195 .get_current_sclk = &ci_dpm_get_current_sclk, 2196 .get_current_mclk = &ci_dpm_get_current_mclk, 2197 }, 2198 .pflip = { 2199 .page_flip = &evergreen_page_flip, 2200 .page_flip_pending = &evergreen_page_flip_pending, 2201 }, 2202 }; 2203 2204 static struct radeon_asic kv_asic = { 2205 .init = &cik_init, 2206 .fini = &cik_fini, 2207 .suspend = &cik_suspend, 2208 .resume = &cik_resume, 2209 .asic_reset = &cik_asic_reset, 2210 .vga_set_state = &r600_vga_set_state, 2211 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2212 .gui_idle = &r600_gui_idle, 2213 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2214 .get_xclk = &cik_get_xclk, 2215 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2216 .get_allowed_info_register = cik_get_allowed_info_register, 2217 .gart = { 2218 .tlb_flush = &cik_pcie_gart_tlb_flush, 2219 .get_page_entry = &rs600_gart_get_page_entry, 2220 .set_page = &rs600_gart_set_page, 2221 }, 2222 .vm = { 2223 .init = &cik_vm_init, 2224 .fini = &cik_vm_fini, 2225 .copy_pages = &cik_sdma_vm_copy_pages, 2226 .write_pages = &cik_sdma_vm_write_pages, 2227 .set_pages = &cik_sdma_vm_set_pages, 2228 .pad_ib = &cik_sdma_vm_pad_ib, 2229 }, 2230 .ring = { 2231 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2232 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2233 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2234 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2235 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2236 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2237 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2238 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2239 }, 2240 .irq = { 2241 .set = &cik_irq_set, 2242 .process = &cik_irq_process, 2243 }, 2244 .display = { 2245 .bandwidth_update = &dce8_bandwidth_update, 2246 .get_vblank_counter = &evergreen_get_vblank_counter, 2247 .wait_for_vblank = &dce4_wait_for_vblank, 2248 .set_backlight_level = &atombios_set_backlight_level, 2249 .get_backlight_level = &atombios_get_backlight_level, 2250 }, 2251 .copy = { 2252 .blit = &cik_copy_cpdma, 2253 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2254 .dma = &cik_copy_dma, 2255 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2256 .copy = &cik_copy_dma, 2257 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2258 }, 2259 .surface = { 2260 .set_reg = r600_set_surface_reg, 2261 .clear_reg = r600_clear_surface_reg, 2262 }, 2263 .hpd = { 2264 .init = &evergreen_hpd_init, 2265 .fini = &evergreen_hpd_fini, 2266 .sense = &evergreen_hpd_sense, 2267 .set_polarity = &evergreen_hpd_set_polarity, 2268 }, 2269 .pm = { 2270 .misc = &evergreen_pm_misc, 2271 .prepare = &evergreen_pm_prepare, 2272 .finish = &evergreen_pm_finish, 2273 .init_profile = &sumo_pm_init_profile, 2274 .get_dynpm_state = &r600_pm_get_dynpm_state, 2275 .get_engine_clock = &radeon_atom_get_engine_clock, 2276 .set_engine_clock = &radeon_atom_set_engine_clock, 2277 .get_memory_clock = &radeon_atom_get_memory_clock, 2278 .set_memory_clock = &radeon_atom_set_memory_clock, 2279 .get_pcie_lanes = NULL, 2280 .set_pcie_lanes = NULL, 2281 .set_clock_gating = NULL, 2282 .set_uvd_clocks = &cik_set_uvd_clocks, 2283 .set_vce_clocks = &cik_set_vce_clocks, 2284 .get_temperature = &kv_get_temp, 2285 }, 2286 .dpm = { 2287 .init = &kv_dpm_init, 2288 .setup_asic = &kv_dpm_setup_asic, 2289 .enable = &kv_dpm_enable, 2290 .late_enable = &kv_dpm_late_enable, 2291 .disable = &kv_dpm_disable, 2292 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2293 .set_power_state = &kv_dpm_set_power_state, 2294 .post_set_power_state = &kv_dpm_post_set_power_state, 2295 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2296 .fini = &kv_dpm_fini, 2297 .get_sclk = &kv_dpm_get_sclk, 2298 .get_mclk = &kv_dpm_get_mclk, 2299 .print_power_state = &kv_dpm_print_power_state, 2300 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2301 .force_performance_level = &kv_dpm_force_performance_level, 2302 .powergate_uvd = &kv_dpm_powergate_uvd, 2303 .enable_bapm = &kv_dpm_enable_bapm, 2304 .get_current_sclk = &kv_dpm_get_current_sclk, 2305 .get_current_mclk = &kv_dpm_get_current_mclk, 2306 }, 2307 .pflip = { 2308 .page_flip = &evergreen_page_flip, 2309 .page_flip_pending = &evergreen_page_flip_pending, 2310 }, 2311 }; 2312 2313 /** 2314 * radeon_asic_init - register asic specific callbacks 2315 * 2316 * @rdev: radeon device pointer 2317 * 2318 * Registers the appropriate asic specific callbacks for each 2319 * chip family. Also sets other asics specific info like the number 2320 * of crtcs and the register aperture accessors (all asics). 2321 * Returns 0 for success. 2322 */ 2323 int radeon_asic_init(struct radeon_device *rdev) 2324 { 2325 radeon_register_accessor_init(rdev); 2326 2327 /* set the number of crtcs */ 2328 if (rdev->flags & RADEON_SINGLE_CRTC) 2329 rdev->num_crtc = 1; 2330 else 2331 rdev->num_crtc = 2; 2332 2333 rdev->has_uvd = false; 2334 rdev->has_vce = false; 2335 2336 switch (rdev->family) { 2337 case CHIP_R100: 2338 case CHIP_RV100: 2339 case CHIP_RS100: 2340 case CHIP_RV200: 2341 case CHIP_RS200: 2342 rdev->asic = &r100_asic; 2343 break; 2344 case CHIP_R200: 2345 case CHIP_RV250: 2346 case CHIP_RS300: 2347 case CHIP_RV280: 2348 rdev->asic = &r200_asic; 2349 break; 2350 case CHIP_R300: 2351 case CHIP_R350: 2352 case CHIP_RV350: 2353 case CHIP_RV380: 2354 if (rdev->flags & RADEON_IS_PCIE) 2355 rdev->asic = &r300_asic_pcie; 2356 else 2357 rdev->asic = &r300_asic; 2358 break; 2359 case CHIP_R420: 2360 case CHIP_R423: 2361 case CHIP_RV410: 2362 rdev->asic = &r420_asic; 2363 /* handle macs */ 2364 if (rdev->bios == NULL) { 2365 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2366 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2367 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2368 rdev->asic->pm.set_memory_clock = NULL; 2369 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2370 } 2371 break; 2372 case CHIP_RS400: 2373 case CHIP_RS480: 2374 rdev->asic = &rs400_asic; 2375 break; 2376 case CHIP_RS600: 2377 rdev->asic = &rs600_asic; 2378 break; 2379 case CHIP_RS690: 2380 case CHIP_RS740: 2381 rdev->asic = &rs690_asic; 2382 break; 2383 case CHIP_RV515: 2384 rdev->asic = &rv515_asic; 2385 break; 2386 case CHIP_R520: 2387 case CHIP_RV530: 2388 case CHIP_RV560: 2389 case CHIP_RV570: 2390 case CHIP_R580: 2391 rdev->asic = &r520_asic; 2392 break; 2393 case CHIP_R600: 2394 rdev->asic = &r600_asic; 2395 break; 2396 case CHIP_RV610: 2397 case CHIP_RV630: 2398 case CHIP_RV620: 2399 case CHIP_RV635: 2400 case CHIP_RV670: 2401 rdev->asic = &rv6xx_asic; 2402 rdev->has_uvd = true; 2403 break; 2404 case CHIP_RS780: 2405 case CHIP_RS880: 2406 rdev->asic = &rs780_asic; 2407 /* 760G/780V/880V don't have UVD */ 2408 if ((rdev->pdev->device == 0x9616)|| 2409 (rdev->pdev->device == 0x9611)|| 2410 (rdev->pdev->device == 0x9613)|| 2411 (rdev->pdev->device == 0x9711)|| 2412 (rdev->pdev->device == 0x9713)) 2413 rdev->has_uvd = false; 2414 else 2415 rdev->has_uvd = true; 2416 break; 2417 case CHIP_RV770: 2418 case CHIP_RV730: 2419 case CHIP_RV710: 2420 case CHIP_RV740: 2421 rdev->asic = &rv770_asic; 2422 rdev->has_uvd = true; 2423 break; 2424 case CHIP_CEDAR: 2425 case CHIP_REDWOOD: 2426 case CHIP_JUNIPER: 2427 case CHIP_CYPRESS: 2428 case CHIP_HEMLOCK: 2429 /* set num crtcs */ 2430 if (rdev->family == CHIP_CEDAR) 2431 rdev->num_crtc = 4; 2432 else 2433 rdev->num_crtc = 6; 2434 rdev->asic = &evergreen_asic; 2435 rdev->has_uvd = true; 2436 break; 2437 case CHIP_PALM: 2438 case CHIP_SUMO: 2439 case CHIP_SUMO2: 2440 rdev->asic = &sumo_asic; 2441 rdev->has_uvd = true; 2442 break; 2443 case CHIP_BARTS: 2444 case CHIP_TURKS: 2445 case CHIP_CAICOS: 2446 /* set num crtcs */ 2447 if (rdev->family == CHIP_CAICOS) 2448 rdev->num_crtc = 4; 2449 else 2450 rdev->num_crtc = 6; 2451 rdev->asic = &btc_asic; 2452 rdev->has_uvd = true; 2453 break; 2454 case CHIP_CAYMAN: 2455 rdev->asic = &cayman_asic; 2456 /* set num crtcs */ 2457 rdev->num_crtc = 6; 2458 rdev->has_uvd = true; 2459 break; 2460 case CHIP_ARUBA: 2461 rdev->asic = &trinity_asic; 2462 /* set num crtcs */ 2463 rdev->num_crtc = 4; 2464 rdev->has_uvd = true; 2465 rdev->has_vce = true; 2466 rdev->cg_flags = 2467 RADEON_CG_SUPPORT_VCE_MGCG; 2468 break; 2469 case CHIP_TAHITI: 2470 case CHIP_PITCAIRN: 2471 case CHIP_VERDE: 2472 case CHIP_OLAND: 2473 case CHIP_HAINAN: 2474 rdev->asic = &si_asic; 2475 /* set num crtcs */ 2476 if (rdev->family == CHIP_HAINAN) 2477 rdev->num_crtc = 0; 2478 else if (rdev->family == CHIP_OLAND) 2479 rdev->num_crtc = 2; 2480 else 2481 rdev->num_crtc = 6; 2482 if (rdev->family == CHIP_HAINAN) { 2483 rdev->has_uvd = false; 2484 rdev->has_vce = false; 2485 } else { 2486 rdev->has_uvd = true; 2487 rdev->has_vce = true; 2488 } 2489 switch (rdev->family) { 2490 case CHIP_TAHITI: 2491 rdev->cg_flags = 2492 RADEON_CG_SUPPORT_GFX_MGCG | 2493 RADEON_CG_SUPPORT_GFX_MGLS | 2494 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2495 RADEON_CG_SUPPORT_GFX_CGLS | 2496 RADEON_CG_SUPPORT_GFX_CGTS | 2497 RADEON_CG_SUPPORT_GFX_CP_LS | 2498 RADEON_CG_SUPPORT_MC_MGCG | 2499 RADEON_CG_SUPPORT_SDMA_MGCG | 2500 RADEON_CG_SUPPORT_BIF_LS | 2501 RADEON_CG_SUPPORT_VCE_MGCG | 2502 RADEON_CG_SUPPORT_UVD_MGCG | 2503 RADEON_CG_SUPPORT_HDP_LS | 2504 RADEON_CG_SUPPORT_HDP_MGCG; 2505 rdev->pg_flags = 0; 2506 break; 2507 case CHIP_PITCAIRN: 2508 rdev->cg_flags = 2509 RADEON_CG_SUPPORT_GFX_MGCG | 2510 RADEON_CG_SUPPORT_GFX_MGLS | 2511 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2512 RADEON_CG_SUPPORT_GFX_CGLS | 2513 RADEON_CG_SUPPORT_GFX_CGTS | 2514 RADEON_CG_SUPPORT_GFX_CP_LS | 2515 RADEON_CG_SUPPORT_GFX_RLC_LS | 2516 RADEON_CG_SUPPORT_MC_LS | 2517 RADEON_CG_SUPPORT_MC_MGCG | 2518 RADEON_CG_SUPPORT_SDMA_MGCG | 2519 RADEON_CG_SUPPORT_BIF_LS | 2520 RADEON_CG_SUPPORT_VCE_MGCG | 2521 RADEON_CG_SUPPORT_UVD_MGCG | 2522 RADEON_CG_SUPPORT_HDP_LS | 2523 RADEON_CG_SUPPORT_HDP_MGCG; 2524 rdev->pg_flags = 0; 2525 break; 2526 case CHIP_VERDE: 2527 rdev->cg_flags = 2528 RADEON_CG_SUPPORT_GFX_MGCG | 2529 RADEON_CG_SUPPORT_GFX_MGLS | 2530 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2531 RADEON_CG_SUPPORT_GFX_CGLS | 2532 RADEON_CG_SUPPORT_GFX_CGTS | 2533 RADEON_CG_SUPPORT_GFX_CP_LS | 2534 RADEON_CG_SUPPORT_GFX_RLC_LS | 2535 RADEON_CG_SUPPORT_MC_LS | 2536 RADEON_CG_SUPPORT_MC_MGCG | 2537 RADEON_CG_SUPPORT_SDMA_MGCG | 2538 RADEON_CG_SUPPORT_BIF_LS | 2539 RADEON_CG_SUPPORT_VCE_MGCG | 2540 RADEON_CG_SUPPORT_UVD_MGCG | 2541 RADEON_CG_SUPPORT_HDP_LS | 2542 RADEON_CG_SUPPORT_HDP_MGCG; 2543 rdev->pg_flags = 0 | 2544 /*RADEON_PG_SUPPORT_GFX_PG | */ 2545 RADEON_PG_SUPPORT_SDMA; 2546 break; 2547 case CHIP_OLAND: 2548 rdev->cg_flags = 2549 RADEON_CG_SUPPORT_GFX_MGCG | 2550 RADEON_CG_SUPPORT_GFX_MGLS | 2551 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2552 RADEON_CG_SUPPORT_GFX_CGLS | 2553 RADEON_CG_SUPPORT_GFX_CGTS | 2554 RADEON_CG_SUPPORT_GFX_CP_LS | 2555 RADEON_CG_SUPPORT_GFX_RLC_LS | 2556 RADEON_CG_SUPPORT_MC_LS | 2557 RADEON_CG_SUPPORT_MC_MGCG | 2558 RADEON_CG_SUPPORT_SDMA_MGCG | 2559 RADEON_CG_SUPPORT_BIF_LS | 2560 RADEON_CG_SUPPORT_UVD_MGCG | 2561 RADEON_CG_SUPPORT_HDP_LS | 2562 RADEON_CG_SUPPORT_HDP_MGCG; 2563 rdev->pg_flags = 0; 2564 break; 2565 case CHIP_HAINAN: 2566 rdev->cg_flags = 2567 RADEON_CG_SUPPORT_GFX_MGCG | 2568 RADEON_CG_SUPPORT_GFX_MGLS | 2569 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2570 RADEON_CG_SUPPORT_GFX_CGLS | 2571 RADEON_CG_SUPPORT_GFX_CGTS | 2572 RADEON_CG_SUPPORT_GFX_CP_LS | 2573 RADEON_CG_SUPPORT_GFX_RLC_LS | 2574 RADEON_CG_SUPPORT_MC_LS | 2575 RADEON_CG_SUPPORT_MC_MGCG | 2576 RADEON_CG_SUPPORT_SDMA_MGCG | 2577 RADEON_CG_SUPPORT_BIF_LS | 2578 RADEON_CG_SUPPORT_HDP_LS | 2579 RADEON_CG_SUPPORT_HDP_MGCG; 2580 rdev->pg_flags = 0; 2581 break; 2582 default: 2583 rdev->cg_flags = 0; 2584 rdev->pg_flags = 0; 2585 break; 2586 } 2587 break; 2588 case CHIP_BONAIRE: 2589 case CHIP_HAWAII: 2590 rdev->asic = &ci_asic; 2591 rdev->num_crtc = 6; 2592 rdev->has_uvd = true; 2593 rdev->has_vce = true; 2594 if (rdev->family == CHIP_BONAIRE) { 2595 rdev->cg_flags = 2596 RADEON_CG_SUPPORT_GFX_MGCG | 2597 RADEON_CG_SUPPORT_GFX_MGLS | 2598 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2599 RADEON_CG_SUPPORT_GFX_CGLS | 2600 RADEON_CG_SUPPORT_GFX_CGTS | 2601 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2602 RADEON_CG_SUPPORT_GFX_CP_LS | 2603 RADEON_CG_SUPPORT_MC_LS | 2604 RADEON_CG_SUPPORT_MC_MGCG | 2605 RADEON_CG_SUPPORT_SDMA_MGCG | 2606 RADEON_CG_SUPPORT_SDMA_LS | 2607 RADEON_CG_SUPPORT_BIF_LS | 2608 RADEON_CG_SUPPORT_VCE_MGCG | 2609 RADEON_CG_SUPPORT_UVD_MGCG | 2610 RADEON_CG_SUPPORT_HDP_LS | 2611 RADEON_CG_SUPPORT_HDP_MGCG; 2612 rdev->pg_flags = 0; 2613 } else { 2614 rdev->cg_flags = 2615 RADEON_CG_SUPPORT_GFX_MGCG | 2616 RADEON_CG_SUPPORT_GFX_MGLS | 2617 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2618 RADEON_CG_SUPPORT_GFX_CGLS | 2619 RADEON_CG_SUPPORT_GFX_CGTS | 2620 RADEON_CG_SUPPORT_GFX_CP_LS | 2621 RADEON_CG_SUPPORT_MC_LS | 2622 RADEON_CG_SUPPORT_MC_MGCG | 2623 RADEON_CG_SUPPORT_SDMA_MGCG | 2624 RADEON_CG_SUPPORT_SDMA_LS | 2625 RADEON_CG_SUPPORT_BIF_LS | 2626 RADEON_CG_SUPPORT_VCE_MGCG | 2627 RADEON_CG_SUPPORT_UVD_MGCG | 2628 RADEON_CG_SUPPORT_HDP_LS | 2629 RADEON_CG_SUPPORT_HDP_MGCG; 2630 rdev->pg_flags = 0; 2631 } 2632 break; 2633 case CHIP_KAVERI: 2634 case CHIP_KABINI: 2635 case CHIP_MULLINS: 2636 rdev->asic = &kv_asic; 2637 /* set num crtcs */ 2638 if (rdev->family == CHIP_KAVERI) { 2639 rdev->num_crtc = 4; 2640 rdev->cg_flags = 2641 RADEON_CG_SUPPORT_GFX_MGCG | 2642 RADEON_CG_SUPPORT_GFX_MGLS | 2643 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2644 RADEON_CG_SUPPORT_GFX_CGLS | 2645 RADEON_CG_SUPPORT_GFX_CGTS | 2646 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2647 RADEON_CG_SUPPORT_GFX_CP_LS | 2648 RADEON_CG_SUPPORT_SDMA_MGCG | 2649 RADEON_CG_SUPPORT_SDMA_LS | 2650 RADEON_CG_SUPPORT_BIF_LS | 2651 RADEON_CG_SUPPORT_VCE_MGCG | 2652 RADEON_CG_SUPPORT_UVD_MGCG | 2653 RADEON_CG_SUPPORT_HDP_LS | 2654 RADEON_CG_SUPPORT_HDP_MGCG; 2655 rdev->pg_flags = 0; 2656 /*RADEON_PG_SUPPORT_GFX_PG | 2657 RADEON_PG_SUPPORT_GFX_SMG | 2658 RADEON_PG_SUPPORT_GFX_DMG | 2659 RADEON_PG_SUPPORT_UVD | 2660 RADEON_PG_SUPPORT_VCE | 2661 RADEON_PG_SUPPORT_CP | 2662 RADEON_PG_SUPPORT_GDS | 2663 RADEON_PG_SUPPORT_RLC_SMU_HS | 2664 RADEON_PG_SUPPORT_ACP | 2665 RADEON_PG_SUPPORT_SAMU;*/ 2666 } else { 2667 rdev->num_crtc = 2; 2668 rdev->cg_flags = 2669 RADEON_CG_SUPPORT_GFX_MGCG | 2670 RADEON_CG_SUPPORT_GFX_MGLS | 2671 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2672 RADEON_CG_SUPPORT_GFX_CGLS | 2673 RADEON_CG_SUPPORT_GFX_CGTS | 2674 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2675 RADEON_CG_SUPPORT_GFX_CP_LS | 2676 RADEON_CG_SUPPORT_SDMA_MGCG | 2677 RADEON_CG_SUPPORT_SDMA_LS | 2678 RADEON_CG_SUPPORT_BIF_LS | 2679 RADEON_CG_SUPPORT_VCE_MGCG | 2680 RADEON_CG_SUPPORT_UVD_MGCG | 2681 RADEON_CG_SUPPORT_HDP_LS | 2682 RADEON_CG_SUPPORT_HDP_MGCG; 2683 rdev->pg_flags = 0; 2684 /*RADEON_PG_SUPPORT_GFX_PG | 2685 RADEON_PG_SUPPORT_GFX_SMG | 2686 RADEON_PG_SUPPORT_UVD | 2687 RADEON_PG_SUPPORT_VCE | 2688 RADEON_PG_SUPPORT_CP | 2689 RADEON_PG_SUPPORT_GDS | 2690 RADEON_PG_SUPPORT_RLC_SMU_HS | 2691 RADEON_PG_SUPPORT_SAMU;*/ 2692 } 2693 rdev->has_uvd = true; 2694 rdev->has_vce = true; 2695 break; 2696 default: 2697 /* FIXME: not supported yet */ 2698 return -EINVAL; 2699 } 2700 2701 if (rdev->flags & RADEON_IS_IGP) { 2702 rdev->asic->pm.get_memory_clock = NULL; 2703 rdev->asic->pm.set_memory_clock = NULL; 2704 } 2705 2706 if (!radeon_uvd) 2707 rdev->has_uvd = false; 2708 if (!radeon_vce) 2709 rdev->has_vce = false; 2710 2711 return 0; 2712 } 2713 2714
Indexes created Sat Oct 25 16:10:12 GMT 2025