radeon_asic.c revision 1.2.30.1
1 /* $NetBSD: radeon_asic.c,v 1.2.30.1 2018/09/06 06:56:32 pgoyette Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_asic.c,v 1.2.30.1 2018/09/06 06:56:32 pgoyette Exp $"); 33 34 #include <linux/console.h> 35 #include <drm/drmP.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/radeon_drm.h> 38 #include <linux/vgaarb.h> 39 #include "radeon_reg.h" 40 #include "radeon.h" 41 #include "radeon_asic.h" 42 #include "atom.h" 43 44 /* 45 * Registers accessors functions. 46 */ 47 /** 48 * radeon_invalid_rreg - dummy reg read function 49 * 50 * @rdev: radeon device pointer 51 * @reg: offset of register 52 * 53 * Dummy register read function. Used for register blocks 54 * that certain asics don't have (all asics). 55 * Returns the value in the register. 56 */ 57 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 58 { 59 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 60 BUG_ON(1); 61 return 0; 62 } 63 64 /** 65 * radeon_invalid_wreg - dummy reg write function 66 * 67 * @rdev: radeon device pointer 68 * @reg: offset of register 69 * @v: value to write to the register 70 * 71 * Dummy register read function. Used for register blocks 72 * that certain asics don't have (all asics). 73 */ 74 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 75 { 76 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 77 reg, v); 78 BUG_ON(1); 79 } 80 81 /** 82 * radeon_register_accessor_init - sets up the register accessor callbacks 83 * 84 * @rdev: radeon device pointer 85 * 86 * Sets up the register accessor callbacks for various register 87 * apertures. Not all asics have all apertures (all asics). 88 */ 89 static void radeon_register_accessor_init(struct radeon_device *rdev) 90 { 91 rdev->mc_rreg = &radeon_invalid_rreg; 92 rdev->mc_wreg = &radeon_invalid_wreg; 93 rdev->pll_rreg = &radeon_invalid_rreg; 94 rdev->pll_wreg = &radeon_invalid_wreg; 95 rdev->pciep_rreg = &radeon_invalid_rreg; 96 rdev->pciep_wreg = &radeon_invalid_wreg; 97 98 /* Don't change order as we are overridding accessor. */ 99 if (rdev->family < CHIP_RV515) { 100 rdev->pcie_reg_mask = 0xff; 101 } else { 102 rdev->pcie_reg_mask = 0x7ff; 103 } 104 /* FIXME: not sure here */ 105 if (rdev->family <= CHIP_R580) { 106 rdev->pll_rreg = &r100_pll_rreg; 107 rdev->pll_wreg = &r100_pll_wreg; 108 } 109 if (rdev->family >= CHIP_R420) { 110 rdev->mc_rreg = &r420_mc_rreg; 111 rdev->mc_wreg = &r420_mc_wreg; 112 } 113 if (rdev->family >= CHIP_RV515) { 114 rdev->mc_rreg = &rv515_mc_rreg; 115 rdev->mc_wreg = &rv515_mc_wreg; 116 } 117 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 118 rdev->mc_rreg = &rs400_mc_rreg; 119 rdev->mc_wreg = &rs400_mc_wreg; 120 } 121 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 122 rdev->mc_rreg = &rs690_mc_rreg; 123 rdev->mc_wreg = &rs690_mc_wreg; 124 } 125 if (rdev->family == CHIP_RS600) { 126 rdev->mc_rreg = &rs600_mc_rreg; 127 rdev->mc_wreg = &rs600_mc_wreg; 128 } 129 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 130 rdev->mc_rreg = &rs780_mc_rreg; 131 rdev->mc_wreg = &rs780_mc_wreg; 132 } 133 134 if (rdev->family >= CHIP_BONAIRE) { 135 rdev->pciep_rreg = &cik_pciep_rreg; 136 rdev->pciep_wreg = &cik_pciep_wreg; 137 } else if (rdev->family >= CHIP_R600) { 138 rdev->pciep_rreg = &r600_pciep_rreg; 139 rdev->pciep_wreg = &r600_pciep_wreg; 140 } 141 } 142 143 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, 144 u32 reg, u32 *val) 145 { 146 return -EINVAL; 147 } 148 149 /* helper to disable agp */ 150 /** 151 * radeon_agp_disable - AGP disable helper function 152 * 153 * @rdev: radeon device pointer 154 * 155 * Removes AGP flags and changes the gart callbacks on AGP 156 * cards when using the internal gart rather than AGP (all asics). 157 */ 158 void radeon_agp_disable(struct radeon_device *rdev) 159 { 160 rdev->flags &= ~RADEON_IS_AGP; 161 if (rdev->family >= CHIP_R600) { 162 DRM_INFO("Forcing AGP to PCIE mode\n"); 163 rdev->flags |= RADEON_IS_PCIE; 164 } else if (rdev->family >= CHIP_RV515 || 165 rdev->family == CHIP_RV380 || 166 rdev->family == CHIP_RV410 || 167 rdev->family == CHIP_R423) { 168 DRM_INFO("Forcing AGP to PCIE mode\n"); 169 rdev->flags |= RADEON_IS_PCIE; 170 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 171 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; 172 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 173 } else { 174 DRM_INFO("Forcing AGP to PCI mode\n"); 175 rdev->flags |= RADEON_IS_PCI; 176 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 177 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 178 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 179 } 180 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 181 } 182 183 /* 184 * ASIC 185 */ 186 187 static struct radeon_asic_ring r100_gfx_ring = { 188 .ib_execute = &r100_ring_ib_execute, 189 .emit_fence = &r100_fence_ring_emit, 190 .emit_semaphore = &r100_semaphore_ring_emit, 191 .cs_parse = &r100_cs_parse, 192 .ring_start = &r100_ring_start, 193 .ring_test = &r100_ring_test, 194 .ib_test = &r100_ib_test, 195 .is_lockup = &r100_gpu_is_lockup, 196 .get_rptr = &r100_gfx_get_rptr, 197 .get_wptr = &r100_gfx_get_wptr, 198 .set_wptr = &r100_gfx_set_wptr, 199 }; 200 201 static struct radeon_asic r100_asic = { 202 .init = &r100_init, 203 .fini = &r100_fini, 204 .suspend = &r100_suspend, 205 .resume = &r100_resume, 206 .vga_set_state = &r100_vga_set_state, 207 .asic_reset = &r100_asic_reset, 208 .mmio_hdp_flush = NULL, 209 .gui_idle = &r100_gui_idle, 210 .mc_wait_for_idle = &r100_mc_wait_for_idle, 211 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 212 .gart = { 213 .tlb_flush = &r100_pci_gart_tlb_flush, 214 .get_page_entry = &r100_pci_gart_get_page_entry, 215 .set_page = &r100_pci_gart_set_page, 216 }, 217 .ring = { 218 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 219 }, 220 .irq = { 221 .set = &r100_irq_set, 222 .process = &r100_irq_process, 223 }, 224 .display = { 225 .bandwidth_update = &r100_bandwidth_update, 226 .get_vblank_counter = &r100_get_vblank_counter, 227 .wait_for_vblank = &r100_wait_for_vblank, 228 .set_backlight_level = &radeon_legacy_set_backlight_level, 229 .get_backlight_level = &radeon_legacy_get_backlight_level, 230 }, 231 .copy = { 232 .blit = &r100_copy_blit, 233 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 234 .dma = NULL, 235 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 236 .copy = &r100_copy_blit, 237 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 238 }, 239 .surface = { 240 .set_reg = r100_set_surface_reg, 241 .clear_reg = r100_clear_surface_reg, 242 }, 243 .hpd = { 244 .init = &r100_hpd_init, 245 .fini = &r100_hpd_fini, 246 .sense = &r100_hpd_sense, 247 .set_polarity = &r100_hpd_set_polarity, 248 }, 249 .pm = { 250 .misc = &r100_pm_misc, 251 .prepare = &r100_pm_prepare, 252 .finish = &r100_pm_finish, 253 .init_profile = &r100_pm_init_profile, 254 .get_dynpm_state = &r100_pm_get_dynpm_state, 255 .get_engine_clock = &radeon_legacy_get_engine_clock, 256 .set_engine_clock = &radeon_legacy_set_engine_clock, 257 .get_memory_clock = &radeon_legacy_get_memory_clock, 258 .set_memory_clock = NULL, 259 .get_pcie_lanes = NULL, 260 .set_pcie_lanes = NULL, 261 .set_clock_gating = &radeon_legacy_set_clock_gating, 262 }, 263 .pflip = { 264 .page_flip = &r100_page_flip, 265 .page_flip_pending = &r100_page_flip_pending, 266 }, 267 }; 268 269 static struct radeon_asic r200_asic = { 270 .init = &r100_init, 271 .fini = &r100_fini, 272 .suspend = &r100_suspend, 273 .resume = &r100_resume, 274 .vga_set_state = &r100_vga_set_state, 275 .asic_reset = &r100_asic_reset, 276 .mmio_hdp_flush = NULL, 277 .gui_idle = &r100_gui_idle, 278 .mc_wait_for_idle = &r100_mc_wait_for_idle, 279 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 280 .gart = { 281 .tlb_flush = &r100_pci_gart_tlb_flush, 282 .get_page_entry = &r100_pci_gart_get_page_entry, 283 .set_page = &r100_pci_gart_set_page, 284 }, 285 .ring = { 286 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 287 }, 288 .irq = { 289 .set = &r100_irq_set, 290 .process = &r100_irq_process, 291 }, 292 .display = { 293 .bandwidth_update = &r100_bandwidth_update, 294 .get_vblank_counter = &r100_get_vblank_counter, 295 .wait_for_vblank = &r100_wait_for_vblank, 296 .set_backlight_level = &radeon_legacy_set_backlight_level, 297 .get_backlight_level = &radeon_legacy_get_backlight_level, 298 }, 299 .copy = { 300 .blit = &r100_copy_blit, 301 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 302 .dma = &r200_copy_dma, 303 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 304 .copy = &r100_copy_blit, 305 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 306 }, 307 .surface = { 308 .set_reg = r100_set_surface_reg, 309 .clear_reg = r100_clear_surface_reg, 310 }, 311 .hpd = { 312 .init = &r100_hpd_init, 313 .fini = &r100_hpd_fini, 314 .sense = &r100_hpd_sense, 315 .set_polarity = &r100_hpd_set_polarity, 316 }, 317 .pm = { 318 .misc = &r100_pm_misc, 319 .prepare = &r100_pm_prepare, 320 .finish = &r100_pm_finish, 321 .init_profile = &r100_pm_init_profile, 322 .get_dynpm_state = &r100_pm_get_dynpm_state, 323 .get_engine_clock = &radeon_legacy_get_engine_clock, 324 .set_engine_clock = &radeon_legacy_set_engine_clock, 325 .get_memory_clock = &radeon_legacy_get_memory_clock, 326 .set_memory_clock = NULL, 327 .get_pcie_lanes = NULL, 328 .set_pcie_lanes = NULL, 329 .set_clock_gating = &radeon_legacy_set_clock_gating, 330 }, 331 .pflip = { 332 .page_flip = &r100_page_flip, 333 .page_flip_pending = &r100_page_flip_pending, 334 }, 335 }; 336 337 static struct radeon_asic_ring r300_gfx_ring = { 338 .ib_execute = &r100_ring_ib_execute, 339 .emit_fence = &r300_fence_ring_emit, 340 .emit_semaphore = &r100_semaphore_ring_emit, 341 .cs_parse = &r300_cs_parse, 342 .ring_start = &r300_ring_start, 343 .ring_test = &r100_ring_test, 344 .ib_test = &r100_ib_test, 345 .is_lockup = &r100_gpu_is_lockup, 346 .get_rptr = &r100_gfx_get_rptr, 347 .get_wptr = &r100_gfx_get_wptr, 348 .set_wptr = &r100_gfx_set_wptr, 349 }; 350 351 static struct radeon_asic_ring rv515_gfx_ring = { 352 .ib_execute = &r100_ring_ib_execute, 353 .emit_fence = &r300_fence_ring_emit, 354 .emit_semaphore = &r100_semaphore_ring_emit, 355 .cs_parse = &r300_cs_parse, 356 .ring_start = &rv515_ring_start, 357 .ring_test = &r100_ring_test, 358 .ib_test = &r100_ib_test, 359 .is_lockup = &r100_gpu_is_lockup, 360 .get_rptr = &r100_gfx_get_rptr, 361 .get_wptr = &r100_gfx_get_wptr, 362 .set_wptr = &r100_gfx_set_wptr, 363 }; 364 365 static struct radeon_asic r300_asic = { 366 .init = &r300_init, 367 .fini = &r300_fini, 368 .suspend = &r300_suspend, 369 .resume = &r300_resume, 370 .vga_set_state = &r100_vga_set_state, 371 .asic_reset = &r300_asic_reset, 372 .mmio_hdp_flush = NULL, 373 .gui_idle = &r100_gui_idle, 374 .mc_wait_for_idle = &r300_mc_wait_for_idle, 375 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 376 .gart = { 377 .tlb_flush = &r100_pci_gart_tlb_flush, 378 .get_page_entry = &r100_pci_gart_get_page_entry, 379 .set_page = &r100_pci_gart_set_page, 380 }, 381 .ring = { 382 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 383 }, 384 .irq = { 385 .set = &r100_irq_set, 386 .process = &r100_irq_process, 387 }, 388 .display = { 389 .bandwidth_update = &r100_bandwidth_update, 390 .get_vblank_counter = &r100_get_vblank_counter, 391 .wait_for_vblank = &r100_wait_for_vblank, 392 .set_backlight_level = &radeon_legacy_set_backlight_level, 393 .get_backlight_level = &radeon_legacy_get_backlight_level, 394 }, 395 .copy = { 396 .blit = &r100_copy_blit, 397 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 398 .dma = &r200_copy_dma, 399 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 400 .copy = &r100_copy_blit, 401 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 402 }, 403 .surface = { 404 .set_reg = r100_set_surface_reg, 405 .clear_reg = r100_clear_surface_reg, 406 }, 407 .hpd = { 408 .init = &r100_hpd_init, 409 .fini = &r100_hpd_fini, 410 .sense = &r100_hpd_sense, 411 .set_polarity = &r100_hpd_set_polarity, 412 }, 413 .pm = { 414 .misc = &r100_pm_misc, 415 .prepare = &r100_pm_prepare, 416 .finish = &r100_pm_finish, 417 .init_profile = &r100_pm_init_profile, 418 .get_dynpm_state = &r100_pm_get_dynpm_state, 419 .get_engine_clock = &radeon_legacy_get_engine_clock, 420 .set_engine_clock = &radeon_legacy_set_engine_clock, 421 .get_memory_clock = &radeon_legacy_get_memory_clock, 422 .set_memory_clock = NULL, 423 .get_pcie_lanes = &rv370_get_pcie_lanes, 424 .set_pcie_lanes = &rv370_set_pcie_lanes, 425 .set_clock_gating = &radeon_legacy_set_clock_gating, 426 }, 427 .pflip = { 428 .page_flip = &r100_page_flip, 429 .page_flip_pending = &r100_page_flip_pending, 430 }, 431 }; 432 433 static struct radeon_asic r300_asic_pcie = { 434 .init = &r300_init, 435 .fini = &r300_fini, 436 .suspend = &r300_suspend, 437 .resume = &r300_resume, 438 .vga_set_state = &r100_vga_set_state, 439 .asic_reset = &r300_asic_reset, 440 .mmio_hdp_flush = NULL, 441 .gui_idle = &r100_gui_idle, 442 .mc_wait_for_idle = &r300_mc_wait_for_idle, 443 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 444 .gart = { 445 .tlb_flush = &rv370_pcie_gart_tlb_flush, 446 .get_page_entry = &rv370_pcie_gart_get_page_entry, 447 .set_page = &rv370_pcie_gart_set_page, 448 }, 449 .ring = { 450 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 451 }, 452 .irq = { 453 .set = &r100_irq_set, 454 .process = &r100_irq_process, 455 }, 456 .display = { 457 .bandwidth_update = &r100_bandwidth_update, 458 .get_vblank_counter = &r100_get_vblank_counter, 459 .wait_for_vblank = &r100_wait_for_vblank, 460 .set_backlight_level = &radeon_legacy_set_backlight_level, 461 .get_backlight_level = &radeon_legacy_get_backlight_level, 462 }, 463 .copy = { 464 .blit = &r100_copy_blit, 465 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 466 .dma = &r200_copy_dma, 467 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 468 .copy = &r100_copy_blit, 469 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 470 }, 471 .surface = { 472 .set_reg = r100_set_surface_reg, 473 .clear_reg = r100_clear_surface_reg, 474 }, 475 .hpd = { 476 .init = &r100_hpd_init, 477 .fini = &r100_hpd_fini, 478 .sense = &r100_hpd_sense, 479 .set_polarity = &r100_hpd_set_polarity, 480 }, 481 .pm = { 482 .misc = &r100_pm_misc, 483 .prepare = &r100_pm_prepare, 484 .finish = &r100_pm_finish, 485 .init_profile = &r100_pm_init_profile, 486 .get_dynpm_state = &r100_pm_get_dynpm_state, 487 .get_engine_clock = &radeon_legacy_get_engine_clock, 488 .set_engine_clock = &radeon_legacy_set_engine_clock, 489 .get_memory_clock = &radeon_legacy_get_memory_clock, 490 .set_memory_clock = NULL, 491 .get_pcie_lanes = &rv370_get_pcie_lanes, 492 .set_pcie_lanes = &rv370_set_pcie_lanes, 493 .set_clock_gating = &radeon_legacy_set_clock_gating, 494 }, 495 .pflip = { 496 .page_flip = &r100_page_flip, 497 .page_flip_pending = &r100_page_flip_pending, 498 }, 499 }; 500 501 static struct radeon_asic r420_asic = { 502 .init = &r420_init, 503 .fini = &r420_fini, 504 .suspend = &r420_suspend, 505 .resume = &r420_resume, 506 .vga_set_state = &r100_vga_set_state, 507 .asic_reset = &r300_asic_reset, 508 .mmio_hdp_flush = NULL, 509 .gui_idle = &r100_gui_idle, 510 .mc_wait_for_idle = &r300_mc_wait_for_idle, 511 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 512 .gart = { 513 .tlb_flush = &rv370_pcie_gart_tlb_flush, 514 .get_page_entry = &rv370_pcie_gart_get_page_entry, 515 .set_page = &rv370_pcie_gart_set_page, 516 }, 517 .ring = { 518 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 519 }, 520 .irq = { 521 .set = &r100_irq_set, 522 .process = &r100_irq_process, 523 }, 524 .display = { 525 .bandwidth_update = &r100_bandwidth_update, 526 .get_vblank_counter = &r100_get_vblank_counter, 527 .wait_for_vblank = &r100_wait_for_vblank, 528 .set_backlight_level = &atombios_set_backlight_level, 529 .get_backlight_level = &atombios_get_backlight_level, 530 }, 531 .copy = { 532 .blit = &r100_copy_blit, 533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 534 .dma = &r200_copy_dma, 535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 536 .copy = &r100_copy_blit, 537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 538 }, 539 .surface = { 540 .set_reg = r100_set_surface_reg, 541 .clear_reg = r100_clear_surface_reg, 542 }, 543 .hpd = { 544 .init = &r100_hpd_init, 545 .fini = &r100_hpd_fini, 546 .sense = &r100_hpd_sense, 547 .set_polarity = &r100_hpd_set_polarity, 548 }, 549 .pm = { 550 .misc = &r100_pm_misc, 551 .prepare = &r100_pm_prepare, 552 .finish = &r100_pm_finish, 553 .init_profile = &r420_pm_init_profile, 554 .get_dynpm_state = &r100_pm_get_dynpm_state, 555 .get_engine_clock = &radeon_atom_get_engine_clock, 556 .set_engine_clock = &radeon_atom_set_engine_clock, 557 .get_memory_clock = &radeon_atom_get_memory_clock, 558 .set_memory_clock = &radeon_atom_set_memory_clock, 559 .get_pcie_lanes = &rv370_get_pcie_lanes, 560 .set_pcie_lanes = &rv370_set_pcie_lanes, 561 .set_clock_gating = &radeon_atom_set_clock_gating, 562 }, 563 .pflip = { 564 .page_flip = &r100_page_flip, 565 .page_flip_pending = &r100_page_flip_pending, 566 }, 567 }; 568 569 static struct radeon_asic rs400_asic = { 570 .init = &rs400_init, 571 .fini = &rs400_fini, 572 .suspend = &rs400_suspend, 573 .resume = &rs400_resume, 574 .vga_set_state = &r100_vga_set_state, 575 .asic_reset = &r300_asic_reset, 576 .mmio_hdp_flush = NULL, 577 .gui_idle = &r100_gui_idle, 578 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 579 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 580 .gart = { 581 .tlb_flush = &rs400_gart_tlb_flush, 582 .get_page_entry = &rs400_gart_get_page_entry, 583 .set_page = &rs400_gart_set_page, 584 }, 585 .ring = { 586 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 587 }, 588 .irq = { 589 .set = &r100_irq_set, 590 .process = &r100_irq_process, 591 }, 592 .display = { 593 .bandwidth_update = &r100_bandwidth_update, 594 .get_vblank_counter = &r100_get_vblank_counter, 595 .wait_for_vblank = &r100_wait_for_vblank, 596 .set_backlight_level = &radeon_legacy_set_backlight_level, 597 .get_backlight_level = &radeon_legacy_get_backlight_level, 598 }, 599 .copy = { 600 .blit = &r100_copy_blit, 601 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 602 .dma = &r200_copy_dma, 603 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 604 .copy = &r100_copy_blit, 605 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 606 }, 607 .surface = { 608 .set_reg = r100_set_surface_reg, 609 .clear_reg = r100_clear_surface_reg, 610 }, 611 .hpd = { 612 .init = &r100_hpd_init, 613 .fini = &r100_hpd_fini, 614 .sense = &r100_hpd_sense, 615 .set_polarity = &r100_hpd_set_polarity, 616 }, 617 .pm = { 618 .misc = &r100_pm_misc, 619 .prepare = &r100_pm_prepare, 620 .finish = &r100_pm_finish, 621 .init_profile = &r100_pm_init_profile, 622 .get_dynpm_state = &r100_pm_get_dynpm_state, 623 .get_engine_clock = &radeon_legacy_get_engine_clock, 624 .set_engine_clock = &radeon_legacy_set_engine_clock, 625 .get_memory_clock = &radeon_legacy_get_memory_clock, 626 .set_memory_clock = NULL, 627 .get_pcie_lanes = NULL, 628 .set_pcie_lanes = NULL, 629 .set_clock_gating = &radeon_legacy_set_clock_gating, 630 }, 631 .pflip = { 632 .page_flip = &r100_page_flip, 633 .page_flip_pending = &r100_page_flip_pending, 634 }, 635 }; 636 637 static struct radeon_asic rs600_asic = { 638 .init = &rs600_init, 639 .fini = &rs600_fini, 640 .suspend = &rs600_suspend, 641 .resume = &rs600_resume, 642 .vga_set_state = &r100_vga_set_state, 643 .asic_reset = &rs600_asic_reset, 644 .mmio_hdp_flush = NULL, 645 .gui_idle = &r100_gui_idle, 646 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 647 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 648 .gart = { 649 .tlb_flush = &rs600_gart_tlb_flush, 650 .get_page_entry = &rs600_gart_get_page_entry, 651 .set_page = &rs600_gart_set_page, 652 }, 653 .ring = { 654 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 655 }, 656 .irq = { 657 .set = &rs600_irq_set, 658 .process = &rs600_irq_process, 659 }, 660 .display = { 661 .bandwidth_update = &rs600_bandwidth_update, 662 .get_vblank_counter = &rs600_get_vblank_counter, 663 .wait_for_vblank = &avivo_wait_for_vblank, 664 .set_backlight_level = &atombios_set_backlight_level, 665 .get_backlight_level = &atombios_get_backlight_level, 666 }, 667 .copy = { 668 .blit = &r100_copy_blit, 669 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 670 .dma = &r200_copy_dma, 671 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 672 .copy = &r100_copy_blit, 673 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 674 }, 675 .surface = { 676 .set_reg = r100_set_surface_reg, 677 .clear_reg = r100_clear_surface_reg, 678 }, 679 .hpd = { 680 .init = &rs600_hpd_init, 681 .fini = &rs600_hpd_fini, 682 .sense = &rs600_hpd_sense, 683 .set_polarity = &rs600_hpd_set_polarity, 684 }, 685 .pm = { 686 .misc = &rs600_pm_misc, 687 .prepare = &rs600_pm_prepare, 688 .finish = &rs600_pm_finish, 689 .init_profile = &r420_pm_init_profile, 690 .get_dynpm_state = &r100_pm_get_dynpm_state, 691 .get_engine_clock = &radeon_atom_get_engine_clock, 692 .set_engine_clock = &radeon_atom_set_engine_clock, 693 .get_memory_clock = &radeon_atom_get_memory_clock, 694 .set_memory_clock = &radeon_atom_set_memory_clock, 695 .get_pcie_lanes = NULL, 696 .set_pcie_lanes = NULL, 697 .set_clock_gating = &radeon_atom_set_clock_gating, 698 }, 699 .pflip = { 700 .page_flip = &rs600_page_flip, 701 .page_flip_pending = &rs600_page_flip_pending, 702 }, 703 }; 704 705 static struct radeon_asic rs690_asic = { 706 .init = &rs690_init, 707 .fini = &rs690_fini, 708 .suspend = &rs690_suspend, 709 .resume = &rs690_resume, 710 .vga_set_state = &r100_vga_set_state, 711 .asic_reset = &rs600_asic_reset, 712 .mmio_hdp_flush = NULL, 713 .gui_idle = &r100_gui_idle, 714 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 715 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 716 .gart = { 717 .tlb_flush = &rs400_gart_tlb_flush, 718 .get_page_entry = &rs400_gart_get_page_entry, 719 .set_page = &rs400_gart_set_page, 720 }, 721 .ring = { 722 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 723 }, 724 .irq = { 725 .set = &rs600_irq_set, 726 .process = &rs600_irq_process, 727 }, 728 .display = { 729 .get_vblank_counter = &rs600_get_vblank_counter, 730 .bandwidth_update = &rs690_bandwidth_update, 731 .wait_for_vblank = &avivo_wait_for_vblank, 732 .set_backlight_level = &atombios_set_backlight_level, 733 .get_backlight_level = &atombios_get_backlight_level, 734 }, 735 .copy = { 736 .blit = &r100_copy_blit, 737 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 738 .dma = &r200_copy_dma, 739 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 740 .copy = &r200_copy_dma, 741 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 742 }, 743 .surface = { 744 .set_reg = r100_set_surface_reg, 745 .clear_reg = r100_clear_surface_reg, 746 }, 747 .hpd = { 748 .init = &rs600_hpd_init, 749 .fini = &rs600_hpd_fini, 750 .sense = &rs600_hpd_sense, 751 .set_polarity = &rs600_hpd_set_polarity, 752 }, 753 .pm = { 754 .misc = &rs600_pm_misc, 755 .prepare = &rs600_pm_prepare, 756 .finish = &rs600_pm_finish, 757 .init_profile = &r420_pm_init_profile, 758 .get_dynpm_state = &r100_pm_get_dynpm_state, 759 .get_engine_clock = &radeon_atom_get_engine_clock, 760 .set_engine_clock = &radeon_atom_set_engine_clock, 761 .get_memory_clock = &radeon_atom_get_memory_clock, 762 .set_memory_clock = &radeon_atom_set_memory_clock, 763 .get_pcie_lanes = NULL, 764 .set_pcie_lanes = NULL, 765 .set_clock_gating = &radeon_atom_set_clock_gating, 766 }, 767 .pflip = { 768 .page_flip = &rs600_page_flip, 769 .page_flip_pending = &rs600_page_flip_pending, 770 }, 771 }; 772 773 static struct radeon_asic rv515_asic = { 774 .init = &rv515_init, 775 .fini = &rv515_fini, 776 .suspend = &rv515_suspend, 777 .resume = &rv515_resume, 778 .vga_set_state = &r100_vga_set_state, 779 .asic_reset = &rs600_asic_reset, 780 .mmio_hdp_flush = NULL, 781 .gui_idle = &r100_gui_idle, 782 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 783 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 784 .gart = { 785 .tlb_flush = &rv370_pcie_gart_tlb_flush, 786 .get_page_entry = &rv370_pcie_gart_get_page_entry, 787 .set_page = &rv370_pcie_gart_set_page, 788 }, 789 .ring = { 790 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 791 }, 792 .irq = { 793 .set = &rs600_irq_set, 794 .process = &rs600_irq_process, 795 }, 796 .display = { 797 .get_vblank_counter = &rs600_get_vblank_counter, 798 .bandwidth_update = &rv515_bandwidth_update, 799 .wait_for_vblank = &avivo_wait_for_vblank, 800 .set_backlight_level = &atombios_set_backlight_level, 801 .get_backlight_level = &atombios_get_backlight_level, 802 }, 803 .copy = { 804 .blit = &r100_copy_blit, 805 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 806 .dma = &r200_copy_dma, 807 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 808 .copy = &r100_copy_blit, 809 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 810 }, 811 .surface = { 812 .set_reg = r100_set_surface_reg, 813 .clear_reg = r100_clear_surface_reg, 814 }, 815 .hpd = { 816 .init = &rs600_hpd_init, 817 .fini = &rs600_hpd_fini, 818 .sense = &rs600_hpd_sense, 819 .set_polarity = &rs600_hpd_set_polarity, 820 }, 821 .pm = { 822 .misc = &rs600_pm_misc, 823 .prepare = &rs600_pm_prepare, 824 .finish = &rs600_pm_finish, 825 .init_profile = &r420_pm_init_profile, 826 .get_dynpm_state = &r100_pm_get_dynpm_state, 827 .get_engine_clock = &radeon_atom_get_engine_clock, 828 .set_engine_clock = &radeon_atom_set_engine_clock, 829 .get_memory_clock = &radeon_atom_get_memory_clock, 830 .set_memory_clock = &radeon_atom_set_memory_clock, 831 .get_pcie_lanes = &rv370_get_pcie_lanes, 832 .set_pcie_lanes = &rv370_set_pcie_lanes, 833 .set_clock_gating = &radeon_atom_set_clock_gating, 834 }, 835 .pflip = { 836 .page_flip = &rs600_page_flip, 837 .page_flip_pending = &rs600_page_flip_pending, 838 }, 839 }; 840 841 static struct radeon_asic r520_asic = { 842 .init = &r520_init, 843 .fini = &rv515_fini, 844 .suspend = &rv515_suspend, 845 .resume = &r520_resume, 846 .vga_set_state = &r100_vga_set_state, 847 .asic_reset = &rs600_asic_reset, 848 .mmio_hdp_flush = NULL, 849 .gui_idle = &r100_gui_idle, 850 .mc_wait_for_idle = &r520_mc_wait_for_idle, 851 .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 852 .gart = { 853 .tlb_flush = &rv370_pcie_gart_tlb_flush, 854 .get_page_entry = &rv370_pcie_gart_get_page_entry, 855 .set_page = &rv370_pcie_gart_set_page, 856 }, 857 .ring = { 858 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 859 }, 860 .irq = { 861 .set = &rs600_irq_set, 862 .process = &rs600_irq_process, 863 }, 864 .display = { 865 .bandwidth_update = &rv515_bandwidth_update, 866 .get_vblank_counter = &rs600_get_vblank_counter, 867 .wait_for_vblank = &avivo_wait_for_vblank, 868 .set_backlight_level = &atombios_set_backlight_level, 869 .get_backlight_level = &atombios_get_backlight_level, 870 }, 871 .copy = { 872 .blit = &r100_copy_blit, 873 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 874 .dma = &r200_copy_dma, 875 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 876 .copy = &r100_copy_blit, 877 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 878 }, 879 .surface = { 880 .set_reg = r100_set_surface_reg, 881 .clear_reg = r100_clear_surface_reg, 882 }, 883 .hpd = { 884 .init = &rs600_hpd_init, 885 .fini = &rs600_hpd_fini, 886 .sense = &rs600_hpd_sense, 887 .set_polarity = &rs600_hpd_set_polarity, 888 }, 889 .pm = { 890 .misc = &rs600_pm_misc, 891 .prepare = &rs600_pm_prepare, 892 .finish = &rs600_pm_finish, 893 .init_profile = &r420_pm_init_profile, 894 .get_dynpm_state = &r100_pm_get_dynpm_state, 895 .get_engine_clock = &radeon_atom_get_engine_clock, 896 .set_engine_clock = &radeon_atom_set_engine_clock, 897 .get_memory_clock = &radeon_atom_get_memory_clock, 898 .set_memory_clock = &radeon_atom_set_memory_clock, 899 .get_pcie_lanes = &rv370_get_pcie_lanes, 900 .set_pcie_lanes = &rv370_set_pcie_lanes, 901 .set_clock_gating = &radeon_atom_set_clock_gating, 902 }, 903 .pflip = { 904 .page_flip = &rs600_page_flip, 905 .page_flip_pending = &rs600_page_flip_pending, 906 }, 907 }; 908 909 static struct radeon_asic_ring r600_gfx_ring = { 910 .ib_execute = &r600_ring_ib_execute, 911 .emit_fence = &r600_fence_ring_emit, 912 .emit_semaphore = &r600_semaphore_ring_emit, 913 .cs_parse = &r600_cs_parse, 914 .ring_test = &r600_ring_test, 915 .ib_test = &r600_ib_test, 916 .is_lockup = &r600_gfx_is_lockup, 917 .get_rptr = &r600_gfx_get_rptr, 918 .get_wptr = &r600_gfx_get_wptr, 919 .set_wptr = &r600_gfx_set_wptr, 920 }; 921 922 static struct radeon_asic_ring r600_dma_ring = { 923 .ib_execute = &r600_dma_ring_ib_execute, 924 .emit_fence = &r600_dma_fence_ring_emit, 925 .emit_semaphore = &r600_dma_semaphore_ring_emit, 926 .cs_parse = &r600_dma_cs_parse, 927 .ring_test = &r600_dma_ring_test, 928 .ib_test = &r600_dma_ib_test, 929 .is_lockup = &r600_dma_is_lockup, 930 .get_rptr = &r600_dma_get_rptr, 931 .get_wptr = &r600_dma_get_wptr, 932 .set_wptr = &r600_dma_set_wptr, 933 }; 934 935 static struct radeon_asic r600_asic = { 936 .init = &r600_init, 937 .fini = &r600_fini, 938 .suspend = &r600_suspend, 939 .resume = &r600_resume, 940 .vga_set_state = &r600_vga_set_state, 941 .asic_reset = &r600_asic_reset, 942 .mmio_hdp_flush = r600_mmio_hdp_flush, 943 .gui_idle = &r600_gui_idle, 944 .mc_wait_for_idle = &r600_mc_wait_for_idle, 945 .get_xclk = &r600_get_xclk, 946 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 947 .get_allowed_info_register = r600_get_allowed_info_register, 948 .gart = { 949 .tlb_flush = &r600_pcie_gart_tlb_flush, 950 .get_page_entry = &rs600_gart_get_page_entry, 951 .set_page = &rs600_gart_set_page, 952 }, 953 .ring = { 954 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 955 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 956 }, 957 .irq = { 958 .set = &r600_irq_set, 959 .process = &r600_irq_process, 960 }, 961 .display = { 962 .bandwidth_update = &rv515_bandwidth_update, 963 .get_vblank_counter = &rs600_get_vblank_counter, 964 .wait_for_vblank = &avivo_wait_for_vblank, 965 .set_backlight_level = &atombios_set_backlight_level, 966 .get_backlight_level = &atombios_get_backlight_level, 967 }, 968 .copy = { 969 .blit = &r600_copy_cpdma, 970 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 971 .dma = &r600_copy_dma, 972 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 973 .copy = &r600_copy_cpdma, 974 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 975 }, 976 .surface = { 977 .set_reg = r600_set_surface_reg, 978 .clear_reg = r600_clear_surface_reg, 979 }, 980 .hpd = { 981 .init = &r600_hpd_init, 982 .fini = &r600_hpd_fini, 983 .sense = &r600_hpd_sense, 984 .set_polarity = &r600_hpd_set_polarity, 985 }, 986 .pm = { 987 .misc = &r600_pm_misc, 988 .prepare = &rs600_pm_prepare, 989 .finish = &rs600_pm_finish, 990 .init_profile = &r600_pm_init_profile, 991 .get_dynpm_state = &r600_pm_get_dynpm_state, 992 .get_engine_clock = &radeon_atom_get_engine_clock, 993 .set_engine_clock = &radeon_atom_set_engine_clock, 994 .get_memory_clock = &radeon_atom_get_memory_clock, 995 .set_memory_clock = &radeon_atom_set_memory_clock, 996 .get_pcie_lanes = &r600_get_pcie_lanes, 997 .set_pcie_lanes = &r600_set_pcie_lanes, 998 .set_clock_gating = NULL, 999 .get_temperature = &rv6xx_get_temp, 1000 }, 1001 .pflip = { 1002 .page_flip = &rs600_page_flip, 1003 .page_flip_pending = &rs600_page_flip_pending, 1004 }, 1005 }; 1006 1007 static struct radeon_asic_ring rv6xx_uvd_ring = { 1008 .ib_execute = &uvd_v1_0_ib_execute, 1009 .emit_fence = &uvd_v1_0_fence_emit, 1010 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1011 .cs_parse = &radeon_uvd_cs_parse, 1012 .ring_test = &uvd_v1_0_ring_test, 1013 .ib_test = &uvd_v1_0_ib_test, 1014 .is_lockup = &radeon_ring_test_lockup, 1015 .get_rptr = &uvd_v1_0_get_rptr, 1016 .get_wptr = &uvd_v1_0_get_wptr, 1017 .set_wptr = &uvd_v1_0_set_wptr, 1018 }; 1019 1020 static struct radeon_asic rv6xx_asic = { 1021 .init = &r600_init, 1022 .fini = &r600_fini, 1023 .suspend = &r600_suspend, 1024 .resume = &r600_resume, 1025 .vga_set_state = &r600_vga_set_state, 1026 .asic_reset = &r600_asic_reset, 1027 .mmio_hdp_flush = r600_mmio_hdp_flush, 1028 .gui_idle = &r600_gui_idle, 1029 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1030 .get_xclk = &r600_get_xclk, 1031 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1032 .get_allowed_info_register = r600_get_allowed_info_register, 1033 .gart = { 1034 .tlb_flush = &r600_pcie_gart_tlb_flush, 1035 .get_page_entry = &rs600_gart_get_page_entry, 1036 .set_page = &rs600_gart_set_page, 1037 }, 1038 .ring = { 1039 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1040 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1041 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1042 }, 1043 .irq = { 1044 .set = &r600_irq_set, 1045 .process = &r600_irq_process, 1046 }, 1047 .display = { 1048 .bandwidth_update = &rv515_bandwidth_update, 1049 .get_vblank_counter = &rs600_get_vblank_counter, 1050 .wait_for_vblank = &avivo_wait_for_vblank, 1051 .set_backlight_level = &atombios_set_backlight_level, 1052 .get_backlight_level = &atombios_get_backlight_level, 1053 }, 1054 .copy = { 1055 .blit = &r600_copy_cpdma, 1056 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1057 .dma = &r600_copy_dma, 1058 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1059 .copy = &r600_copy_cpdma, 1060 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1061 }, 1062 .surface = { 1063 .set_reg = r600_set_surface_reg, 1064 .clear_reg = r600_clear_surface_reg, 1065 }, 1066 .hpd = { 1067 .init = &r600_hpd_init, 1068 .fini = &r600_hpd_fini, 1069 .sense = &r600_hpd_sense, 1070 .set_polarity = &r600_hpd_set_polarity, 1071 }, 1072 .pm = { 1073 .misc = &r600_pm_misc, 1074 .prepare = &rs600_pm_prepare, 1075 .finish = &rs600_pm_finish, 1076 .init_profile = &r600_pm_init_profile, 1077 .get_dynpm_state = &r600_pm_get_dynpm_state, 1078 .get_engine_clock = &radeon_atom_get_engine_clock, 1079 .set_engine_clock = &radeon_atom_set_engine_clock, 1080 .get_memory_clock = &radeon_atom_get_memory_clock, 1081 .set_memory_clock = &radeon_atom_set_memory_clock, 1082 .get_pcie_lanes = &r600_get_pcie_lanes, 1083 .set_pcie_lanes = &r600_set_pcie_lanes, 1084 .set_clock_gating = NULL, 1085 .get_temperature = &rv6xx_get_temp, 1086 .set_uvd_clocks = &r600_set_uvd_clocks, 1087 }, 1088 .dpm = { 1089 .init = &rv6xx_dpm_init, 1090 .setup_asic = &rv6xx_setup_asic, 1091 .enable = &rv6xx_dpm_enable, 1092 .late_enable = &r600_dpm_late_enable, 1093 .disable = &rv6xx_dpm_disable, 1094 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1095 .set_power_state = &rv6xx_dpm_set_power_state, 1096 .post_set_power_state = &r600_dpm_post_set_power_state, 1097 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1098 .fini = &rv6xx_dpm_fini, 1099 .get_sclk = &rv6xx_dpm_get_sclk, 1100 .get_mclk = &rv6xx_dpm_get_mclk, 1101 .print_power_state = &rv6xx_dpm_print_power_state, 1102 #ifdef CONFIG_DEBUG_FS 1103 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1104 #endif 1105 .force_performance_level = &rv6xx_dpm_force_performance_level, 1106 .get_current_sclk = &rv6xx_dpm_get_current_sclk, 1107 .get_current_mclk = &rv6xx_dpm_get_current_mclk, 1108 }, 1109 .pflip = { 1110 .page_flip = &rs600_page_flip, 1111 .page_flip_pending = &rs600_page_flip_pending, 1112 }, 1113 }; 1114 1115 static struct radeon_asic rs780_asic = { 1116 .init = &r600_init, 1117 .fini = &r600_fini, 1118 .suspend = &r600_suspend, 1119 .resume = &r600_resume, 1120 .vga_set_state = &r600_vga_set_state, 1121 .asic_reset = &r600_asic_reset, 1122 .mmio_hdp_flush = r600_mmio_hdp_flush, 1123 .gui_idle = &r600_gui_idle, 1124 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1125 .get_xclk = &r600_get_xclk, 1126 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1127 .get_allowed_info_register = r600_get_allowed_info_register, 1128 .gart = { 1129 .tlb_flush = &r600_pcie_gart_tlb_flush, 1130 .get_page_entry = &rs600_gart_get_page_entry, 1131 .set_page = &rs600_gart_set_page, 1132 }, 1133 .ring = { 1134 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1135 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1136 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1137 }, 1138 .irq = { 1139 .set = &r600_irq_set, 1140 .process = &r600_irq_process, 1141 }, 1142 .display = { 1143 .bandwidth_update = &rs690_bandwidth_update, 1144 .get_vblank_counter = &rs600_get_vblank_counter, 1145 .wait_for_vblank = &avivo_wait_for_vblank, 1146 .set_backlight_level = &atombios_set_backlight_level, 1147 .get_backlight_level = &atombios_get_backlight_level, 1148 }, 1149 .copy = { 1150 .blit = &r600_copy_cpdma, 1151 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1152 .dma = &r600_copy_dma, 1153 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1154 .copy = &r600_copy_cpdma, 1155 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1156 }, 1157 .surface = { 1158 .set_reg = r600_set_surface_reg, 1159 .clear_reg = r600_clear_surface_reg, 1160 }, 1161 .hpd = { 1162 .init = &r600_hpd_init, 1163 .fini = &r600_hpd_fini, 1164 .sense = &r600_hpd_sense, 1165 .set_polarity = &r600_hpd_set_polarity, 1166 }, 1167 .pm = { 1168 .misc = &r600_pm_misc, 1169 .prepare = &rs600_pm_prepare, 1170 .finish = &rs600_pm_finish, 1171 .init_profile = &rs780_pm_init_profile, 1172 .get_dynpm_state = &r600_pm_get_dynpm_state, 1173 .get_engine_clock = &radeon_atom_get_engine_clock, 1174 .set_engine_clock = &radeon_atom_set_engine_clock, 1175 .get_memory_clock = NULL, 1176 .set_memory_clock = NULL, 1177 .get_pcie_lanes = NULL, 1178 .set_pcie_lanes = NULL, 1179 .set_clock_gating = NULL, 1180 .get_temperature = &rv6xx_get_temp, 1181 .set_uvd_clocks = &r600_set_uvd_clocks, 1182 }, 1183 .dpm = { 1184 .init = &rs780_dpm_init, 1185 .setup_asic = &rs780_dpm_setup_asic, 1186 .enable = &rs780_dpm_enable, 1187 .late_enable = &r600_dpm_late_enable, 1188 .disable = &rs780_dpm_disable, 1189 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1190 .set_power_state = &rs780_dpm_set_power_state, 1191 .post_set_power_state = &r600_dpm_post_set_power_state, 1192 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1193 .fini = &rs780_dpm_fini, 1194 .get_sclk = &rs780_dpm_get_sclk, 1195 .get_mclk = &rs780_dpm_get_mclk, 1196 .print_power_state = &rs780_dpm_print_power_state, 1197 #ifdef CONFIG_DEBUG_FS 1198 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1199 #endif 1200 .force_performance_level = &rs780_dpm_force_performance_level, 1201 .get_current_sclk = &rs780_dpm_get_current_sclk, 1202 .get_current_mclk = &rs780_dpm_get_current_mclk, 1203 }, 1204 .pflip = { 1205 .page_flip = &rs600_page_flip, 1206 .page_flip_pending = &rs600_page_flip_pending, 1207 }, 1208 }; 1209 1210 static struct radeon_asic_ring rv770_uvd_ring = { 1211 .ib_execute = &uvd_v1_0_ib_execute, 1212 .emit_fence = &uvd_v2_2_fence_emit, 1213 .emit_semaphore = &uvd_v2_2_semaphore_emit, 1214 .cs_parse = &radeon_uvd_cs_parse, 1215 .ring_test = &uvd_v1_0_ring_test, 1216 .ib_test = &uvd_v1_0_ib_test, 1217 .is_lockup = &radeon_ring_test_lockup, 1218 .get_rptr = &uvd_v1_0_get_rptr, 1219 .get_wptr = &uvd_v1_0_get_wptr, 1220 .set_wptr = &uvd_v1_0_set_wptr, 1221 }; 1222 1223 static struct radeon_asic rv770_asic = { 1224 .init = &rv770_init, 1225 .fini = &rv770_fini, 1226 .suspend = &rv770_suspend, 1227 .resume = &rv770_resume, 1228 .asic_reset = &r600_asic_reset, 1229 .vga_set_state = &r600_vga_set_state, 1230 .mmio_hdp_flush = r600_mmio_hdp_flush, 1231 .gui_idle = &r600_gui_idle, 1232 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1233 .get_xclk = &rv770_get_xclk, 1234 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1235 .get_allowed_info_register = r600_get_allowed_info_register, 1236 .gart = { 1237 .tlb_flush = &r600_pcie_gart_tlb_flush, 1238 .get_page_entry = &rs600_gart_get_page_entry, 1239 .set_page = &rs600_gart_set_page, 1240 }, 1241 .ring = { 1242 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1243 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1244 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1245 }, 1246 .irq = { 1247 .set = &r600_irq_set, 1248 .process = &r600_irq_process, 1249 }, 1250 .display = { 1251 .bandwidth_update = &rv515_bandwidth_update, 1252 .get_vblank_counter = &rs600_get_vblank_counter, 1253 .wait_for_vblank = &avivo_wait_for_vblank, 1254 .set_backlight_level = &atombios_set_backlight_level, 1255 .get_backlight_level = &atombios_get_backlight_level, 1256 }, 1257 .copy = { 1258 .blit = &r600_copy_cpdma, 1259 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1260 .dma = &rv770_copy_dma, 1261 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1262 .copy = &rv770_copy_dma, 1263 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1264 }, 1265 .surface = { 1266 .set_reg = r600_set_surface_reg, 1267 .clear_reg = r600_clear_surface_reg, 1268 }, 1269 .hpd = { 1270 .init = &r600_hpd_init, 1271 .fini = &r600_hpd_fini, 1272 .sense = &r600_hpd_sense, 1273 .set_polarity = &r600_hpd_set_polarity, 1274 }, 1275 .pm = { 1276 .misc = &rv770_pm_misc, 1277 .prepare = &rs600_pm_prepare, 1278 .finish = &rs600_pm_finish, 1279 .init_profile = &r600_pm_init_profile, 1280 .get_dynpm_state = &r600_pm_get_dynpm_state, 1281 .get_engine_clock = &radeon_atom_get_engine_clock, 1282 .set_engine_clock = &radeon_atom_set_engine_clock, 1283 .get_memory_clock = &radeon_atom_get_memory_clock, 1284 .set_memory_clock = &radeon_atom_set_memory_clock, 1285 .get_pcie_lanes = &r600_get_pcie_lanes, 1286 .set_pcie_lanes = &r600_set_pcie_lanes, 1287 .set_clock_gating = &radeon_atom_set_clock_gating, 1288 .set_uvd_clocks = &rv770_set_uvd_clocks, 1289 .get_temperature = &rv770_get_temp, 1290 }, 1291 .dpm = { 1292 .init = &rv770_dpm_init, 1293 .setup_asic = &rv770_dpm_setup_asic, 1294 .enable = &rv770_dpm_enable, 1295 .late_enable = &rv770_dpm_late_enable, 1296 .disable = &rv770_dpm_disable, 1297 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1298 .set_power_state = &rv770_dpm_set_power_state, 1299 .post_set_power_state = &r600_dpm_post_set_power_state, 1300 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1301 .fini = &rv770_dpm_fini, 1302 .get_sclk = &rv770_dpm_get_sclk, 1303 .get_mclk = &rv770_dpm_get_mclk, 1304 .print_power_state = &rv770_dpm_print_power_state, 1305 #ifdef CONFIG_DEBUG_FS 1306 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1307 #endif 1308 .force_performance_level = &rv770_dpm_force_performance_level, 1309 .vblank_too_short = &rv770_dpm_vblank_too_short, 1310 .get_current_sclk = &rv770_dpm_get_current_sclk, 1311 .get_current_mclk = &rv770_dpm_get_current_mclk, 1312 }, 1313 .pflip = { 1314 .page_flip = &rv770_page_flip, 1315 .page_flip_pending = &rv770_page_flip_pending, 1316 }, 1317 }; 1318 1319 static struct radeon_asic_ring evergreen_gfx_ring = { 1320 .ib_execute = &evergreen_ring_ib_execute, 1321 .emit_fence = &r600_fence_ring_emit, 1322 .emit_semaphore = &r600_semaphore_ring_emit, 1323 .cs_parse = &evergreen_cs_parse, 1324 .ring_test = &r600_ring_test, 1325 .ib_test = &r600_ib_test, 1326 .is_lockup = &evergreen_gfx_is_lockup, 1327 .get_rptr = &r600_gfx_get_rptr, 1328 .get_wptr = &r600_gfx_get_wptr, 1329 .set_wptr = &r600_gfx_set_wptr, 1330 }; 1331 1332 static struct radeon_asic_ring evergreen_dma_ring = { 1333 .ib_execute = &evergreen_dma_ring_ib_execute, 1334 .emit_fence = &evergreen_dma_fence_ring_emit, 1335 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1336 .cs_parse = &evergreen_dma_cs_parse, 1337 .ring_test = &r600_dma_ring_test, 1338 .ib_test = &r600_dma_ib_test, 1339 .is_lockup = &evergreen_dma_is_lockup, 1340 .get_rptr = &r600_dma_get_rptr, 1341 .get_wptr = &r600_dma_get_wptr, 1342 .set_wptr = &r600_dma_set_wptr, 1343 }; 1344 1345 static struct radeon_asic evergreen_asic = { 1346 .init = &evergreen_init, 1347 .fini = &evergreen_fini, 1348 .suspend = &evergreen_suspend, 1349 .resume = &evergreen_resume, 1350 .asic_reset = &evergreen_asic_reset, 1351 .vga_set_state = &r600_vga_set_state, 1352 .mmio_hdp_flush = r600_mmio_hdp_flush, 1353 .gui_idle = &r600_gui_idle, 1354 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1355 .get_xclk = &rv770_get_xclk, 1356 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1357 .get_allowed_info_register = evergreen_get_allowed_info_register, 1358 .gart = { 1359 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1360 .get_page_entry = &rs600_gart_get_page_entry, 1361 .set_page = &rs600_gart_set_page, 1362 }, 1363 .ring = { 1364 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1365 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1366 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1367 }, 1368 .irq = { 1369 .set = &evergreen_irq_set, 1370 .process = &evergreen_irq_process, 1371 }, 1372 .display = { 1373 .bandwidth_update = &evergreen_bandwidth_update, 1374 .get_vblank_counter = &evergreen_get_vblank_counter, 1375 .wait_for_vblank = &dce4_wait_for_vblank, 1376 .set_backlight_level = &atombios_set_backlight_level, 1377 .get_backlight_level = &atombios_get_backlight_level, 1378 }, 1379 .copy = { 1380 .blit = &r600_copy_cpdma, 1381 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1382 .dma = &evergreen_copy_dma, 1383 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1384 .copy = &evergreen_copy_dma, 1385 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1386 }, 1387 .surface = { 1388 .set_reg = r600_set_surface_reg, 1389 .clear_reg = r600_clear_surface_reg, 1390 }, 1391 .hpd = { 1392 .init = &evergreen_hpd_init, 1393 .fini = &evergreen_hpd_fini, 1394 .sense = &evergreen_hpd_sense, 1395 .set_polarity = &evergreen_hpd_set_polarity, 1396 }, 1397 .pm = { 1398 .misc = &evergreen_pm_misc, 1399 .prepare = &evergreen_pm_prepare, 1400 .finish = &evergreen_pm_finish, 1401 .init_profile = &r600_pm_init_profile, 1402 .get_dynpm_state = &r600_pm_get_dynpm_state, 1403 .get_engine_clock = &radeon_atom_get_engine_clock, 1404 .set_engine_clock = &radeon_atom_set_engine_clock, 1405 .get_memory_clock = &radeon_atom_get_memory_clock, 1406 .set_memory_clock = &radeon_atom_set_memory_clock, 1407 .get_pcie_lanes = &r600_get_pcie_lanes, 1408 .set_pcie_lanes = &r600_set_pcie_lanes, 1409 .set_clock_gating = NULL, 1410 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1411 .get_temperature = &evergreen_get_temp, 1412 }, 1413 .dpm = { 1414 .init = &cypress_dpm_init, 1415 .setup_asic = &cypress_dpm_setup_asic, 1416 .enable = &cypress_dpm_enable, 1417 .late_enable = &rv770_dpm_late_enable, 1418 .disable = &cypress_dpm_disable, 1419 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1420 .set_power_state = &cypress_dpm_set_power_state, 1421 .post_set_power_state = &r600_dpm_post_set_power_state, 1422 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1423 .fini = &cypress_dpm_fini, 1424 .get_sclk = &rv770_dpm_get_sclk, 1425 .get_mclk = &rv770_dpm_get_mclk, 1426 .print_power_state = &rv770_dpm_print_power_state, 1427 #ifdef CONFIG_DEBUG_FS 1428 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1429 #endif 1430 .force_performance_level = &rv770_dpm_force_performance_level, 1431 .vblank_too_short = &cypress_dpm_vblank_too_short, 1432 .get_current_sclk = &rv770_dpm_get_current_sclk, 1433 .get_current_mclk = &rv770_dpm_get_current_mclk, 1434 }, 1435 .pflip = { 1436 .page_flip = &evergreen_page_flip, 1437 .page_flip_pending = &evergreen_page_flip_pending, 1438 }, 1439 }; 1440 1441 static struct radeon_asic sumo_asic = { 1442 .init = &evergreen_init, 1443 .fini = &evergreen_fini, 1444 .suspend = &evergreen_suspend, 1445 .resume = &evergreen_resume, 1446 .asic_reset = &evergreen_asic_reset, 1447 .vga_set_state = &r600_vga_set_state, 1448 .mmio_hdp_flush = r600_mmio_hdp_flush, 1449 .gui_idle = &r600_gui_idle, 1450 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1451 .get_xclk = &r600_get_xclk, 1452 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1453 .get_allowed_info_register = evergreen_get_allowed_info_register, 1454 .gart = { 1455 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1456 .get_page_entry = &rs600_gart_get_page_entry, 1457 .set_page = &rs600_gart_set_page, 1458 }, 1459 .ring = { 1460 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1461 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1462 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1463 }, 1464 .irq = { 1465 .set = &evergreen_irq_set, 1466 .process = &evergreen_irq_process, 1467 }, 1468 .display = { 1469 .bandwidth_update = &evergreen_bandwidth_update, 1470 .get_vblank_counter = &evergreen_get_vblank_counter, 1471 .wait_for_vblank = &dce4_wait_for_vblank, 1472 .set_backlight_level = &atombios_set_backlight_level, 1473 .get_backlight_level = &atombios_get_backlight_level, 1474 }, 1475 .copy = { 1476 .blit = &r600_copy_cpdma, 1477 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1478 .dma = &evergreen_copy_dma, 1479 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1480 .copy = &evergreen_copy_dma, 1481 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1482 }, 1483 .surface = { 1484 .set_reg = r600_set_surface_reg, 1485 .clear_reg = r600_clear_surface_reg, 1486 }, 1487 .hpd = { 1488 .init = &evergreen_hpd_init, 1489 .fini = &evergreen_hpd_fini, 1490 .sense = &evergreen_hpd_sense, 1491 .set_polarity = &evergreen_hpd_set_polarity, 1492 }, 1493 .pm = { 1494 .misc = &evergreen_pm_misc, 1495 .prepare = &evergreen_pm_prepare, 1496 .finish = &evergreen_pm_finish, 1497 .init_profile = &sumo_pm_init_profile, 1498 .get_dynpm_state = &r600_pm_get_dynpm_state, 1499 .get_engine_clock = &radeon_atom_get_engine_clock, 1500 .set_engine_clock = &radeon_atom_set_engine_clock, 1501 .get_memory_clock = NULL, 1502 .set_memory_clock = NULL, 1503 .get_pcie_lanes = NULL, 1504 .set_pcie_lanes = NULL, 1505 .set_clock_gating = NULL, 1506 .set_uvd_clocks = &sumo_set_uvd_clocks, 1507 .get_temperature = &sumo_get_temp, 1508 }, 1509 .dpm = { 1510 .init = &sumo_dpm_init, 1511 .setup_asic = &sumo_dpm_setup_asic, 1512 .enable = &sumo_dpm_enable, 1513 .late_enable = &sumo_dpm_late_enable, 1514 .disable = &sumo_dpm_disable, 1515 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1516 .set_power_state = &sumo_dpm_set_power_state, 1517 .post_set_power_state = &sumo_dpm_post_set_power_state, 1518 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1519 .fini = &sumo_dpm_fini, 1520 .get_sclk = &sumo_dpm_get_sclk, 1521 .get_mclk = &sumo_dpm_get_mclk, 1522 .print_power_state = &sumo_dpm_print_power_state, 1523 #ifdef CONFIG_DEBUG_FS 1524 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1525 #endif 1526 .force_performance_level = &sumo_dpm_force_performance_level, 1527 .get_current_sclk = &sumo_dpm_get_current_sclk, 1528 .get_current_mclk = &sumo_dpm_get_current_mclk, 1529 }, 1530 .pflip = { 1531 .page_flip = &evergreen_page_flip, 1532 .page_flip_pending = &evergreen_page_flip_pending, 1533 }, 1534 }; 1535 1536 static struct radeon_asic btc_asic = { 1537 .init = &evergreen_init, 1538 .fini = &evergreen_fini, 1539 .suspend = &evergreen_suspend, 1540 .resume = &evergreen_resume, 1541 .asic_reset = &evergreen_asic_reset, 1542 .vga_set_state = &r600_vga_set_state, 1543 .mmio_hdp_flush = r600_mmio_hdp_flush, 1544 .gui_idle = &r600_gui_idle, 1545 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1546 .get_xclk = &rv770_get_xclk, 1547 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1548 .get_allowed_info_register = evergreen_get_allowed_info_register, 1549 .gart = { 1550 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1551 .get_page_entry = &rs600_gart_get_page_entry, 1552 .set_page = &rs600_gart_set_page, 1553 }, 1554 .ring = { 1555 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1556 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1557 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1558 }, 1559 .irq = { 1560 .set = &evergreen_irq_set, 1561 .process = &evergreen_irq_process, 1562 }, 1563 .display = { 1564 .bandwidth_update = &evergreen_bandwidth_update, 1565 .get_vblank_counter = &evergreen_get_vblank_counter, 1566 .wait_for_vblank = &dce4_wait_for_vblank, 1567 .set_backlight_level = &atombios_set_backlight_level, 1568 .get_backlight_level = &atombios_get_backlight_level, 1569 }, 1570 .copy = { 1571 .blit = &r600_copy_cpdma, 1572 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1573 .dma = &evergreen_copy_dma, 1574 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1575 .copy = &evergreen_copy_dma, 1576 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1577 }, 1578 .surface = { 1579 .set_reg = r600_set_surface_reg, 1580 .clear_reg = r600_clear_surface_reg, 1581 }, 1582 .hpd = { 1583 .init = &evergreen_hpd_init, 1584 .fini = &evergreen_hpd_fini, 1585 .sense = &evergreen_hpd_sense, 1586 .set_polarity = &evergreen_hpd_set_polarity, 1587 }, 1588 .pm = { 1589 .misc = &evergreen_pm_misc, 1590 .prepare = &evergreen_pm_prepare, 1591 .finish = &evergreen_pm_finish, 1592 .init_profile = &btc_pm_init_profile, 1593 .get_dynpm_state = &r600_pm_get_dynpm_state, 1594 .get_engine_clock = &radeon_atom_get_engine_clock, 1595 .set_engine_clock = &radeon_atom_set_engine_clock, 1596 .get_memory_clock = &radeon_atom_get_memory_clock, 1597 .set_memory_clock = &radeon_atom_set_memory_clock, 1598 .get_pcie_lanes = &r600_get_pcie_lanes, 1599 .set_pcie_lanes = &r600_set_pcie_lanes, 1600 .set_clock_gating = NULL, 1601 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1602 .get_temperature = &evergreen_get_temp, 1603 }, 1604 .dpm = { 1605 .init = &btc_dpm_init, 1606 .setup_asic = &btc_dpm_setup_asic, 1607 .enable = &btc_dpm_enable, 1608 .late_enable = &rv770_dpm_late_enable, 1609 .disable = &btc_dpm_disable, 1610 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1611 .set_power_state = &btc_dpm_set_power_state, 1612 .post_set_power_state = &btc_dpm_post_set_power_state, 1613 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1614 .fini = &btc_dpm_fini, 1615 .get_sclk = &btc_dpm_get_sclk, 1616 .get_mclk = &btc_dpm_get_mclk, 1617 .print_power_state = &rv770_dpm_print_power_state, 1618 #ifdef CONFIG_DEBUG_FS 1619 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1620 #endif 1621 .force_performance_level = &rv770_dpm_force_performance_level, 1622 .vblank_too_short = &btc_dpm_vblank_too_short, 1623 .get_current_sclk = &btc_dpm_get_current_sclk, 1624 .get_current_mclk = &btc_dpm_get_current_mclk, 1625 }, 1626 .pflip = { 1627 .page_flip = &evergreen_page_flip, 1628 .page_flip_pending = &evergreen_page_flip_pending, 1629 }, 1630 }; 1631 1632 static struct radeon_asic_ring cayman_gfx_ring = { 1633 .ib_execute = &cayman_ring_ib_execute, 1634 .ib_parse = &evergreen_ib_parse, 1635 .emit_fence = &cayman_fence_ring_emit, 1636 .emit_semaphore = &r600_semaphore_ring_emit, 1637 .cs_parse = &evergreen_cs_parse, 1638 .ring_test = &r600_ring_test, 1639 .ib_test = &r600_ib_test, 1640 .is_lockup = &cayman_gfx_is_lockup, 1641 .vm_flush = &cayman_vm_flush, 1642 .get_rptr = &cayman_gfx_get_rptr, 1643 .get_wptr = &cayman_gfx_get_wptr, 1644 .set_wptr = &cayman_gfx_set_wptr, 1645 }; 1646 1647 static struct radeon_asic_ring cayman_dma_ring = { 1648 .ib_execute = &cayman_dma_ring_ib_execute, 1649 .ib_parse = &evergreen_dma_ib_parse, 1650 .emit_fence = &evergreen_dma_fence_ring_emit, 1651 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1652 .cs_parse = &evergreen_dma_cs_parse, 1653 .ring_test = &r600_dma_ring_test, 1654 .ib_test = &r600_dma_ib_test, 1655 .is_lockup = &cayman_dma_is_lockup, 1656 .vm_flush = &cayman_dma_vm_flush, 1657 .get_rptr = &cayman_dma_get_rptr, 1658 .get_wptr = &cayman_dma_get_wptr, 1659 .set_wptr = &cayman_dma_set_wptr 1660 }; 1661 1662 static struct radeon_asic_ring cayman_uvd_ring = { 1663 .ib_execute = &uvd_v1_0_ib_execute, 1664 .emit_fence = &uvd_v2_2_fence_emit, 1665 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1666 .cs_parse = &radeon_uvd_cs_parse, 1667 .ring_test = &uvd_v1_0_ring_test, 1668 .ib_test = &uvd_v1_0_ib_test, 1669 .is_lockup = &radeon_ring_test_lockup, 1670 .get_rptr = &uvd_v1_0_get_rptr, 1671 .get_wptr = &uvd_v1_0_get_wptr, 1672 .set_wptr = &uvd_v1_0_set_wptr, 1673 }; 1674 1675 static struct radeon_asic cayman_asic = { 1676 .init = &cayman_init, 1677 .fini = &cayman_fini, 1678 .suspend = &cayman_suspend, 1679 .resume = &cayman_resume, 1680 .asic_reset = &cayman_asic_reset, 1681 .vga_set_state = &r600_vga_set_state, 1682 .mmio_hdp_flush = r600_mmio_hdp_flush, 1683 .gui_idle = &r600_gui_idle, 1684 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1685 .get_xclk = &rv770_get_xclk, 1686 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1687 .get_allowed_info_register = cayman_get_allowed_info_register, 1688 .gart = { 1689 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1690 .get_page_entry = &rs600_gart_get_page_entry, 1691 .set_page = &rs600_gart_set_page, 1692 }, 1693 .vm = { 1694 .init = &cayman_vm_init, 1695 .fini = &cayman_vm_fini, 1696 .copy_pages = &cayman_dma_vm_copy_pages, 1697 .write_pages = &cayman_dma_vm_write_pages, 1698 .set_pages = &cayman_dma_vm_set_pages, 1699 .pad_ib = &cayman_dma_vm_pad_ib, 1700 }, 1701 .ring = { 1702 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1703 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1704 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1705 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1706 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1707 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1708 }, 1709 .irq = { 1710 .set = &evergreen_irq_set, 1711 .process = &evergreen_irq_process, 1712 }, 1713 .display = { 1714 .bandwidth_update = &evergreen_bandwidth_update, 1715 .get_vblank_counter = &evergreen_get_vblank_counter, 1716 .wait_for_vblank = &dce4_wait_for_vblank, 1717 .set_backlight_level = &atombios_set_backlight_level, 1718 .get_backlight_level = &atombios_get_backlight_level, 1719 }, 1720 .copy = { 1721 .blit = &r600_copy_cpdma, 1722 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1723 .dma = &evergreen_copy_dma, 1724 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1725 .copy = &evergreen_copy_dma, 1726 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1727 }, 1728 .surface = { 1729 .set_reg = r600_set_surface_reg, 1730 .clear_reg = r600_clear_surface_reg, 1731 }, 1732 .hpd = { 1733 .init = &evergreen_hpd_init, 1734 .fini = &evergreen_hpd_fini, 1735 .sense = &evergreen_hpd_sense, 1736 .set_polarity = &evergreen_hpd_set_polarity, 1737 }, 1738 .pm = { 1739 .misc = &evergreen_pm_misc, 1740 .prepare = &evergreen_pm_prepare, 1741 .finish = &evergreen_pm_finish, 1742 .init_profile = &btc_pm_init_profile, 1743 .get_dynpm_state = &r600_pm_get_dynpm_state, 1744 .get_engine_clock = &radeon_atom_get_engine_clock, 1745 .set_engine_clock = &radeon_atom_set_engine_clock, 1746 .get_memory_clock = &radeon_atom_get_memory_clock, 1747 .set_memory_clock = &radeon_atom_set_memory_clock, 1748 .get_pcie_lanes = &r600_get_pcie_lanes, 1749 .set_pcie_lanes = &r600_set_pcie_lanes, 1750 .set_clock_gating = NULL, 1751 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1752 .get_temperature = &evergreen_get_temp, 1753 }, 1754 .dpm = { 1755 .init = &ni_dpm_init, 1756 .setup_asic = &ni_dpm_setup_asic, 1757 .enable = &ni_dpm_enable, 1758 .late_enable = &rv770_dpm_late_enable, 1759 .disable = &ni_dpm_disable, 1760 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1761 .set_power_state = &ni_dpm_set_power_state, 1762 .post_set_power_state = &ni_dpm_post_set_power_state, 1763 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1764 .fini = &ni_dpm_fini, 1765 .get_sclk = &ni_dpm_get_sclk, 1766 .get_mclk = &ni_dpm_get_mclk, 1767 .print_power_state = &ni_dpm_print_power_state, 1768 #ifdef CONFIG_DEBUG_FS 1769 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1770 #endif 1771 .force_performance_level = &ni_dpm_force_performance_level, 1772 .vblank_too_short = &ni_dpm_vblank_too_short, 1773 .get_current_sclk = &ni_dpm_get_current_sclk, 1774 .get_current_mclk = &ni_dpm_get_current_mclk, 1775 }, 1776 .pflip = { 1777 .page_flip = &evergreen_page_flip, 1778 .page_flip_pending = &evergreen_page_flip_pending, 1779 }, 1780 }; 1781 1782 static struct radeon_asic_ring trinity_vce_ring = { 1783 .ib_execute = &radeon_vce_ib_execute, 1784 .emit_fence = &radeon_vce_fence_emit, 1785 .emit_semaphore = &radeon_vce_semaphore_emit, 1786 .cs_parse = &radeon_vce_cs_parse, 1787 .ring_test = &radeon_vce_ring_test, 1788 .ib_test = &radeon_vce_ib_test, 1789 .is_lockup = &radeon_ring_test_lockup, 1790 .get_rptr = &vce_v1_0_get_rptr, 1791 .get_wptr = &vce_v1_0_get_wptr, 1792 .set_wptr = &vce_v1_0_set_wptr, 1793 }; 1794 1795 static struct radeon_asic trinity_asic = { 1796 .init = &cayman_init, 1797 .fini = &cayman_fini, 1798 .suspend = &cayman_suspend, 1799 .resume = &cayman_resume, 1800 .asic_reset = &cayman_asic_reset, 1801 .vga_set_state = &r600_vga_set_state, 1802 .mmio_hdp_flush = r600_mmio_hdp_flush, 1803 .gui_idle = &r600_gui_idle, 1804 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1805 .get_xclk = &r600_get_xclk, 1806 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1807 .get_allowed_info_register = cayman_get_allowed_info_register, 1808 .gart = { 1809 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1810 .get_page_entry = &rs600_gart_get_page_entry, 1811 .set_page = &rs600_gart_set_page, 1812 }, 1813 .vm = { 1814 .init = &cayman_vm_init, 1815 .fini = &cayman_vm_fini, 1816 .copy_pages = &cayman_dma_vm_copy_pages, 1817 .write_pages = &cayman_dma_vm_write_pages, 1818 .set_pages = &cayman_dma_vm_set_pages, 1819 .pad_ib = &cayman_dma_vm_pad_ib, 1820 }, 1821 .ring = { 1822 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1823 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1824 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1825 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1826 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1827 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1828 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1829 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1830 }, 1831 .irq = { 1832 .set = &evergreen_irq_set, 1833 .process = &evergreen_irq_process, 1834 }, 1835 .display = { 1836 .bandwidth_update = &dce6_bandwidth_update, 1837 .get_vblank_counter = &evergreen_get_vblank_counter, 1838 .wait_for_vblank = &dce4_wait_for_vblank, 1839 .set_backlight_level = &atombios_set_backlight_level, 1840 .get_backlight_level = &atombios_get_backlight_level, 1841 }, 1842 .copy = { 1843 .blit = &r600_copy_cpdma, 1844 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1845 .dma = &evergreen_copy_dma, 1846 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1847 .copy = &evergreen_copy_dma, 1848 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1849 }, 1850 .surface = { 1851 .set_reg = r600_set_surface_reg, 1852 .clear_reg = r600_clear_surface_reg, 1853 }, 1854 .hpd = { 1855 .init = &evergreen_hpd_init, 1856 .fini = &evergreen_hpd_fini, 1857 .sense = &evergreen_hpd_sense, 1858 .set_polarity = &evergreen_hpd_set_polarity, 1859 }, 1860 .pm = { 1861 .misc = &evergreen_pm_misc, 1862 .prepare = &evergreen_pm_prepare, 1863 .finish = &evergreen_pm_finish, 1864 .init_profile = &sumo_pm_init_profile, 1865 .get_dynpm_state = &r600_pm_get_dynpm_state, 1866 .get_engine_clock = &radeon_atom_get_engine_clock, 1867 .set_engine_clock = &radeon_atom_set_engine_clock, 1868 .get_memory_clock = NULL, 1869 .set_memory_clock = NULL, 1870 .get_pcie_lanes = NULL, 1871 .set_pcie_lanes = NULL, 1872 .set_clock_gating = NULL, 1873 .set_uvd_clocks = &sumo_set_uvd_clocks, 1874 .set_vce_clocks = &tn_set_vce_clocks, 1875 .get_temperature = &tn_get_temp, 1876 }, 1877 .dpm = { 1878 .init = &trinity_dpm_init, 1879 .setup_asic = &trinity_dpm_setup_asic, 1880 .enable = &trinity_dpm_enable, 1881 .late_enable = &trinity_dpm_late_enable, 1882 .disable = &trinity_dpm_disable, 1883 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1884 .set_power_state = &trinity_dpm_set_power_state, 1885 .post_set_power_state = &trinity_dpm_post_set_power_state, 1886 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1887 .fini = &trinity_dpm_fini, 1888 .get_sclk = &trinity_dpm_get_sclk, 1889 .get_mclk = &trinity_dpm_get_mclk, 1890 .print_power_state = &trinity_dpm_print_power_state, 1891 #ifdef CONFIG_DEBUG_FS 1892 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1893 #endif 1894 .force_performance_level = &trinity_dpm_force_performance_level, 1895 .enable_bapm = &trinity_dpm_enable_bapm, 1896 .get_current_sclk = &trinity_dpm_get_current_sclk, 1897 .get_current_mclk = &trinity_dpm_get_current_mclk, 1898 }, 1899 .pflip = { 1900 .page_flip = &evergreen_page_flip, 1901 .page_flip_pending = &evergreen_page_flip_pending, 1902 }, 1903 }; 1904 1905 static struct radeon_asic_ring si_gfx_ring = { 1906 .ib_execute = &si_ring_ib_execute, 1907 .ib_parse = &si_ib_parse, 1908 .emit_fence = &si_fence_ring_emit, 1909 .emit_semaphore = &r600_semaphore_ring_emit, 1910 .cs_parse = NULL, 1911 .ring_test = &r600_ring_test, 1912 .ib_test = &r600_ib_test, 1913 .is_lockup = &si_gfx_is_lockup, 1914 .vm_flush = &si_vm_flush, 1915 .get_rptr = &cayman_gfx_get_rptr, 1916 .get_wptr = &cayman_gfx_get_wptr, 1917 .set_wptr = &cayman_gfx_set_wptr, 1918 }; 1919 1920 static struct radeon_asic_ring si_dma_ring = { 1921 .ib_execute = &cayman_dma_ring_ib_execute, 1922 .ib_parse = &evergreen_dma_ib_parse, 1923 .emit_fence = &evergreen_dma_fence_ring_emit, 1924 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1925 .cs_parse = NULL, 1926 .ring_test = &r600_dma_ring_test, 1927 .ib_test = &r600_dma_ib_test, 1928 .is_lockup = &si_dma_is_lockup, 1929 .vm_flush = &si_dma_vm_flush, 1930 .get_rptr = &cayman_dma_get_rptr, 1931 .get_wptr = &cayman_dma_get_wptr, 1932 .set_wptr = &cayman_dma_set_wptr, 1933 }; 1934 1935 static struct radeon_asic si_asic = { 1936 .init = &si_init, 1937 .fini = &si_fini, 1938 .suspend = &si_suspend, 1939 .resume = &si_resume, 1940 .asic_reset = &si_asic_reset, 1941 .vga_set_state = &r600_vga_set_state, 1942 .mmio_hdp_flush = r600_mmio_hdp_flush, 1943 .gui_idle = &r600_gui_idle, 1944 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1945 .get_xclk = &si_get_xclk, 1946 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1947 .get_allowed_info_register = si_get_allowed_info_register, 1948 .gart = { 1949 .tlb_flush = &si_pcie_gart_tlb_flush, 1950 .get_page_entry = &rs600_gart_get_page_entry, 1951 .set_page = &rs600_gart_set_page, 1952 }, 1953 .vm = { 1954 .init = &si_vm_init, 1955 .fini = &si_vm_fini, 1956 .copy_pages = &si_dma_vm_copy_pages, 1957 .write_pages = &si_dma_vm_write_pages, 1958 .set_pages = &si_dma_vm_set_pages, 1959 .pad_ib = &cayman_dma_vm_pad_ib, 1960 }, 1961 .ring = { 1962 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1963 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1964 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1965 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1966 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1967 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1968 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, 1969 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, 1970 }, 1971 .irq = { 1972 .set = &si_irq_set, 1973 .process = &si_irq_process, 1974 }, 1975 .display = { 1976 .bandwidth_update = &dce6_bandwidth_update, 1977 .get_vblank_counter = &evergreen_get_vblank_counter, 1978 .wait_for_vblank = &dce4_wait_for_vblank, 1979 .set_backlight_level = &atombios_set_backlight_level, 1980 .get_backlight_level = &atombios_get_backlight_level, 1981 }, 1982 .copy = { 1983 .blit = &r600_copy_cpdma, 1984 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1985 .dma = &si_copy_dma, 1986 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1987 .copy = &si_copy_dma, 1988 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1989 }, 1990 .surface = { 1991 .set_reg = r600_set_surface_reg, 1992 .clear_reg = r600_clear_surface_reg, 1993 }, 1994 .hpd = { 1995 .init = &evergreen_hpd_init, 1996 .fini = &evergreen_hpd_fini, 1997 .sense = &evergreen_hpd_sense, 1998 .set_polarity = &evergreen_hpd_set_polarity, 1999 }, 2000 .pm = { 2001 .misc = &evergreen_pm_misc, 2002 .prepare = &evergreen_pm_prepare, 2003 .finish = &evergreen_pm_finish, 2004 .init_profile = &sumo_pm_init_profile, 2005 .get_dynpm_state = &r600_pm_get_dynpm_state, 2006 .get_engine_clock = &radeon_atom_get_engine_clock, 2007 .set_engine_clock = &radeon_atom_set_engine_clock, 2008 .get_memory_clock = &radeon_atom_get_memory_clock, 2009 .set_memory_clock = &radeon_atom_set_memory_clock, 2010 .get_pcie_lanes = &r600_get_pcie_lanes, 2011 .set_pcie_lanes = &r600_set_pcie_lanes, 2012 .set_clock_gating = NULL, 2013 .set_uvd_clocks = &si_set_uvd_clocks, 2014 .set_vce_clocks = &si_set_vce_clocks, 2015 .get_temperature = &si_get_temp, 2016 }, 2017 .dpm = { 2018 .init = &si_dpm_init, 2019 .setup_asic = &si_dpm_setup_asic, 2020 .enable = &si_dpm_enable, 2021 .late_enable = &si_dpm_late_enable, 2022 .disable = &si_dpm_disable, 2023 .pre_set_power_state = &si_dpm_pre_set_power_state, 2024 .set_power_state = &si_dpm_set_power_state, 2025 .post_set_power_state = &si_dpm_post_set_power_state, 2026 .display_configuration_changed = &si_dpm_display_configuration_changed, 2027 .fini = &si_dpm_fini, 2028 .get_sclk = &ni_dpm_get_sclk, 2029 .get_mclk = &ni_dpm_get_mclk, 2030 .print_power_state = &ni_dpm_print_power_state, 2031 #ifdef CONFIG_DEBUG_FS 2032 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2033 #endif 2034 .force_performance_level = &si_dpm_force_performance_level, 2035 .vblank_too_short = &ni_dpm_vblank_too_short, 2036 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, 2037 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, 2038 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, 2039 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, 2040 .get_current_sclk = &si_dpm_get_current_sclk, 2041 .get_current_mclk = &si_dpm_get_current_mclk, 2042 }, 2043 .pflip = { 2044 .page_flip = &evergreen_page_flip, 2045 .page_flip_pending = &evergreen_page_flip_pending, 2046 }, 2047 }; 2048 2049 static struct radeon_asic_ring ci_gfx_ring = { 2050 .ib_execute = &cik_ring_ib_execute, 2051 .ib_parse = &cik_ib_parse, 2052 .emit_fence = &cik_fence_gfx_ring_emit, 2053 .emit_semaphore = &cik_semaphore_ring_emit, 2054 .cs_parse = NULL, 2055 .ring_test = &cik_ring_test, 2056 .ib_test = &cik_ib_test, 2057 .is_lockup = &cik_gfx_is_lockup, 2058 .vm_flush = &cik_vm_flush, 2059 .get_rptr = &cik_gfx_get_rptr, 2060 .get_wptr = &cik_gfx_get_wptr, 2061 .set_wptr = &cik_gfx_set_wptr, 2062 }; 2063 2064 static struct radeon_asic_ring ci_cp_ring = { 2065 .ib_execute = &cik_ring_ib_execute, 2066 .ib_parse = &cik_ib_parse, 2067 .emit_fence = &cik_fence_compute_ring_emit, 2068 .emit_semaphore = &cik_semaphore_ring_emit, 2069 .cs_parse = NULL, 2070 .ring_test = &cik_ring_test, 2071 .ib_test = &cik_ib_test, 2072 .is_lockup = &cik_gfx_is_lockup, 2073 .vm_flush = &cik_vm_flush, 2074 .get_rptr = &cik_compute_get_rptr, 2075 .get_wptr = &cik_compute_get_wptr, 2076 .set_wptr = &cik_compute_set_wptr, 2077 }; 2078 2079 static struct radeon_asic_ring ci_dma_ring = { 2080 .ib_execute = &cik_sdma_ring_ib_execute, 2081 .ib_parse = &cik_ib_parse, 2082 .emit_fence = &cik_sdma_fence_ring_emit, 2083 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2084 .cs_parse = NULL, 2085 .ring_test = &cik_sdma_ring_test, 2086 .ib_test = &cik_sdma_ib_test, 2087 .is_lockup = &cik_sdma_is_lockup, 2088 .vm_flush = &cik_dma_vm_flush, 2089 .get_rptr = &cik_sdma_get_rptr, 2090 .get_wptr = &cik_sdma_get_wptr, 2091 .set_wptr = &cik_sdma_set_wptr, 2092 }; 2093 2094 static struct radeon_asic_ring ci_vce_ring = { 2095 .ib_execute = &radeon_vce_ib_execute, 2096 .emit_fence = &radeon_vce_fence_emit, 2097 .emit_semaphore = &radeon_vce_semaphore_emit, 2098 .cs_parse = &radeon_vce_cs_parse, 2099 .ring_test = &radeon_vce_ring_test, 2100 .ib_test = &radeon_vce_ib_test, 2101 .is_lockup = &radeon_ring_test_lockup, 2102 .get_rptr = &vce_v1_0_get_rptr, 2103 .get_wptr = &vce_v1_0_get_wptr, 2104 .set_wptr = &vce_v1_0_set_wptr, 2105 }; 2106 2107 static struct radeon_asic ci_asic = { 2108 .init = &cik_init, 2109 .fini = &cik_fini, 2110 .suspend = &cik_suspend, 2111 .resume = &cik_resume, 2112 .asic_reset = &cik_asic_reset, 2113 .vga_set_state = &r600_vga_set_state, 2114 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2115 .gui_idle = &r600_gui_idle, 2116 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2117 .get_xclk = &cik_get_xclk, 2118 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2119 .get_allowed_info_register = cik_get_allowed_info_register, 2120 .gart = { 2121 .tlb_flush = &cik_pcie_gart_tlb_flush, 2122 .get_page_entry = &rs600_gart_get_page_entry, 2123 .set_page = &rs600_gart_set_page, 2124 }, 2125 .vm = { 2126 .init = &cik_vm_init, 2127 .fini = &cik_vm_fini, 2128 .copy_pages = &cik_sdma_vm_copy_pages, 2129 .write_pages = &cik_sdma_vm_write_pages, 2130 .set_pages = &cik_sdma_vm_set_pages, 2131 .pad_ib = &cik_sdma_vm_pad_ib, 2132 }, 2133 .ring = { 2134 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2135 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2136 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2137 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2138 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2139 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2140 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2141 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2142 }, 2143 .irq = { 2144 .set = &cik_irq_set, 2145 .process = &cik_irq_process, 2146 }, 2147 .display = { 2148 .bandwidth_update = &dce8_bandwidth_update, 2149 .get_vblank_counter = &evergreen_get_vblank_counter, 2150 .wait_for_vblank = &dce4_wait_for_vblank, 2151 .set_backlight_level = &atombios_set_backlight_level, 2152 .get_backlight_level = &atombios_get_backlight_level, 2153 }, 2154 .copy = { 2155 .blit = &cik_copy_cpdma, 2156 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2157 .dma = &cik_copy_dma, 2158 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2159 .copy = &cik_copy_dma, 2160 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2161 }, 2162 .surface = { 2163 .set_reg = r600_set_surface_reg, 2164 .clear_reg = r600_clear_surface_reg, 2165 }, 2166 .hpd = { 2167 .init = &evergreen_hpd_init, 2168 .fini = &evergreen_hpd_fini, 2169 .sense = &evergreen_hpd_sense, 2170 .set_polarity = &evergreen_hpd_set_polarity, 2171 }, 2172 .pm = { 2173 .misc = &evergreen_pm_misc, 2174 .prepare = &evergreen_pm_prepare, 2175 .finish = &evergreen_pm_finish, 2176 .init_profile = &sumo_pm_init_profile, 2177 .get_dynpm_state = &r600_pm_get_dynpm_state, 2178 .get_engine_clock = &radeon_atom_get_engine_clock, 2179 .set_engine_clock = &radeon_atom_set_engine_clock, 2180 .get_memory_clock = &radeon_atom_get_memory_clock, 2181 .set_memory_clock = &radeon_atom_set_memory_clock, 2182 .get_pcie_lanes = NULL, 2183 .set_pcie_lanes = NULL, 2184 .set_clock_gating = NULL, 2185 .set_uvd_clocks = &cik_set_uvd_clocks, 2186 .set_vce_clocks = &cik_set_vce_clocks, 2187 .get_temperature = &ci_get_temp, 2188 }, 2189 .dpm = { 2190 .init = &ci_dpm_init, 2191 .setup_asic = &ci_dpm_setup_asic, 2192 .enable = &ci_dpm_enable, 2193 .late_enable = &ci_dpm_late_enable, 2194 .disable = &ci_dpm_disable, 2195 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2196 .set_power_state = &ci_dpm_set_power_state, 2197 .post_set_power_state = &ci_dpm_post_set_power_state, 2198 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2199 .fini = &ci_dpm_fini, 2200 .get_sclk = &ci_dpm_get_sclk, 2201 .get_mclk = &ci_dpm_get_mclk, 2202 .print_power_state = &ci_dpm_print_power_state, 2203 #ifdef CONFIG_DEBUG_FS 2204 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2205 #endif 2206 .force_performance_level = &ci_dpm_force_performance_level, 2207 .vblank_too_short = &ci_dpm_vblank_too_short, 2208 .powergate_uvd = &ci_dpm_powergate_uvd, 2209 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, 2210 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, 2211 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, 2212 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, 2213 .get_current_sclk = &ci_dpm_get_current_sclk, 2214 .get_current_mclk = &ci_dpm_get_current_mclk, 2215 }, 2216 .pflip = { 2217 .page_flip = &evergreen_page_flip, 2218 .page_flip_pending = &evergreen_page_flip_pending, 2219 }, 2220 }; 2221 2222 static struct radeon_asic kv_asic = { 2223 .init = &cik_init, 2224 .fini = &cik_fini, 2225 .suspend = &cik_suspend, 2226 .resume = &cik_resume, 2227 .asic_reset = &cik_asic_reset, 2228 .vga_set_state = &r600_vga_set_state, 2229 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2230 .gui_idle = &r600_gui_idle, 2231 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2232 .get_xclk = &cik_get_xclk, 2233 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2234 .get_allowed_info_register = cik_get_allowed_info_register, 2235 .gart = { 2236 .tlb_flush = &cik_pcie_gart_tlb_flush, 2237 .get_page_entry = &rs600_gart_get_page_entry, 2238 .set_page = &rs600_gart_set_page, 2239 }, 2240 .vm = { 2241 .init = &cik_vm_init, 2242 .fini = &cik_vm_fini, 2243 .copy_pages = &cik_sdma_vm_copy_pages, 2244 .write_pages = &cik_sdma_vm_write_pages, 2245 .set_pages = &cik_sdma_vm_set_pages, 2246 .pad_ib = &cik_sdma_vm_pad_ib, 2247 }, 2248 .ring = { 2249 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2250 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2251 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2252 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2253 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2254 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2255 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2256 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2257 }, 2258 .irq = { 2259 .set = &cik_irq_set, 2260 .process = &cik_irq_process, 2261 }, 2262 .display = { 2263 .bandwidth_update = &dce8_bandwidth_update, 2264 .get_vblank_counter = &evergreen_get_vblank_counter, 2265 .wait_for_vblank = &dce4_wait_for_vblank, 2266 .set_backlight_level = &atombios_set_backlight_level, 2267 .get_backlight_level = &atombios_get_backlight_level, 2268 }, 2269 .copy = { 2270 .blit = &cik_copy_cpdma, 2271 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2272 .dma = &cik_copy_dma, 2273 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2274 .copy = &cik_copy_dma, 2275 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2276 }, 2277 .surface = { 2278 .set_reg = r600_set_surface_reg, 2279 .clear_reg = r600_clear_surface_reg, 2280 }, 2281 .hpd = { 2282 .init = &evergreen_hpd_init, 2283 .fini = &evergreen_hpd_fini, 2284 .sense = &evergreen_hpd_sense, 2285 .set_polarity = &evergreen_hpd_set_polarity, 2286 }, 2287 .pm = { 2288 .misc = &evergreen_pm_misc, 2289 .prepare = &evergreen_pm_prepare, 2290 .finish = &evergreen_pm_finish, 2291 .init_profile = &sumo_pm_init_profile, 2292 .get_dynpm_state = &r600_pm_get_dynpm_state, 2293 .get_engine_clock = &radeon_atom_get_engine_clock, 2294 .set_engine_clock = &radeon_atom_set_engine_clock, 2295 .get_memory_clock = &radeon_atom_get_memory_clock, 2296 .set_memory_clock = &radeon_atom_set_memory_clock, 2297 .get_pcie_lanes = NULL, 2298 .set_pcie_lanes = NULL, 2299 .set_clock_gating = NULL, 2300 .set_uvd_clocks = &cik_set_uvd_clocks, 2301 .set_vce_clocks = &cik_set_vce_clocks, 2302 .get_temperature = &kv_get_temp, 2303 }, 2304 .dpm = { 2305 .init = &kv_dpm_init, 2306 .setup_asic = &kv_dpm_setup_asic, 2307 .enable = &kv_dpm_enable, 2308 .late_enable = &kv_dpm_late_enable, 2309 .disable = &kv_dpm_disable, 2310 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2311 .set_power_state = &kv_dpm_set_power_state, 2312 .post_set_power_state = &kv_dpm_post_set_power_state, 2313 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2314 .fini = &kv_dpm_fini, 2315 .get_sclk = &kv_dpm_get_sclk, 2316 .get_mclk = &kv_dpm_get_mclk, 2317 .print_power_state = &kv_dpm_print_power_state, 2318 #ifdef CONFIG_DEBUG_FS 2319 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2320 #endif 2321 .force_performance_level = &kv_dpm_force_performance_level, 2322 .powergate_uvd = &kv_dpm_powergate_uvd, 2323 .enable_bapm = &kv_dpm_enable_bapm, 2324 .get_current_sclk = &kv_dpm_get_current_sclk, 2325 .get_current_mclk = &kv_dpm_get_current_mclk, 2326 }, 2327 .pflip = { 2328 .page_flip = &evergreen_page_flip, 2329 .page_flip_pending = &evergreen_page_flip_pending, 2330 }, 2331 }; 2332 2333 /** 2334 * radeon_asic_init - register asic specific callbacks 2335 * 2336 * @rdev: radeon device pointer 2337 * 2338 * Registers the appropriate asic specific callbacks for each 2339 * chip family. Also sets other asics specific info like the number 2340 * of crtcs and the register aperture accessors (all asics). 2341 * Returns 0 for success. 2342 */ 2343 int radeon_asic_init(struct radeon_device *rdev) 2344 { 2345 radeon_register_accessor_init(rdev); 2346 2347 /* set the number of crtcs */ 2348 if (rdev->flags & RADEON_SINGLE_CRTC) 2349 rdev->num_crtc = 1; 2350 else 2351 rdev->num_crtc = 2; 2352 2353 rdev->has_uvd = false; 2354 2355 switch (rdev->family) { 2356 case CHIP_R100: 2357 case CHIP_RV100: 2358 case CHIP_RS100: 2359 case CHIP_RV200: 2360 case CHIP_RS200: 2361 rdev->asic = &r100_asic; 2362 break; 2363 case CHIP_R200: 2364 case CHIP_RV250: 2365 case CHIP_RS300: 2366 case CHIP_RV280: 2367 rdev->asic = &r200_asic; 2368 break; 2369 case CHIP_R300: 2370 case CHIP_R350: 2371 case CHIP_RV350: 2372 case CHIP_RV380: 2373 if (rdev->flags & RADEON_IS_PCIE) 2374 rdev->asic = &r300_asic_pcie; 2375 else 2376 rdev->asic = &r300_asic; 2377 break; 2378 case CHIP_R420: 2379 case CHIP_R423: 2380 case CHIP_RV410: 2381 rdev->asic = &r420_asic; 2382 /* handle macs */ 2383 if (rdev->bios == NULL) { 2384 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2385 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2386 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2387 rdev->asic->pm.set_memory_clock = NULL; 2388 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2389 } 2390 break; 2391 case CHIP_RS400: 2392 case CHIP_RS480: 2393 rdev->asic = &rs400_asic; 2394 break; 2395 case CHIP_RS600: 2396 rdev->asic = &rs600_asic; 2397 break; 2398 case CHIP_RS690: 2399 case CHIP_RS740: 2400 rdev->asic = &rs690_asic; 2401 break; 2402 case CHIP_RV515: 2403 rdev->asic = &rv515_asic; 2404 break; 2405 case CHIP_R520: 2406 case CHIP_RV530: 2407 case CHIP_RV560: 2408 case CHIP_RV570: 2409 case CHIP_R580: 2410 rdev->asic = &r520_asic; 2411 break; 2412 case CHIP_R600: 2413 rdev->asic = &r600_asic; 2414 break; 2415 case CHIP_RV610: 2416 case CHIP_RV630: 2417 case CHIP_RV620: 2418 case CHIP_RV635: 2419 case CHIP_RV670: 2420 rdev->asic = &rv6xx_asic; 2421 rdev->has_uvd = true; 2422 break; 2423 case CHIP_RS780: 2424 case CHIP_RS880: 2425 rdev->asic = &rs780_asic; 2426 /* 760G/780V/880V don't have UVD */ 2427 if ((rdev->pdev->device == 0x9616)|| 2428 (rdev->pdev->device == 0x9611)|| 2429 (rdev->pdev->device == 0x9613)|| 2430 (rdev->pdev->device == 0x9711)|| 2431 (rdev->pdev->device == 0x9713)) 2432 rdev->has_uvd = false; 2433 else 2434 rdev->has_uvd = true; 2435 break; 2436 case CHIP_RV770: 2437 case CHIP_RV730: 2438 case CHIP_RV710: 2439 case CHIP_RV740: 2440 rdev->asic = &rv770_asic; 2441 rdev->has_uvd = true; 2442 break; 2443 case CHIP_CEDAR: 2444 case CHIP_REDWOOD: 2445 case CHIP_JUNIPER: 2446 case CHIP_CYPRESS: 2447 case CHIP_HEMLOCK: 2448 /* set num crtcs */ 2449 if (rdev->family == CHIP_CEDAR) 2450 rdev->num_crtc = 4; 2451 else 2452 rdev->num_crtc = 6; 2453 rdev->asic = &evergreen_asic; 2454 rdev->has_uvd = true; 2455 break; 2456 case CHIP_PALM: 2457 case CHIP_SUMO: 2458 case CHIP_SUMO2: 2459 rdev->asic = &sumo_asic; 2460 rdev->has_uvd = true; 2461 break; 2462 case CHIP_BARTS: 2463 case CHIP_TURKS: 2464 case CHIP_CAICOS: 2465 /* set num crtcs */ 2466 if (rdev->family == CHIP_CAICOS) 2467 rdev->num_crtc = 4; 2468 else 2469 rdev->num_crtc = 6; 2470 rdev->asic = &btc_asic; 2471 rdev->has_uvd = true; 2472 break; 2473 case CHIP_CAYMAN: 2474 rdev->asic = &cayman_asic; 2475 /* set num crtcs */ 2476 rdev->num_crtc = 6; 2477 rdev->has_uvd = true; 2478 break; 2479 case CHIP_ARUBA: 2480 rdev->asic = &trinity_asic; 2481 /* set num crtcs */ 2482 rdev->num_crtc = 4; 2483 rdev->has_uvd = true; 2484 rdev->cg_flags = 2485 RADEON_CG_SUPPORT_VCE_MGCG; 2486 break; 2487 case CHIP_TAHITI: 2488 case CHIP_PITCAIRN: 2489 case CHIP_VERDE: 2490 case CHIP_OLAND: 2491 case CHIP_HAINAN: 2492 rdev->asic = &si_asic; 2493 /* set num crtcs */ 2494 if (rdev->family == CHIP_HAINAN) 2495 rdev->num_crtc = 0; 2496 else if (rdev->family == CHIP_OLAND) 2497 rdev->num_crtc = 2; 2498 else 2499 rdev->num_crtc = 6; 2500 if (rdev->family == CHIP_HAINAN) 2501 rdev->has_uvd = false; 2502 else 2503 rdev->has_uvd = true; 2504 switch (rdev->family) { 2505 case CHIP_TAHITI: 2506 rdev->cg_flags = 2507 RADEON_CG_SUPPORT_GFX_MGCG | 2508 RADEON_CG_SUPPORT_GFX_MGLS | 2509 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2510 RADEON_CG_SUPPORT_GFX_CGLS | 2511 RADEON_CG_SUPPORT_GFX_CGTS | 2512 RADEON_CG_SUPPORT_GFX_CP_LS | 2513 RADEON_CG_SUPPORT_MC_MGCG | 2514 RADEON_CG_SUPPORT_SDMA_MGCG | 2515 RADEON_CG_SUPPORT_BIF_LS | 2516 RADEON_CG_SUPPORT_VCE_MGCG | 2517 RADEON_CG_SUPPORT_UVD_MGCG | 2518 RADEON_CG_SUPPORT_HDP_LS | 2519 RADEON_CG_SUPPORT_HDP_MGCG; 2520 rdev->pg_flags = 0; 2521 break; 2522 case CHIP_PITCAIRN: 2523 rdev->cg_flags = 2524 RADEON_CG_SUPPORT_GFX_MGCG | 2525 RADEON_CG_SUPPORT_GFX_MGLS | 2526 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2527 RADEON_CG_SUPPORT_GFX_CGLS | 2528 RADEON_CG_SUPPORT_GFX_CGTS | 2529 RADEON_CG_SUPPORT_GFX_CP_LS | 2530 RADEON_CG_SUPPORT_GFX_RLC_LS | 2531 RADEON_CG_SUPPORT_MC_LS | 2532 RADEON_CG_SUPPORT_MC_MGCG | 2533 RADEON_CG_SUPPORT_SDMA_MGCG | 2534 RADEON_CG_SUPPORT_BIF_LS | 2535 RADEON_CG_SUPPORT_VCE_MGCG | 2536 RADEON_CG_SUPPORT_UVD_MGCG | 2537 RADEON_CG_SUPPORT_HDP_LS | 2538 RADEON_CG_SUPPORT_HDP_MGCG; 2539 rdev->pg_flags = 0; 2540 break; 2541 case CHIP_VERDE: 2542 rdev->cg_flags = 2543 RADEON_CG_SUPPORT_GFX_MGCG | 2544 RADEON_CG_SUPPORT_GFX_MGLS | 2545 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2546 RADEON_CG_SUPPORT_GFX_CGLS | 2547 RADEON_CG_SUPPORT_GFX_CGTS | 2548 RADEON_CG_SUPPORT_GFX_CP_LS | 2549 RADEON_CG_SUPPORT_GFX_RLC_LS | 2550 RADEON_CG_SUPPORT_MC_LS | 2551 RADEON_CG_SUPPORT_MC_MGCG | 2552 RADEON_CG_SUPPORT_SDMA_MGCG | 2553 RADEON_CG_SUPPORT_BIF_LS | 2554 RADEON_CG_SUPPORT_VCE_MGCG | 2555 RADEON_CG_SUPPORT_UVD_MGCG | 2556 RADEON_CG_SUPPORT_HDP_LS | 2557 RADEON_CG_SUPPORT_HDP_MGCG; 2558 rdev->pg_flags = 0 | 2559 /*RADEON_PG_SUPPORT_GFX_PG | */ 2560 RADEON_PG_SUPPORT_SDMA; 2561 break; 2562 case CHIP_OLAND: 2563 rdev->cg_flags = 2564 RADEON_CG_SUPPORT_GFX_MGCG | 2565 RADEON_CG_SUPPORT_GFX_MGLS | 2566 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2567 RADEON_CG_SUPPORT_GFX_CGLS | 2568 RADEON_CG_SUPPORT_GFX_CGTS | 2569 RADEON_CG_SUPPORT_GFX_CP_LS | 2570 RADEON_CG_SUPPORT_GFX_RLC_LS | 2571 RADEON_CG_SUPPORT_MC_LS | 2572 RADEON_CG_SUPPORT_MC_MGCG | 2573 RADEON_CG_SUPPORT_SDMA_MGCG | 2574 RADEON_CG_SUPPORT_BIF_LS | 2575 RADEON_CG_SUPPORT_UVD_MGCG | 2576 RADEON_CG_SUPPORT_HDP_LS | 2577 RADEON_CG_SUPPORT_HDP_MGCG; 2578 rdev->pg_flags = 0; 2579 break; 2580 case CHIP_HAINAN: 2581 rdev->cg_flags = 2582 RADEON_CG_SUPPORT_GFX_MGCG | 2583 RADEON_CG_SUPPORT_GFX_MGLS | 2584 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2585 RADEON_CG_SUPPORT_GFX_CGLS | 2586 RADEON_CG_SUPPORT_GFX_CGTS | 2587 RADEON_CG_SUPPORT_GFX_CP_LS | 2588 RADEON_CG_SUPPORT_GFX_RLC_LS | 2589 RADEON_CG_SUPPORT_MC_LS | 2590 RADEON_CG_SUPPORT_MC_MGCG | 2591 RADEON_CG_SUPPORT_SDMA_MGCG | 2592 RADEON_CG_SUPPORT_BIF_LS | 2593 RADEON_CG_SUPPORT_HDP_LS | 2594 RADEON_CG_SUPPORT_HDP_MGCG; 2595 rdev->pg_flags = 0; 2596 break; 2597 default: 2598 rdev->cg_flags = 0; 2599 rdev->pg_flags = 0; 2600 break; 2601 } 2602 break; 2603 case CHIP_BONAIRE: 2604 case CHIP_HAWAII: 2605 rdev->asic = &ci_asic; 2606 rdev->num_crtc = 6; 2607 rdev->has_uvd = true; 2608 if (rdev->family == CHIP_BONAIRE) { 2609 rdev->cg_flags = 2610 RADEON_CG_SUPPORT_GFX_MGCG | 2611 RADEON_CG_SUPPORT_GFX_MGLS | 2612 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2613 RADEON_CG_SUPPORT_GFX_CGLS | 2614 RADEON_CG_SUPPORT_GFX_CGTS | 2615 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2616 RADEON_CG_SUPPORT_GFX_CP_LS | 2617 RADEON_CG_SUPPORT_MC_LS | 2618 RADEON_CG_SUPPORT_MC_MGCG | 2619 RADEON_CG_SUPPORT_SDMA_MGCG | 2620 RADEON_CG_SUPPORT_SDMA_LS | 2621 RADEON_CG_SUPPORT_BIF_LS | 2622 RADEON_CG_SUPPORT_VCE_MGCG | 2623 RADEON_CG_SUPPORT_UVD_MGCG | 2624 RADEON_CG_SUPPORT_HDP_LS | 2625 RADEON_CG_SUPPORT_HDP_MGCG; 2626 rdev->pg_flags = 0; 2627 } else { 2628 rdev->cg_flags = 2629 RADEON_CG_SUPPORT_GFX_MGCG | 2630 RADEON_CG_SUPPORT_GFX_MGLS | 2631 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2632 RADEON_CG_SUPPORT_GFX_CGLS | 2633 RADEON_CG_SUPPORT_GFX_CGTS | 2634 RADEON_CG_SUPPORT_GFX_CP_LS | 2635 RADEON_CG_SUPPORT_MC_LS | 2636 RADEON_CG_SUPPORT_MC_MGCG | 2637 RADEON_CG_SUPPORT_SDMA_MGCG | 2638 RADEON_CG_SUPPORT_SDMA_LS | 2639 RADEON_CG_SUPPORT_BIF_LS | 2640 RADEON_CG_SUPPORT_VCE_MGCG | 2641 RADEON_CG_SUPPORT_UVD_MGCG | 2642 RADEON_CG_SUPPORT_HDP_LS | 2643 RADEON_CG_SUPPORT_HDP_MGCG; 2644 rdev->pg_flags = 0; 2645 } 2646 break; 2647 case CHIP_KAVERI: 2648 case CHIP_KABINI: 2649 case CHIP_MULLINS: 2650 rdev->asic = &kv_asic; 2651 /* set num crtcs */ 2652 if (rdev->family == CHIP_KAVERI) { 2653 rdev->num_crtc = 4; 2654 rdev->cg_flags = 2655 RADEON_CG_SUPPORT_GFX_MGCG | 2656 RADEON_CG_SUPPORT_GFX_MGLS | 2657 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2658 RADEON_CG_SUPPORT_GFX_CGLS | 2659 RADEON_CG_SUPPORT_GFX_CGTS | 2660 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2661 RADEON_CG_SUPPORT_GFX_CP_LS | 2662 RADEON_CG_SUPPORT_SDMA_MGCG | 2663 RADEON_CG_SUPPORT_SDMA_LS | 2664 RADEON_CG_SUPPORT_BIF_LS | 2665 RADEON_CG_SUPPORT_VCE_MGCG | 2666 RADEON_CG_SUPPORT_UVD_MGCG | 2667 RADEON_CG_SUPPORT_HDP_LS | 2668 RADEON_CG_SUPPORT_HDP_MGCG; 2669 rdev->pg_flags = 0; 2670 /*RADEON_PG_SUPPORT_GFX_PG | 2671 RADEON_PG_SUPPORT_GFX_SMG | 2672 RADEON_PG_SUPPORT_GFX_DMG | 2673 RADEON_PG_SUPPORT_UVD | 2674 RADEON_PG_SUPPORT_VCE | 2675 RADEON_PG_SUPPORT_CP | 2676 RADEON_PG_SUPPORT_GDS | 2677 RADEON_PG_SUPPORT_RLC_SMU_HS | 2678 RADEON_PG_SUPPORT_ACP | 2679 RADEON_PG_SUPPORT_SAMU;*/ 2680 } else { 2681 rdev->num_crtc = 2; 2682 rdev->cg_flags = 2683 RADEON_CG_SUPPORT_GFX_MGCG | 2684 RADEON_CG_SUPPORT_GFX_MGLS | 2685 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2686 RADEON_CG_SUPPORT_GFX_CGLS | 2687 RADEON_CG_SUPPORT_GFX_CGTS | 2688 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2689 RADEON_CG_SUPPORT_GFX_CP_LS | 2690 RADEON_CG_SUPPORT_SDMA_MGCG | 2691 RADEON_CG_SUPPORT_SDMA_LS | 2692 RADEON_CG_SUPPORT_BIF_LS | 2693 RADEON_CG_SUPPORT_VCE_MGCG | 2694 RADEON_CG_SUPPORT_UVD_MGCG | 2695 RADEON_CG_SUPPORT_HDP_LS | 2696 RADEON_CG_SUPPORT_HDP_MGCG; 2697 rdev->pg_flags = 0; 2698 /*RADEON_PG_SUPPORT_GFX_PG | 2699 RADEON_PG_SUPPORT_GFX_SMG | 2700 RADEON_PG_SUPPORT_UVD | 2701 RADEON_PG_SUPPORT_VCE | 2702 RADEON_PG_SUPPORT_CP | 2703 RADEON_PG_SUPPORT_GDS | 2704 RADEON_PG_SUPPORT_RLC_SMU_HS | 2705 RADEON_PG_SUPPORT_SAMU;*/ 2706 } 2707 rdev->has_uvd = true; 2708 break; 2709 default: 2710 /* FIXME: not supported yet */ 2711 return -EINVAL; 2712 } 2713 2714 if (rdev->flags & RADEON_IS_IGP) { 2715 rdev->asic->pm.get_memory_clock = NULL; 2716 rdev->asic->pm.set_memory_clock = NULL; 2717 } 2718 2719 return 0; 2720 } 2721 2722
Indexes created Sat Oct 25 01:09:55 GMT 2025