1 /* $NetBSD: radeon_cursor.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_cursor.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <drm/drm_device.h> 33 #include <drm/radeon_drm.h> 34 35 #include "radeon.h" 36 37 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) 38 { 39 struct radeon_device *rdev = crtc->dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 uint32_t cur_lock; 42 43 if (ASIC_IS_DCE4(rdev)) { 44 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 45 if (lock) 46 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 47 else 48 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 49 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 50 } else if (ASIC_IS_AVIVO(rdev)) { 51 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 52 if (lock) 53 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; 54 else 55 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 56 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 57 } else { 58 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); 59 if (lock) 60 cur_lock |= RADEON_CUR_LOCK; 61 else 62 cur_lock &= ~RADEON_CUR_LOCK; 63 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); 64 } 65 } 66 67 static void radeon_hide_cursor(struct drm_crtc *crtc) 68 { 69 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 70 struct radeon_device *rdev = crtc->dev->dev_private; 71 72 if (ASIC_IS_DCE4(rdev)) { 73 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 74 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 75 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 76 } else if (ASIC_IS_AVIVO(rdev)) { 77 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 78 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 79 } else { 80 u32 reg; 81 switch (radeon_crtc->crtc_id) { 82 case 0: 83 reg = RADEON_CRTC_GEN_CNTL; 84 break; 85 case 1: 86 reg = RADEON_CRTC2_GEN_CNTL; 87 break; 88 default: 89 return; 90 } 91 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); 92 } 93 } 94 95 static void radeon_show_cursor(struct drm_crtc *crtc) 96 { 97 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 98 struct radeon_device *rdev = crtc->dev->dev_private; 99 100 if (radeon_crtc->cursor_out_of_bounds) 101 return; 102 103 if (ASIC_IS_DCE4(rdev)) { 104 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 105 upper_32_bits(radeon_crtc->cursor_addr)); 106 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 107 lower_32_bits(radeon_crtc->cursor_addr)); 108 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 109 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 110 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 111 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 112 } else if (ASIC_IS_AVIVO(rdev)) { 113 if (rdev->family >= CHIP_RV770) { 114 if (radeon_crtc->crtc_id) 115 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 116 upper_32_bits(radeon_crtc->cursor_addr)); 117 else 118 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 119 upper_32_bits(radeon_crtc->cursor_addr)); 120 } 121 122 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 123 lower_32_bits(radeon_crtc->cursor_addr)); 124 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 125 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 126 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 127 } else { 128 /* offset is from DISP(2)_BASE_ADDRESS */ 129 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 130 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr); 131 132 switch (radeon_crtc->crtc_id) { 133 case 0: 134 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 135 break; 136 case 1: 137 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 138 break; 139 default: 140 return; 141 } 142 143 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | 144 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), 145 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 146 } 147 } 148 149 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y) 150 { 151 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 152 struct radeon_device *rdev = crtc->dev->dev_private; 153 int xorigin = 0, yorigin = 0; 154 int w = radeon_crtc->cursor_width; 155 156 radeon_crtc->cursor_x = x; 157 radeon_crtc->cursor_y = y; 158 159 if (ASIC_IS_AVIVO(rdev)) { 160 /* avivo cursor are offset into the total surface */ 161 x += crtc->x; 162 y += crtc->y; 163 } 164 165 if (x < 0) 166 xorigin = min(-x, radeon_crtc->max_cursor_width - 1); 167 if (y < 0) 168 yorigin = min(-y, radeon_crtc->max_cursor_height - 1); 169 170 if (!ASIC_IS_AVIVO(rdev)) { 171 x += crtc->x; 172 y += crtc->y; 173 } 174 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 175 176 /* fixed on DCE6 and newer */ 177 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { 178 int i = 0; 179 struct drm_crtc *crtc_p; 180 181 /* 182 * avivo cursor image can't end on 128 pixel boundary or 183 * go past the end of the frame if both crtcs are enabled 184 * 185 * NOTE: It is safe to access crtc->enabled of other crtcs 186 * without holding either the mode_config lock or the other 187 * crtc's lock as long as write access to this flag _always_ 188 * grabs all locks. 189 */ 190 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 191 if (crtc_p->enabled) 192 i++; 193 } 194 if (i > 1) { 195 int cursor_end, frame_end; 196 197 cursor_end = x + w; 198 frame_end = crtc->x + crtc->mode.crtc_hdisplay; 199 if (cursor_end >= frame_end) { 200 w = w - (cursor_end - frame_end); 201 if (!(frame_end & 0x7f)) 202 w--; 203 } else if (cursor_end <= 0) { 204 goto out_of_bounds; 205 } else if (!(cursor_end & 0x7f)) { 206 w--; 207 } 208 if (w <= 0) { 209 goto out_of_bounds; 210 } 211 } 212 } 213 214 if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) || 215 x >= (crtc->x + crtc->mode.hdisplay) || 216 y >= (crtc->y + crtc->mode.vdisplay)) 217 goto out_of_bounds; 218 219 x += xorigin; 220 y += yorigin; 221 222 if (ASIC_IS_DCE4(rdev)) { 223 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 224 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 225 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 226 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 227 } else if (ASIC_IS_AVIVO(rdev)) { 228 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 229 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 230 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 231 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 232 } else { 233 x -= crtc->x; 234 y -= crtc->y; 235 236 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 237 y *= 2; 238 239 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, 240 (RADEON_CUR_LOCK 241 | (xorigin << 16) 242 | yorigin)); 243 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 244 (RADEON_CUR_LOCK 245 | (x << 16) 246 | y)); 247 /* offset is from DISP(2)_BASE_ADDRESS */ 248 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 249 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr + 250 yorigin * 256); 251 } 252 253 if (radeon_crtc->cursor_out_of_bounds) { 254 radeon_crtc->cursor_out_of_bounds = false; 255 if (radeon_crtc->cursor_bo) 256 radeon_show_cursor(crtc); 257 } 258 259 return 0; 260 261 out_of_bounds: 262 if (!radeon_crtc->cursor_out_of_bounds) { 263 radeon_hide_cursor(crtc); 264 radeon_crtc->cursor_out_of_bounds = true; 265 } 266 return 0; 267 } 268 269 int radeon_crtc_cursor_move(struct drm_crtc *crtc, 270 int x, int y) 271 { 272 int ret; 273 274 radeon_lock_cursor(crtc, true); 275 ret = radeon_cursor_move_locked(crtc, x, y); 276 radeon_lock_cursor(crtc, false); 277 278 return ret; 279 } 280 281 int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 282 struct drm_file *file_priv, 283 uint32_t handle, 284 uint32_t width, 285 uint32_t height, 286 int32_t hot_x, 287 int32_t hot_y) 288 { 289 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 290 struct radeon_device *rdev = crtc->dev->dev_private; 291 struct drm_gem_object *obj; 292 struct radeon_bo *robj; 293 int ret; 294 295 if (!handle) { 296 /* turn off cursor */ 297 radeon_hide_cursor(crtc); 298 obj = NULL; 299 goto unpin; 300 } 301 302 if ((width > radeon_crtc->max_cursor_width) || 303 (height > radeon_crtc->max_cursor_height)) { 304 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 305 return -EINVAL; 306 } 307 308 obj = drm_gem_object_lookup(file_priv, handle); 309 if (!obj) { 310 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 311 return -ENOENT; 312 } 313 314 robj = gem_to_radeon_bo(obj); 315 ret = radeon_bo_reserve(robj, false); 316 if (ret != 0) { 317 drm_gem_object_put_unlocked(obj); 318 return ret; 319 } 320 /* Only 27 bit offset for legacy cursor */ 321 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 322 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 323 &radeon_crtc->cursor_addr); 324 radeon_bo_unreserve(robj); 325 if (ret) { 326 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 327 drm_gem_object_put_unlocked(obj); 328 return ret; 329 } 330 331 radeon_lock_cursor(crtc, true); 332 333 if (width != radeon_crtc->cursor_width || 334 height != radeon_crtc->cursor_height || 335 hot_x != radeon_crtc->cursor_hot_x || 336 hot_y != radeon_crtc->cursor_hot_y) { 337 int x, y; 338 339 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x; 340 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y; 341 342 radeon_crtc->cursor_width = width; 343 radeon_crtc->cursor_height = height; 344 radeon_crtc->cursor_hot_x = hot_x; 345 radeon_crtc->cursor_hot_y = hot_y; 346 347 radeon_cursor_move_locked(crtc, x, y); 348 } 349 350 radeon_show_cursor(crtc); 351 352 radeon_lock_cursor(crtc, false); 353 354 unpin: 355 if (radeon_crtc->cursor_bo) { 356 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 357 ret = radeon_bo_reserve(robj, false); 358 if (likely(ret == 0)) { 359 radeon_bo_unpin(robj); 360 radeon_bo_unreserve(robj); 361 } 362 drm_gem_object_put_unlocked(radeon_crtc->cursor_bo); 363 } 364 365 radeon_crtc->cursor_bo = obj; 366 return 0; 367 } 368 369 /** 370 * radeon_cursor_reset - Re-set the current cursor, if any. 371 * 372 * @crtc: drm crtc 373 * 374 * If the CRTC passed in currently has a cursor assigned, this function 375 * makes sure it's visible. 376 */ 377 void radeon_cursor_reset(struct drm_crtc *crtc) 378 { 379 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 380 381 if (radeon_crtc->cursor_bo) { 382 radeon_lock_cursor(crtc, true); 383 384 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, 385 radeon_crtc->cursor_y); 386 387 radeon_show_cursor(crtc); 388 389 radeon_lock_cursor(crtc, false); 390 } 391 } 392
Indexes created Sat Sep 20 22:09:52 GMT 2025