radeon_si_dpm.c revision 1.1.6.3
1 /* $NetBSD: radeon_si_dpm.c,v 1.1.6.3 2020/04/08 14:08:26 martin Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_si_dpm.c,v 1.1.6.3 2020/04/08 14:08:26 martin Exp $"); 28 29 #include "drmP.h" 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "sid.h" 33 #include "r600_dpm.h" 34 #include "si_dpm.h" 35 #include "atom.h" 36 #include <linux/math64.h> 37 #include <linux/seq_file.h> 38 39 #define MC_CG_ARB_FREQ_F0 0x0a 40 #define MC_CG_ARB_FREQ_F1 0x0b 41 #define MC_CG_ARB_FREQ_F2 0x0c 42 #define MC_CG_ARB_FREQ_F3 0x0d 43 44 #define SMC_RAM_END 0x20000 45 46 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 47 48 static const struct si_cac_config_reg cac_weights_tahiti[] = 49 { 50 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 51 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 53 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 59 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 60 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 62 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 63 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 64 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 65 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 66 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 68 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 70 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 71 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 72 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 81 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 85 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 88 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 90 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 107 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 108 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 109 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 110 { 0xFFFFFFFF } 111 }; 112 113 static const struct si_cac_config_reg lcac_tahiti[] = 114 { 115 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 118 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 120 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 122 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 134 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 136 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 138 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 158 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 160 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 162 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 170 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 172 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 174 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 182 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 184 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 186 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 188 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 196 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 197 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 198 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 199 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 200 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 201 { 0xFFFFFFFF } 202 203 }; 204 205 static const struct si_cac_config_reg cac_override_tahiti[] = 206 { 207 { 0xFFFFFFFF } 208 }; 209 210 static const struct si_powertune_data powertune_data_tahiti = 211 { 212 ((1 << 16) | 27027), 213 6, 214 0, 215 4, 216 95, 217 { 218 0UL, 219 0UL, 220 4521550UL, 221 309631529UL, 222 -1270850L, 223 4513710L, 224 40 225 }, 226 595000000UL, 227 12, 228 { 229 0, 230 0, 231 0, 232 0, 233 0, 234 0, 235 0, 236 0 237 }, 238 true 239 }; 240 241 static const struct si_dte_data dte_data_tahiti = 242 { 243 { 1159409, 0, 0, 0, 0 }, 244 { 777, 0, 0, 0, 0 }, 245 2, 246 54000, 247 127000, 248 25, 249 2, 250 10, 251 13, 252 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 253 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 254 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 255 85, 256 false 257 }; 258 259 static const struct si_dte_data dte_data_tahiti_le = 260 { 261 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 262 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 263 0x5, 264 0xAFC8, 265 0x64, 266 0x32, 267 1, 268 0, 269 0x10, 270 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 271 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 272 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 273 85, 274 true 275 }; 276 277 static const struct si_dte_data dte_data_tahiti_pro = 278 { 279 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 280 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 281 5, 282 45000, 283 100, 284 0xA, 285 1, 286 0, 287 0x10, 288 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 289 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 290 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 291 90, 292 true 293 }; 294 295 static const struct si_dte_data dte_data_new_zealand = 296 { 297 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 298 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 299 0x5, 300 0xAFC8, 301 0x69, 302 0x32, 303 1, 304 0, 305 0x10, 306 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 307 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 308 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 309 85, 310 true 311 }; 312 313 static const struct si_dte_data dte_data_aruba_pro = 314 { 315 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 316 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 317 5, 318 45000, 319 100, 320 0xA, 321 1, 322 0, 323 0x10, 324 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 325 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 326 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 327 90, 328 true 329 }; 330 331 static const struct si_dte_data dte_data_malta = 332 { 333 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 334 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 335 5, 336 45000, 337 100, 338 0xA, 339 1, 340 0, 341 0x10, 342 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 343 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 344 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 345 90, 346 true 347 }; 348 349 struct si_cac_config_reg cac_weights_pitcairn[] = 350 { 351 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 352 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 355 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 356 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 357 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 358 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 359 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 361 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 362 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 363 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 364 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 365 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 366 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 367 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 368 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 369 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 370 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 371 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 372 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 373 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 374 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 377 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 378 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 382 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 384 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 386 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 387 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 388 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 390 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 408 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 409 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 410 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 411 { 0xFFFFFFFF } 412 }; 413 414 static const struct si_cac_config_reg lcac_pitcairn[] = 415 { 416 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 417 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 419 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 421 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 423 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 425 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 427 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 429 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 431 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 433 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 435 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 437 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 439 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 441 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 443 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 445 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 447 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 449 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 451 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 453 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 455 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 457 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 459 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 461 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 471 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 473 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 475 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 485 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 487 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 489 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 497 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 499 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 500 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 501 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 502 { 0xFFFFFFFF } 503 }; 504 505 static const struct si_cac_config_reg cac_override_pitcairn[] = 506 { 507 { 0xFFFFFFFF } 508 }; 509 510 static const struct si_powertune_data powertune_data_pitcairn = 511 { 512 ((1 << 16) | 27027), 513 5, 514 0, 515 6, 516 100, 517 { 518 51600000UL, 519 1800000UL, 520 7194395UL, 521 309631529UL, 522 -1270850L, 523 4513710L, 524 100 525 }, 526 117830498UL, 527 12, 528 { 529 0, 530 0, 531 0, 532 0, 533 0, 534 0, 535 0, 536 0 537 }, 538 true 539 }; 540 541 static const struct si_dte_data dte_data_pitcairn = 542 { 543 { 0, 0, 0, 0, 0 }, 544 { 0, 0, 0, 0, 0 }, 545 0, 546 0, 547 0, 548 0, 549 0, 550 0, 551 0, 552 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 553 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 554 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 555 0, 556 false 557 }; 558 559 static const struct si_dte_data dte_data_curacao_xt = 560 { 561 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 562 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 563 5, 564 45000, 565 100, 566 0xA, 567 1, 568 0, 569 0x10, 570 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 571 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 572 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 573 90, 574 true 575 }; 576 577 static const struct si_dte_data dte_data_curacao_pro = 578 { 579 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 580 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 581 5, 582 45000, 583 100, 584 0xA, 585 1, 586 0, 587 0x10, 588 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 589 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 590 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 591 90, 592 true 593 }; 594 595 static const struct si_dte_data dte_data_neptune_xt = 596 { 597 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 598 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 599 5, 600 45000, 601 100, 602 0xA, 603 1, 604 0, 605 0x10, 606 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 607 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 608 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 609 90, 610 true 611 }; 612 613 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 614 { 615 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 616 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 618 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 619 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 620 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 621 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 622 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 623 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 624 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 625 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 626 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 627 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 628 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 629 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 630 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 631 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 632 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 633 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 634 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 635 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 636 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 637 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 638 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 639 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 640 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 642 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 643 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 644 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 645 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 646 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 647 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 648 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 649 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 650 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 651 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 653 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 655 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 656 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 672 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 673 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 674 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 675 { 0xFFFFFFFF } 676 }; 677 678 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 679 { 680 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 681 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 683 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 684 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 685 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 686 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 687 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 688 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 689 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 690 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 691 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 692 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 693 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 694 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 695 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 696 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 697 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 698 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 699 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 700 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 701 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 702 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 703 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 704 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 705 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 707 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 708 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 709 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 710 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 711 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 712 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 713 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 714 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 715 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 718 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 720 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 721 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 737 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 738 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 739 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 740 { 0xFFFFFFFF } 741 }; 742 743 static const struct si_cac_config_reg cac_weights_heathrow[] = 744 { 745 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 746 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 748 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 749 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 750 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 751 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 752 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 753 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 754 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 755 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 756 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 757 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 758 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 759 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 760 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 761 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 762 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 763 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 764 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 765 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 766 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 767 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 768 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 769 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 770 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 772 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 774 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 775 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 776 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 777 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 778 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 779 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 780 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 781 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 783 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 785 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 786 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 802 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 803 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 804 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 805 { 0xFFFFFFFF } 806 }; 807 808 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 809 { 810 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 811 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 813 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 814 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 815 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 816 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 817 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 818 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 819 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 820 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 821 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 822 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 823 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 824 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 825 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 826 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 827 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 828 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 829 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 830 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 831 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 832 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 833 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 834 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 835 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 837 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 839 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 840 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 841 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 842 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 843 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 844 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 845 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 846 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 848 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 850 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 851 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 867 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 868 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 869 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 870 { 0xFFFFFFFF } 871 }; 872 873 static const struct si_cac_config_reg cac_weights_cape_verde[] = 874 { 875 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 876 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 878 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 879 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 880 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 881 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 882 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 883 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 884 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 885 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 886 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 887 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 888 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 889 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 890 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 891 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 892 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 893 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 894 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 895 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 896 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 897 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 898 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 899 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 900 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 902 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 904 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 905 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 906 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 907 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 908 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 909 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 910 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 911 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 913 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 915 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 916 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 932 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 933 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 934 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 935 { 0xFFFFFFFF } 936 }; 937 938 static const struct si_cac_config_reg lcac_cape_verde[] = 939 { 940 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 941 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 943 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 945 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 949 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 953 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 955 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 957 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 959 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 977 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 981 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 985 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 992 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 993 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 994 { 0xFFFFFFFF } 995 }; 996 997 static const struct si_cac_config_reg cac_override_cape_verde[] = 998 { 999 { 0xFFFFFFFF } 1000 }; 1001 1002 static const struct si_powertune_data powertune_data_cape_verde = 1003 { 1004 ((1 << 16) | 0x6993), 1005 5, 1006 0, 1007 7, 1008 105, 1009 { 1010 0UL, 1011 0UL, 1012 7194395UL, 1013 309631529UL, 1014 -1270850L, 1015 4513710L, 1016 100 1017 }, 1018 117830498UL, 1019 12, 1020 { 1021 0, 1022 0, 1023 0, 1024 0, 1025 0, 1026 0, 1027 0, 1028 0 1029 }, 1030 true 1031 }; 1032 1033 static const struct si_dte_data dte_data_cape_verde = 1034 { 1035 { 0, 0, 0, 0, 0 }, 1036 { 0, 0, 0, 0, 0 }, 1037 0, 1038 0, 1039 0, 1040 0, 1041 0, 1042 0, 1043 0, 1044 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1045 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1046 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1047 0, 1048 false 1049 }; 1050 1051 static const struct si_dte_data dte_data_venus_xtx = 1052 { 1053 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1054 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1055 5, 1056 55000, 1057 0x69, 1058 0xA, 1059 1, 1060 0, 1061 0x3, 1062 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1063 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1064 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1065 90, 1066 true 1067 }; 1068 1069 static const struct si_dte_data dte_data_venus_xt = 1070 { 1071 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1072 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1073 5, 1074 55000, 1075 0x69, 1076 0xA, 1077 1, 1078 0, 1079 0x3, 1080 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1081 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1082 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1083 90, 1084 true 1085 }; 1086 1087 static const struct si_dte_data dte_data_venus_pro = 1088 { 1089 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1090 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1091 5, 1092 55000, 1093 0x69, 1094 0xA, 1095 1, 1096 0, 1097 0x3, 1098 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1099 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1100 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1101 90, 1102 true 1103 }; 1104 1105 struct si_cac_config_reg cac_weights_oland[] = 1106 { 1107 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1123 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1124 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1125 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1132 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1134 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1164 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1165 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1166 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1167 { 0xFFFFFFFF } 1168 }; 1169 1170 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1171 { 1172 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1188 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1189 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1190 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1197 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1198 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1199 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xFFFFFFFF } 1233 }; 1234 1235 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1236 { 1237 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1262 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1263 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1264 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xFFFFFFFF } 1298 }; 1299 1300 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1301 { 1302 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1327 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1328 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1329 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xFFFFFFFF } 1363 }; 1364 1365 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1366 { 1367 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1392 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1393 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1394 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1424 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1425 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1426 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xFFFFFFFF } 1428 }; 1429 1430 static const struct si_cac_config_reg lcac_oland[] = 1431 { 1432 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1474 { 0xFFFFFFFF } 1475 }; 1476 1477 static const struct si_cac_config_reg lcac_mars_pro[] = 1478 { 1479 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1521 { 0xFFFFFFFF } 1522 }; 1523 1524 static const struct si_cac_config_reg cac_override_oland[] = 1525 { 1526 { 0xFFFFFFFF } 1527 }; 1528 1529 static const struct si_powertune_data powertune_data_oland = 1530 { 1531 ((1 << 16) | 0x6993), 1532 5, 1533 0, 1534 7, 1535 105, 1536 { 1537 0UL, 1538 0UL, 1539 7194395UL, 1540 309631529UL, 1541 -1270850L, 1542 4513710L, 1543 100 1544 }, 1545 117830498UL, 1546 12, 1547 { 1548 0, 1549 0, 1550 0, 1551 0, 1552 0, 1553 0, 1554 0, 1555 0 1556 }, 1557 true 1558 }; 1559 1560 static const struct si_powertune_data powertune_data_mars_pro = 1561 { 1562 ((1 << 16) | 0x6993), 1563 5, 1564 0, 1565 7, 1566 105, 1567 { 1568 0UL, 1569 0UL, 1570 7194395UL, 1571 309631529UL, 1572 -1270850L, 1573 4513710L, 1574 100 1575 }, 1576 117830498UL, 1577 12, 1578 { 1579 0, 1580 0, 1581 0, 1582 0, 1583 0, 1584 0, 1585 0, 1586 0 1587 }, 1588 true 1589 }; 1590 1591 static const struct si_dte_data dte_data_oland = 1592 { 1593 { 0, 0, 0, 0, 0 }, 1594 { 0, 0, 0, 0, 0 }, 1595 0, 1596 0, 1597 0, 1598 0, 1599 0, 1600 0, 1601 0, 1602 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1603 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1604 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1605 0, 1606 false 1607 }; 1608 1609 static const struct si_dte_data dte_data_mars_pro = 1610 { 1611 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1612 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1613 5, 1614 55000, 1615 105, 1616 0xA, 1617 1, 1618 0, 1619 0x10, 1620 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1621 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1622 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1623 90, 1624 true 1625 }; 1626 1627 static const struct si_dte_data dte_data_sun_xt = 1628 { 1629 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1630 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1631 5, 1632 55000, 1633 105, 1634 0xA, 1635 1, 1636 0, 1637 0x10, 1638 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1639 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1640 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1641 90, 1642 true 1643 }; 1644 1645 1646 static const struct si_cac_config_reg cac_weights_hainan[] = 1647 { 1648 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1664 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1665 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1666 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1674 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1675 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1705 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1706 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1707 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1708 { 0xFFFFFFFF } 1709 }; 1710 1711 static const struct si_powertune_data powertune_data_hainan = 1712 { 1713 ((1 << 16) | 0x6993), 1714 5, 1715 0, 1716 9, 1717 105, 1718 { 1719 0UL, 1720 0UL, 1721 7194395UL, 1722 309631529UL, 1723 -1270850L, 1724 4513710L, 1725 100 1726 }, 1727 117830498UL, 1728 12, 1729 { 1730 0, 1731 0, 1732 0, 1733 0, 1734 0, 1735 0, 1736 0, 1737 0 1738 }, 1739 true 1740 }; 1741 1742 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1743 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1744 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1745 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1746 1747 extern int si_mc_load_microcode(struct radeon_device *rdev); 1748 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1749 1750 static int si_populate_voltage_value(struct radeon_device *rdev, 1751 const struct atom_voltage_table *table, 1752 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1753 static int si_get_std_voltage_value(struct radeon_device *rdev, 1754 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1755 u16 *std_voltage); 1756 static int si_write_smc_soft_register(struct radeon_device *rdev, 1757 u16 reg_offset, u32 value); 1758 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1759 struct rv7xx_pl *pl, 1760 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1761 static int si_calculate_sclk_params(struct radeon_device *rdev, 1762 u32 engine_clock, 1763 SISLANDS_SMC_SCLK_VALUE *sclk); 1764 1765 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1766 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1767 1768 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1769 { 1770 struct si_power_info *pi = rdev->pm.dpm.priv; 1771 1772 return pi; 1773 } 1774 1775 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1776 u16 v, s32 t, u32 ileakage, u32 *leakage) 1777 { 1778 s64 kt, kv, leakage_w, i_leakage, vddc; 1779 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1780 s64 tmp; 1781 1782 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1783 vddc = div64_s64(drm_int2fixp(v), 1000); 1784 temperature = div64_s64(drm_int2fixp(t), 1000); 1785 1786 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1787 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1788 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1789 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1790 t_ref = drm_int2fixp(coeff->t_ref); 1791 1792 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1793 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1794 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1795 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1796 1797 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1798 1799 *leakage = drm_fixp2int(leakage_w * 1000); 1800 } 1801 1802 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1803 const struct ni_leakage_coeffients *coeff, 1804 u16 v, 1805 s32 t, 1806 u32 i_leakage, 1807 u32 *leakage) 1808 { 1809 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1810 } 1811 1812 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1813 const u32 fixed_kt, u16 v, 1814 u32 ileakage, u32 *leakage) 1815 { 1816 s64 kt, kv, leakage_w, i_leakage, vddc; 1817 1818 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1819 vddc = div64_s64(drm_int2fixp(v), 1000); 1820 1821 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1822 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1823 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1824 1825 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1826 1827 *leakage = drm_fixp2int(leakage_w * 1000); 1828 } 1829 1830 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1831 const struct ni_leakage_coeffients *coeff, 1832 const u32 fixed_kt, 1833 u16 v, 1834 u32 i_leakage, 1835 u32 *leakage) 1836 { 1837 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1838 } 1839 1840 1841 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1842 struct si_dte_data *dte_data) 1843 { 1844 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1845 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1846 u32 k = dte_data->k; 1847 u32 t_max = dte_data->max_t; 1848 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1849 u32 t_0 = dte_data->t0; 1850 u32 i; 1851 1852 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1853 dte_data->tdep_count = 3; 1854 1855 for (i = 0; i < k; i++) { 1856 dte_data->r[i] = 1857 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1858 (p_limit2 * (u32)100); 1859 } 1860 1861 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1862 1863 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1864 dte_data->tdep_r[i] = dte_data->r[4]; 1865 } 1866 } else { 1867 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1868 } 1869 } 1870 1871 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1872 { 1873 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1874 struct si_power_info *si_pi = si_get_pi(rdev); 1875 bool update_dte_from_pl2 = false; 1876 1877 if (rdev->family == CHIP_TAHITI) { 1878 si_pi->cac_weights = cac_weights_tahiti; 1879 si_pi->lcac_config = lcac_tahiti; 1880 si_pi->cac_override = cac_override_tahiti; 1881 si_pi->powertune_data = &powertune_data_tahiti; 1882 si_pi->dte_data = dte_data_tahiti; 1883 1884 switch (rdev->pdev->device) { 1885 case 0x6798: 1886 si_pi->dte_data.enable_dte_by_default = true; 1887 break; 1888 case 0x6799: 1889 si_pi->dte_data = dte_data_new_zealand; 1890 break; 1891 case 0x6790: 1892 case 0x6791: 1893 case 0x6792: 1894 case 0x679E: 1895 si_pi->dte_data = dte_data_aruba_pro; 1896 update_dte_from_pl2 = true; 1897 break; 1898 case 0x679B: 1899 si_pi->dte_data = dte_data_malta; 1900 update_dte_from_pl2 = true; 1901 break; 1902 case 0x679A: 1903 si_pi->dte_data = dte_data_tahiti_pro; 1904 update_dte_from_pl2 = true; 1905 break; 1906 default: 1907 if (si_pi->dte_data.enable_dte_by_default == true) 1908 DRM_ERROR("DTE is not enabled!\n"); 1909 break; 1910 } 1911 } else if (rdev->family == CHIP_PITCAIRN) { 1912 switch (rdev->pdev->device) { 1913 case 0x6810: 1914 case 0x6818: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_xt; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6819: 1923 case 0x6811: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_curacao_pro; 1929 update_dte_from_pl2 = true; 1930 break; 1931 case 0x6800: 1932 case 0x6806: 1933 si_pi->cac_weights = cac_weights_pitcairn; 1934 si_pi->lcac_config = lcac_pitcairn; 1935 si_pi->cac_override = cac_override_pitcairn; 1936 si_pi->powertune_data = &powertune_data_pitcairn; 1937 si_pi->dte_data = dte_data_neptune_xt; 1938 update_dte_from_pl2 = true; 1939 break; 1940 default: 1941 si_pi->cac_weights = cac_weights_pitcairn; 1942 si_pi->lcac_config = lcac_pitcairn; 1943 si_pi->cac_override = cac_override_pitcairn; 1944 si_pi->powertune_data = &powertune_data_pitcairn; 1945 si_pi->dte_data = dte_data_pitcairn; 1946 break; 1947 } 1948 } else if (rdev->family == CHIP_VERDE) { 1949 si_pi->lcac_config = lcac_cape_verde; 1950 si_pi->cac_override = cac_override_cape_verde; 1951 si_pi->powertune_data = &powertune_data_cape_verde; 1952 1953 switch (rdev->pdev->device) { 1954 case 0x683B: 1955 case 0x683F: 1956 case 0x6829: 1957 case 0x6835: 1958 si_pi->cac_weights = cac_weights_cape_verde_pro; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x682C: 1962 si_pi->cac_weights = cac_weights_cape_verde_pro; 1963 si_pi->dte_data = dte_data_sun_xt; 1964 break; 1965 case 0x6825: 1966 case 0x6827: 1967 si_pi->cac_weights = cac_weights_heathrow; 1968 si_pi->dte_data = dte_data_cape_verde; 1969 break; 1970 case 0x6824: 1971 case 0x682D: 1972 si_pi->cac_weights = cac_weights_chelsea_xt; 1973 si_pi->dte_data = dte_data_cape_verde; 1974 break; 1975 case 0x682F: 1976 si_pi->cac_weights = cac_weights_chelsea_pro; 1977 si_pi->dte_data = dte_data_cape_verde; 1978 break; 1979 case 0x6820: 1980 si_pi->cac_weights = cac_weights_heathrow; 1981 si_pi->dte_data = dte_data_venus_xtx; 1982 break; 1983 case 0x6821: 1984 si_pi->cac_weights = cac_weights_heathrow; 1985 si_pi->dte_data = dte_data_venus_xt; 1986 break; 1987 case 0x6823: 1988 case 0x682B: 1989 case 0x6822: 1990 case 0x682A: 1991 si_pi->cac_weights = cac_weights_chelsea_pro; 1992 si_pi->dte_data = dte_data_venus_pro; 1993 break; 1994 default: 1995 si_pi->cac_weights = cac_weights_cape_verde; 1996 si_pi->dte_data = dte_data_cape_verde; 1997 break; 1998 } 1999 } else if (rdev->family == CHIP_OLAND) { 2000 switch (rdev->pdev->device) { 2001 case 0x6601: 2002 case 0x6621: 2003 case 0x6603: 2004 case 0x6605: 2005 si_pi->cac_weights = cac_weights_mars_pro; 2006 si_pi->lcac_config = lcac_mars_pro; 2007 si_pi->cac_override = cac_override_oland; 2008 si_pi->powertune_data = &powertune_data_mars_pro; 2009 si_pi->dte_data = dte_data_mars_pro; 2010 update_dte_from_pl2 = true; 2011 break; 2012 case 0x6600: 2013 case 0x6606: 2014 case 0x6620: 2015 case 0x6604: 2016 si_pi->cac_weights = cac_weights_mars_xt; 2017 si_pi->lcac_config = lcac_mars_pro; 2018 si_pi->cac_override = cac_override_oland; 2019 si_pi->powertune_data = &powertune_data_mars_pro; 2020 si_pi->dte_data = dte_data_mars_pro; 2021 update_dte_from_pl2 = true; 2022 break; 2023 case 0x6611: 2024 case 0x6613: 2025 case 0x6608: 2026 si_pi->cac_weights = cac_weights_oland_pro; 2027 si_pi->lcac_config = lcac_mars_pro; 2028 si_pi->cac_override = cac_override_oland; 2029 si_pi->powertune_data = &powertune_data_mars_pro; 2030 si_pi->dte_data = dte_data_mars_pro; 2031 update_dte_from_pl2 = true; 2032 break; 2033 case 0x6610: 2034 si_pi->cac_weights = cac_weights_oland_xt; 2035 si_pi->lcac_config = lcac_mars_pro; 2036 si_pi->cac_override = cac_override_oland; 2037 si_pi->powertune_data = &powertune_data_mars_pro; 2038 si_pi->dte_data = dte_data_mars_pro; 2039 update_dte_from_pl2 = true; 2040 break; 2041 default: 2042 si_pi->cac_weights = cac_weights_oland; 2043 si_pi->lcac_config = lcac_oland; 2044 si_pi->cac_override = cac_override_oland; 2045 si_pi->powertune_data = &powertune_data_oland; 2046 si_pi->dte_data = dte_data_oland; 2047 break; 2048 } 2049 } else if (rdev->family == CHIP_HAINAN) { 2050 si_pi->cac_weights = cac_weights_hainan; 2051 si_pi->lcac_config = lcac_oland; 2052 si_pi->cac_override = cac_override_oland; 2053 si_pi->powertune_data = &powertune_data_hainan; 2054 si_pi->dte_data = dte_data_sun_xt; 2055 update_dte_from_pl2 = true; 2056 } else { 2057 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2058 return; 2059 } 2060 2061 ni_pi->enable_power_containment = false; 2062 ni_pi->enable_cac = false; 2063 ni_pi->enable_sq_ramping = false; 2064 si_pi->enable_dte = false; 2065 2066 if (si_pi->powertune_data->enable_powertune_by_default) { 2067 ni_pi->enable_power_containment= true; 2068 ni_pi->enable_cac = true; 2069 if (si_pi->dte_data.enable_dte_by_default) { 2070 si_pi->enable_dte = true; 2071 if (update_dte_from_pl2) 2072 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2073 2074 } 2075 ni_pi->enable_sq_ramping = true; 2076 } 2077 2078 ni_pi->driver_calculate_cac_leakage = true; 2079 ni_pi->cac_configuration_required = true; 2080 2081 if (ni_pi->cac_configuration_required) { 2082 ni_pi->support_cac_long_term_average = true; 2083 si_pi->dyn_powertune_data.l2_lta_window_size = 2084 si_pi->powertune_data->l2_lta_window_size_default; 2085 si_pi->dyn_powertune_data.lts_truncate = 2086 si_pi->powertune_data->lts_truncate_default; 2087 } else { 2088 ni_pi->support_cac_long_term_average = false; 2089 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2090 si_pi->dyn_powertune_data.lts_truncate = 0; 2091 } 2092 2093 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2094 } 2095 2096 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2097 { 2098 return 1; 2099 } 2100 2101 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2102 { 2103 u32 xclk; 2104 u32 wintime; 2105 u32 cac_window; 2106 u32 cac_window_size; 2107 2108 xclk = radeon_get_xclk(rdev); 2109 2110 if (xclk == 0) 2111 return 0; 2112 2113 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2114 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2115 2116 wintime = (cac_window_size * 100) / xclk; 2117 2118 return wintime; 2119 } 2120 2121 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2122 { 2123 return power_in_watts; 2124 } 2125 2126 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2127 bool adjust_polarity, 2128 u32 tdp_adjustment, 2129 u32 *tdp_limit, 2130 u32 *near_tdp_limit) 2131 { 2132 u32 adjustment_delta, max_tdp_limit; 2133 2134 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2135 return -EINVAL; 2136 2137 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2138 2139 if (adjust_polarity) { 2140 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2142 } else { 2143 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2144 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2145 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2146 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2147 else 2148 *near_tdp_limit = 0; 2149 } 2150 2151 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2152 return -EINVAL; 2153 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2154 return -EINVAL; 2155 2156 return 0; 2157 } 2158 2159 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2160 struct radeon_ps *radeon_state) 2161 { 2162 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2163 struct si_power_info *si_pi = si_get_pi(rdev); 2164 2165 if (ni_pi->enable_power_containment) { 2166 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2167 PP_SIslands_PAPMParameters *papm_parm; 2168 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2169 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2170 u32 tdp_limit; 2171 u32 near_tdp_limit; 2172 int ret; 2173 2174 if (scaling_factor == 0) 2175 return -EINVAL; 2176 2177 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2178 2179 ret = si_calculate_adjusted_tdp_limits(rdev, 2180 false, /* ??? */ 2181 rdev->pm.dpm.tdp_adjustment, 2182 &tdp_limit, 2183 &near_tdp_limit); 2184 if (ret) 2185 return ret; 2186 2187 smc_table->dpm2Params.TDPLimit = 2188 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2189 smc_table->dpm2Params.NearTDPLimit = 2190 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2191 smc_table->dpm2Params.SafePowerLimit = 2192 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2193 2194 ret = si_copy_bytes_to_smc(rdev, 2195 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2196 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2197 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2198 sizeof(u32) * 3, 2199 si_pi->sram_end); 2200 if (ret) 2201 return ret; 2202 2203 if (si_pi->enable_ppm) { 2204 papm_parm = &si_pi->papm_parm; 2205 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2206 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2207 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2208 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2209 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2210 papm_parm->PlatformPowerLimit = 0xffffffff; 2211 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2212 2213 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2214 (u8 *)papm_parm, 2215 sizeof(PP_SIslands_PAPMParameters), 2216 si_pi->sram_end); 2217 if (ret) 2218 return ret; 2219 } 2220 } 2221 return 0; 2222 } 2223 2224 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2225 struct radeon_ps *radeon_state) 2226 { 2227 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2228 struct si_power_info *si_pi = si_get_pi(rdev); 2229 2230 if (ni_pi->enable_power_containment) { 2231 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2232 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2233 int ret; 2234 2235 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2236 2237 smc_table->dpm2Params.NearTDPLimit = 2238 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2239 smc_table->dpm2Params.SafePowerLimit = 2240 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2241 2242 ret = si_copy_bytes_to_smc(rdev, 2243 (si_pi->state_table_start + 2244 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2245 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2246 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2247 sizeof(u32) * 2, 2248 si_pi->sram_end); 2249 if (ret) 2250 return ret; 2251 } 2252 2253 return 0; 2254 } 2255 2256 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2257 const u16 prev_std_vddc, 2258 const u16 curr_std_vddc) 2259 { 2260 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2261 u64 prev_vddc = (u64)prev_std_vddc; 2262 u64 curr_vddc = (u64)curr_std_vddc; 2263 u64 pwr_efficiency_ratio, n, d; 2264 2265 if ((prev_vddc == 0) || (curr_vddc == 0)) 2266 return 0; 2267 2268 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2269 d = prev_vddc * prev_vddc; 2270 pwr_efficiency_ratio = div64_u64(n, d); 2271 2272 if (pwr_efficiency_ratio > (u64)0xFFFF) 2273 return 0; 2274 2275 return (u16)pwr_efficiency_ratio; 2276 } 2277 2278 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2279 struct radeon_ps *radeon_state) 2280 { 2281 struct si_power_info *si_pi = si_get_pi(rdev); 2282 2283 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2284 radeon_state->vclk && radeon_state->dclk) 2285 return true; 2286 2287 return false; 2288 } 2289 2290 static int si_populate_power_containment_values(struct radeon_device *rdev, 2291 struct radeon_ps *radeon_state, 2292 SISLANDS_SMC_SWSTATE *smc_state) 2293 { 2294 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2295 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2296 struct ni_ps *state = ni_get_ps(radeon_state); 2297 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2298 u32 prev_sclk; 2299 u32 max_sclk; 2300 u32 min_sclk; 2301 u16 prev_std_vddc; 2302 u16 curr_std_vddc; 2303 int i; 2304 u16 pwr_efficiency_ratio; 2305 u8 max_ps_percent; 2306 bool disable_uvd_power_tune; 2307 int ret; 2308 2309 if (ni_pi->enable_power_containment == false) 2310 return 0; 2311 2312 if (state->performance_level_count == 0) 2313 return -EINVAL; 2314 2315 if (smc_state->levelCount != state->performance_level_count) 2316 return -EINVAL; 2317 2318 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2319 2320 smc_state->levels[0].dpm2.MaxPS = 0; 2321 smc_state->levels[0].dpm2.NearTDPDec = 0; 2322 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2323 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2324 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2325 2326 for (i = 1; i < state->performance_level_count; i++) { 2327 prev_sclk = state->performance_levels[i-1].sclk; 2328 max_sclk = state->performance_levels[i].sclk; 2329 if (i == 1) 2330 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2331 else 2332 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2333 2334 if (prev_sclk > max_sclk) 2335 return -EINVAL; 2336 2337 if ((max_ps_percent == 0) || 2338 (prev_sclk == max_sclk) || 2339 disable_uvd_power_tune) { 2340 min_sclk = max_sclk; 2341 } else if (i == 1) { 2342 min_sclk = prev_sclk; 2343 } else { 2344 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2345 } 2346 2347 if (min_sclk < state->performance_levels[0].sclk) 2348 min_sclk = state->performance_levels[0].sclk; 2349 2350 if (min_sclk == 0) 2351 return -EINVAL; 2352 2353 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2354 state->performance_levels[i-1].vddc, &vddc); 2355 if (ret) 2356 return ret; 2357 2358 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2359 if (ret) 2360 return ret; 2361 2362 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2363 state->performance_levels[i].vddc, &vddc); 2364 if (ret) 2365 return ret; 2366 2367 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2368 if (ret) 2369 return ret; 2370 2371 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2372 prev_std_vddc, curr_std_vddc); 2373 2374 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2375 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2376 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2377 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2378 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2385 struct radeon_ps *radeon_state, 2386 SISLANDS_SMC_SWSTATE *smc_state) 2387 { 2388 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2389 struct ni_ps *state = ni_get_ps(radeon_state); 2390 u32 sq_power_throttle, sq_power_throttle2; 2391 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2392 int i; 2393 2394 if (state->performance_level_count == 0) 2395 return -EINVAL; 2396 2397 if (smc_state->levelCount != state->performance_level_count) 2398 return -EINVAL; 2399 2400 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2401 return -EINVAL; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2410 enable_sq_ramping = false; 2411 2412 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2413 enable_sq_ramping = false; 2414 2415 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2416 enable_sq_ramping = false; 2417 2418 for (i = 0; i < state->performance_level_count; i++) { 2419 sq_power_throttle = 0; 2420 sq_power_throttle2 = 0; 2421 2422 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2423 enable_sq_ramping) { 2424 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2425 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2426 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2427 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2428 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2429 } else { 2430 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2431 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2432 } 2433 2434 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2435 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2436 } 2437 2438 return 0; 2439 } 2440 2441 static int si_enable_power_containment(struct radeon_device *rdev, 2442 struct radeon_ps *radeon_new_state, 2443 bool enable) 2444 { 2445 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2446 PPSMC_Result smc_result; 2447 int ret = 0; 2448 2449 if (ni_pi->enable_power_containment) { 2450 if (enable) { 2451 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2452 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2453 if (smc_result != PPSMC_Result_OK) { 2454 ret = -EINVAL; 2455 ni_pi->pc_enabled = false; 2456 } else { 2457 ni_pi->pc_enabled = true; 2458 } 2459 } 2460 } else { 2461 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2462 if (smc_result != PPSMC_Result_OK) 2463 ret = -EINVAL; 2464 ni_pi->pc_enabled = false; 2465 } 2466 } 2467 2468 return ret; 2469 } 2470 2471 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2472 { 2473 struct si_power_info *si_pi = si_get_pi(rdev); 2474 int ret = 0; 2475 struct si_dte_data *dte_data = &si_pi->dte_data; 2476 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2477 u32 table_size; 2478 u8 tdep_count; 2479 u32 i; 2480 2481 if (dte_data == NULL) 2482 si_pi->enable_dte = false; 2483 2484 if (si_pi->enable_dte == false) 2485 return 0; 2486 2487 if (dte_data->k <= 0) 2488 return -EINVAL; 2489 2490 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2491 if (dte_tables == NULL) { 2492 si_pi->enable_dte = false; 2493 return -ENOMEM; 2494 } 2495 2496 table_size = dte_data->k; 2497 2498 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2499 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2500 2501 tdep_count = dte_data->tdep_count; 2502 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2503 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2504 2505 dte_tables->K = cpu_to_be32(table_size); 2506 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2507 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2508 dte_tables->WindowSize = dte_data->window_size; 2509 dte_tables->temp_select = dte_data->temp_select; 2510 dte_tables->DTE_mode = dte_data->dte_mode; 2511 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2512 2513 if (tdep_count > 0) 2514 table_size--; 2515 2516 for (i = 0; i < table_size; i++) { 2517 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2518 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2519 } 2520 2521 dte_tables->Tdep_count = tdep_count; 2522 2523 for (i = 0; i < (u32)tdep_count; i++) { 2524 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2525 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2526 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2527 } 2528 2529 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2530 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2531 kfree(dte_tables); 2532 2533 return ret; 2534 } 2535 2536 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2537 u16 *max, u16 *min) 2538 { 2539 struct si_power_info *si_pi = si_get_pi(rdev); 2540 struct radeon_cac_leakage_table *table = 2541 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2542 u32 i; 2543 u32 v0_loadline; 2544 2545 2546 if (table == NULL) 2547 return -EINVAL; 2548 2549 *max = 0; 2550 *min = 0xFFFF; 2551 2552 for (i = 0; i < table->count; i++) { 2553 if (table->entries[i].vddc > *max) 2554 *max = table->entries[i].vddc; 2555 if (table->entries[i].vddc < *min) 2556 *min = table->entries[i].vddc; 2557 } 2558 2559 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2560 return -EINVAL; 2561 2562 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2563 2564 if (v0_loadline > 0xFFFFUL) 2565 return -EINVAL; 2566 2567 *min = (u16)v0_loadline; 2568 2569 if ((*min > *max) || (*max == 0) || (*min == 0)) 2570 return -EINVAL; 2571 2572 return 0; 2573 } 2574 2575 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2576 { 2577 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2578 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2579 } 2580 2581 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2582 PP_SIslands_CacConfig *cac_tables, 2583 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2584 u16 t0, u16 t_step) 2585 { 2586 struct si_power_info *si_pi = si_get_pi(rdev); 2587 u32 leakage; 2588 unsigned int i, j; 2589 s32 t; 2590 u32 smc_leakage; 2591 u32 scaling_factor; 2592 u16 voltage; 2593 2594 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2595 2596 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2597 t = (1000 * (i * t_step + t0)); 2598 2599 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2600 voltage = vddc_max - (vddc_step * j); 2601 2602 si_calculate_leakage_for_v_and_t(rdev, 2603 &si_pi->powertune_data->leakage_coefficients, 2604 voltage, 2605 t, 2606 si_pi->dyn_powertune_data.cac_leakage, 2607 &leakage); 2608 2609 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2610 2611 if (smc_leakage > 0xFFFF) 2612 smc_leakage = 0xFFFF; 2613 2614 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2615 cpu_to_be16((u16)smc_leakage); 2616 } 2617 } 2618 return 0; 2619 } 2620 2621 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2622 PP_SIslands_CacConfig *cac_tables, 2623 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2624 { 2625 struct si_power_info *si_pi = si_get_pi(rdev); 2626 u32 leakage; 2627 unsigned int i, j; 2628 u32 smc_leakage; 2629 u32 scaling_factor; 2630 u16 voltage; 2631 2632 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2633 2634 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2635 voltage = vddc_max - (vddc_step * j); 2636 2637 si_calculate_leakage_for_v(rdev, 2638 &si_pi->powertune_data->leakage_coefficients, 2639 si_pi->powertune_data->fixed_kt, 2640 voltage, 2641 si_pi->dyn_powertune_data.cac_leakage, 2642 &leakage); 2643 2644 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2645 2646 if (smc_leakage > 0xFFFF) 2647 smc_leakage = 0xFFFF; 2648 2649 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2650 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2651 cpu_to_be16((u16)smc_leakage); 2652 } 2653 return 0; 2654 } 2655 2656 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2657 { 2658 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2659 struct si_power_info *si_pi = si_get_pi(rdev); 2660 PP_SIslands_CacConfig *cac_tables = NULL; 2661 u16 vddc_max, vddc_min, vddc_step; 2662 u16 t0, t_step; 2663 u32 load_line_slope, reg; 2664 int ret = 0; 2665 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2666 2667 if (ni_pi->enable_cac == false) 2668 return 0; 2669 2670 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2671 if (!cac_tables) 2672 return -ENOMEM; 2673 2674 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2675 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2676 WREG32(CG_CAC_CTRL, reg); 2677 2678 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2679 si_pi->dyn_powertune_data.dc_pwr_value = 2680 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2681 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2682 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2683 2684 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2685 2686 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2687 if (ret) 2688 goto done_free; 2689 2690 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2691 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2692 t_step = 4; 2693 t0 = 60; 2694 2695 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2696 ret = si_init_dte_leakage_table(rdev, cac_tables, 2697 vddc_max, vddc_min, vddc_step, 2698 t0, t_step); 2699 else 2700 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2701 vddc_max, vddc_min, vddc_step); 2702 if (ret) 2703 goto done_free; 2704 2705 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2706 2707 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2708 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2709 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2710 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2711 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2712 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2713 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2714 cac_tables->calculation_repeats = cpu_to_be32(2); 2715 cac_tables->dc_cac = cpu_to_be32(0); 2716 cac_tables->log2_PG_LKG_SCALE = 12; 2717 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2718 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2719 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2720 2721 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2722 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2723 2724 if (ret) 2725 goto done_free; 2726 2727 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2728 2729 done_free: 2730 if (ret) { 2731 ni_pi->enable_cac = false; 2732 ni_pi->enable_power_containment = false; 2733 } 2734 2735 kfree(cac_tables); 2736 2737 return 0; 2738 } 2739 2740 static int si_program_cac_config_registers(struct radeon_device *rdev, 2741 const struct si_cac_config_reg *cac_config_regs) 2742 { 2743 const struct si_cac_config_reg *config_regs = cac_config_regs; 2744 u32 data = 0, offset; 2745 2746 if (!config_regs) 2747 return -EINVAL; 2748 2749 while (config_regs->offset != 0xFFFFFFFF) { 2750 switch (config_regs->type) { 2751 case SISLANDS_CACCONFIG_CGIND: 2752 offset = SMC_CG_IND_START + config_regs->offset; 2753 if (offset < SMC_CG_IND_END) 2754 data = RREG32_SMC(offset); 2755 break; 2756 default: 2757 data = RREG32(config_regs->offset << 2); 2758 break; 2759 } 2760 2761 data &= ~config_regs->mask; 2762 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2763 2764 switch (config_regs->type) { 2765 case SISLANDS_CACCONFIG_CGIND: 2766 offset = SMC_CG_IND_START + config_regs->offset; 2767 if (offset < SMC_CG_IND_END) 2768 WREG32_SMC(offset, data); 2769 break; 2770 default: 2771 WREG32(config_regs->offset << 2, data); 2772 break; 2773 } 2774 config_regs++; 2775 } 2776 return 0; 2777 } 2778 2779 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2780 { 2781 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2782 struct si_power_info *si_pi = si_get_pi(rdev); 2783 int ret; 2784 2785 if ((ni_pi->enable_cac == false) || 2786 (ni_pi->cac_configuration_required == false)) 2787 return 0; 2788 2789 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2790 if (ret) 2791 return ret; 2792 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2793 if (ret) 2794 return ret; 2795 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2796 if (ret) 2797 return ret; 2798 2799 return 0; 2800 } 2801 2802 static int si_enable_smc_cac(struct radeon_device *rdev, 2803 struct radeon_ps *radeon_new_state, 2804 bool enable) 2805 { 2806 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2807 struct si_power_info *si_pi = si_get_pi(rdev); 2808 PPSMC_Result smc_result; 2809 int ret = 0; 2810 2811 if (ni_pi->enable_cac) { 2812 if (enable) { 2813 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2814 if (ni_pi->support_cac_long_term_average) { 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2816 if (smc_result != PPSMC_Result_OK) 2817 ni_pi->support_cac_long_term_average = false; 2818 } 2819 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2821 if (smc_result != PPSMC_Result_OK) { 2822 ret = -EINVAL; 2823 ni_pi->cac_enabled = false; 2824 } else { 2825 ni_pi->cac_enabled = true; 2826 } 2827 2828 if (si_pi->enable_dte) { 2829 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2830 if (smc_result != PPSMC_Result_OK) 2831 ret = -EINVAL; 2832 } 2833 } 2834 } else if (ni_pi->cac_enabled) { 2835 if (si_pi->enable_dte) 2836 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2837 2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2839 2840 ni_pi->cac_enabled = false; 2841 2842 if (ni_pi->support_cac_long_term_average) 2843 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2844 } 2845 } 2846 return ret; 2847 } 2848 2849 static int si_init_smc_spll_table(struct radeon_device *rdev) 2850 { 2851 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2852 struct si_power_info *si_pi = si_get_pi(rdev); 2853 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2854 SISLANDS_SMC_SCLK_VALUE sclk_params; 2855 u32 fb_div, p_div; 2856 u32 clk_s, clk_v; 2857 u32 sclk = 0; 2858 int ret = 0; 2859 u32 tmp; 2860 int i; 2861 2862 if (si_pi->spll_table_start == 0) 2863 return -EINVAL; 2864 2865 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2866 if (spll_table == NULL) 2867 return -ENOMEM; 2868 2869 for (i = 0; i < 256; i++) { 2870 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2871 if (ret) 2872 break; 2873 2874 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2875 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2876 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2877 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2878 2879 fb_div &= ~0x00001FFF; 2880 fb_div >>= 1; 2881 clk_v >>= 6; 2882 2883 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2884 ret = -EINVAL; 2885 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2886 ret = -EINVAL; 2887 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2888 ret = -EINVAL; 2889 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2890 ret = -EINVAL; 2891 2892 if (ret) 2893 break; 2894 2895 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2896 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2897 spll_table->freq[i] = cpu_to_be32(tmp); 2898 2899 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2900 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2901 spll_table->ss[i] = cpu_to_be32(tmp); 2902 2903 sclk += 512; 2904 } 2905 2906 2907 if (!ret) 2908 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2909 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2910 si_pi->sram_end); 2911 2912 if (ret) 2913 ni_pi->enable_power_containment = false; 2914 2915 kfree(spll_table); 2916 2917 return ret; 2918 } 2919 2920 struct si_dpm_quirk { 2921 u32 chip_vendor; 2922 u32 chip_device; 2923 u32 subsys_vendor; 2924 u32 subsys_device; 2925 u32 max_sclk; 2926 u32 max_mclk; 2927 }; 2928 2929 /* cards with dpm stability problems */ 2930 static struct si_dpm_quirk si_dpm_quirk_list[] = { 2931 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2932 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2934 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, 2935 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2936 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2937 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2938 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2939 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2940 { 0, 0, 0, 0 }, 2941 }; 2942 2943 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2944 u16 vce_voltage) 2945 { 2946 u16 highest_leakage = 0; 2947 struct si_power_info *si_pi = si_get_pi(rdev); 2948 int i; 2949 2950 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2951 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2952 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2953 } 2954 2955 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2956 return highest_leakage; 2957 2958 return vce_voltage; 2959 } 2960 2961 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2962 u32 evclk, u32 ecclk, u16 *voltage) 2963 { 2964 u32 i; 2965 int ret = -EINVAL; 2966 struct radeon_vce_clock_voltage_dependency_table *table = 2967 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2968 2969 if (((evclk == 0) && (ecclk == 0)) || 2970 (table && (table->count == 0))) { 2971 *voltage = 0; 2972 return 0; 2973 } 2974 2975 for (i = 0; i < table->count; i++) { 2976 if ((evclk <= table->entries[i].evclk) && 2977 (ecclk <= table->entries[i].ecclk)) { 2978 *voltage = table->entries[i].v; 2979 ret = 0; 2980 break; 2981 } 2982 } 2983 2984 /* if no match return the highest voltage */ 2985 if (ret) 2986 *voltage = table->entries[table->count - 1].v; 2987 2988 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2989 2990 return ret; 2991 } 2992 2993 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2994 struct radeon_ps *rps) 2995 { 2996 struct ni_ps *ps = ni_get_ps(rps); 2997 struct radeon_clock_and_voltage_limits *max_limits; 2998 bool disable_mclk_switching = false; 2999 bool disable_sclk_switching = false; 3000 u32 mclk, sclk; 3001 u16 vddc, vddci, min_vce_voltage = 0; 3002 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3003 u32 max_sclk = 0, max_mclk = 0; 3004 int i; 3005 struct si_dpm_quirk *p = si_dpm_quirk_list; 3006 3007 /* limit all SI kickers */ 3008 if (rdev->family == CHIP_PITCAIRN) { 3009 if ((rdev->pdev->revision == 0x81) || 3010 (rdev->pdev->device == 0x6810) || 3011 (rdev->pdev->device == 0x6811) || 3012 (rdev->pdev->device == 0x6816) || 3013 (rdev->pdev->device == 0x6817) || 3014 (rdev->pdev->device == 0x6806)) 3015 max_mclk = 120000; 3016 } else if (rdev->family == CHIP_OLAND) { 3017 if ((rdev->pdev->revision == 0xC7) || 3018 (rdev->pdev->revision == 0x80) || 3019 (rdev->pdev->revision == 0x81) || 3020 (rdev->pdev->revision == 0x83) || 3021 (rdev->pdev->revision == 0x87) || 3022 (rdev->pdev->device == 0x6604) || 3023 (rdev->pdev->device == 0x6605)) { 3024 max_sclk = 75000; 3025 max_mclk = 80000; 3026 } 3027 } else if (rdev->family == CHIP_HAINAN) { 3028 if ((rdev->pdev->revision == 0x81) || 3029 (rdev->pdev->revision == 0x83) || 3030 (rdev->pdev->revision == 0xC3) || 3031 (rdev->pdev->device == 0x6664) || 3032 (rdev->pdev->device == 0x6665) || 3033 (rdev->pdev->device == 0x6667)) { 3034 max_sclk = 75000; 3035 max_mclk = 80000; 3036 } 3037 } else if (rdev->family == CHIP_OLAND) { 3038 if ((rdev->pdev->revision == 0xC7) || 3039 (rdev->pdev->revision == 0x80) || 3040 (rdev->pdev->revision == 0x81) || 3041 (rdev->pdev->revision == 0x83) || 3042 (rdev->pdev->revision == 0x87) || 3043 (rdev->pdev->device == 0x6604) || 3044 (rdev->pdev->device == 0x6605)) { 3045 max_sclk = 75000; 3046 } 3047 } 3048 /* Apply dpm quirks */ 3049 while (p && p->chip_device != 0) { 3050 if (rdev->pdev->vendor == p->chip_vendor && 3051 rdev->pdev->device == p->chip_device && 3052 rdev->pdev->subsystem_vendor == p->subsys_vendor && 3053 rdev->pdev->subsystem_device == p->subsys_device) { 3054 max_sclk = p->max_sclk; 3055 max_mclk = p->max_mclk; 3056 break; 3057 } 3058 ++p; 3059 } 3060 3061 if (rps->vce_active) { 3062 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3063 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3064 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3065 &min_vce_voltage); 3066 } else { 3067 rps->evclk = 0; 3068 rps->ecclk = 0; 3069 } 3070 3071 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3072 ni_dpm_vblank_too_short(rdev)) 3073 disable_mclk_switching = true; 3074 3075 if (rps->vclk || rps->dclk) { 3076 disable_mclk_switching = true; 3077 disable_sclk_switching = true; 3078 } 3079 3080 if (rdev->pm.dpm.ac_power) 3081 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3082 else 3083 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3084 3085 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3086 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3087 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3088 } 3089 if (rdev->pm.dpm.ac_power == false) { 3090 for (i = 0; i < ps->performance_level_count; i++) { 3091 if (ps->performance_levels[i].mclk > max_limits->mclk) 3092 ps->performance_levels[i].mclk = max_limits->mclk; 3093 if (ps->performance_levels[i].sclk > max_limits->sclk) 3094 ps->performance_levels[i].sclk = max_limits->sclk; 3095 if (ps->performance_levels[i].vddc > max_limits->vddc) 3096 ps->performance_levels[i].vddc = max_limits->vddc; 3097 if (ps->performance_levels[i].vddci > max_limits->vddci) 3098 ps->performance_levels[i].vddci = max_limits->vddci; 3099 } 3100 } 3101 3102 /* limit clocks to max supported clocks based on voltage dependency tables */ 3103 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3104 &max_sclk_vddc); 3105 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3106 &max_mclk_vddci); 3107 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3108 &max_mclk_vddc); 3109 3110 for (i = 0; i < ps->performance_level_count; i++) { 3111 if (max_sclk_vddc) { 3112 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3113 ps->performance_levels[i].sclk = max_sclk_vddc; 3114 } 3115 if (max_mclk_vddci) { 3116 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3117 ps->performance_levels[i].mclk = max_mclk_vddci; 3118 } 3119 if (max_mclk_vddc) { 3120 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3121 ps->performance_levels[i].mclk = max_mclk_vddc; 3122 } 3123 if (max_mclk) { 3124 if (ps->performance_levels[i].mclk > max_mclk) 3125 ps->performance_levels[i].mclk = max_mclk; 3126 } 3127 if (max_sclk) { 3128 if (ps->performance_levels[i].sclk > max_sclk) 3129 ps->performance_levels[i].sclk = max_sclk; 3130 } 3131 } 3132 3133 /* XXX validate the min clocks required for display */ 3134 3135 if (disable_mclk_switching) { 3136 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3137 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3138 } else { 3139 mclk = ps->performance_levels[0].mclk; 3140 vddci = ps->performance_levels[0].vddci; 3141 } 3142 3143 if (disable_sclk_switching) { 3144 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3145 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3146 } else { 3147 sclk = ps->performance_levels[0].sclk; 3148 vddc = ps->performance_levels[0].vddc; 3149 } 3150 3151 if (rps->vce_active) { 3152 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3153 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3154 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3155 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3156 } 3157 3158 /* adjusted low state */ 3159 ps->performance_levels[0].sclk = sclk; 3160 ps->performance_levels[0].mclk = mclk; 3161 ps->performance_levels[0].vddc = vddc; 3162 ps->performance_levels[0].vddci = vddci; 3163 3164 if (disable_sclk_switching) { 3165 sclk = ps->performance_levels[0].sclk; 3166 for (i = 1; i < ps->performance_level_count; i++) { 3167 if (sclk < ps->performance_levels[i].sclk) 3168 sclk = ps->performance_levels[i].sclk; 3169 } 3170 for (i = 0; i < ps->performance_level_count; i++) { 3171 ps->performance_levels[i].sclk = sclk; 3172 ps->performance_levels[i].vddc = vddc; 3173 } 3174 } else { 3175 for (i = 1; i < ps->performance_level_count; i++) { 3176 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3177 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3178 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3179 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3180 } 3181 } 3182 3183 if (disable_mclk_switching) { 3184 mclk = ps->performance_levels[0].mclk; 3185 for (i = 1; i < ps->performance_level_count; i++) { 3186 if (mclk < ps->performance_levels[i].mclk) 3187 mclk = ps->performance_levels[i].mclk; 3188 } 3189 for (i = 0; i < ps->performance_level_count; i++) { 3190 ps->performance_levels[i].mclk = mclk; 3191 ps->performance_levels[i].vddci = vddci; 3192 } 3193 } else { 3194 for (i = 1; i < ps->performance_level_count; i++) { 3195 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3196 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3197 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3198 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3199 } 3200 } 3201 3202 for (i = 0; i < ps->performance_level_count; i++) 3203 btc_adjust_clock_combinations(rdev, max_limits, 3204 &ps->performance_levels[i]); 3205 3206 for (i = 0; i < ps->performance_level_count; i++) { 3207 if (ps->performance_levels[i].vddc < min_vce_voltage) 3208 ps->performance_levels[i].vddc = min_vce_voltage; 3209 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3210 ps->performance_levels[i].sclk, 3211 max_limits->vddc, &ps->performance_levels[i].vddc); 3212 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3213 ps->performance_levels[i].mclk, 3214 max_limits->vddci, &ps->performance_levels[i].vddci); 3215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3216 ps->performance_levels[i].mclk, 3217 max_limits->vddc, &ps->performance_levels[i].vddc); 3218 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3219 rdev->clock.current_dispclk, 3220 max_limits->vddc, &ps->performance_levels[i].vddc); 3221 } 3222 3223 for (i = 0; i < ps->performance_level_count; i++) { 3224 btc_apply_voltage_delta_rules(rdev, 3225 max_limits->vddc, max_limits->vddci, 3226 &ps->performance_levels[i].vddc, 3227 &ps->performance_levels[i].vddci); 3228 } 3229 3230 ps->dc_compatible = true; 3231 for (i = 0; i < ps->performance_level_count; i++) { 3232 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3233 ps->dc_compatible = false; 3234 } 3235 } 3236 3237 #if 0 3238 static int si_read_smc_soft_register(struct radeon_device *rdev, 3239 u16 reg_offset, u32 *value) 3240 { 3241 struct si_power_info *si_pi = si_get_pi(rdev); 3242 3243 return si_read_smc_sram_dword(rdev, 3244 si_pi->soft_regs_start + reg_offset, value, 3245 si_pi->sram_end); 3246 } 3247 #endif 3248 3249 static int si_write_smc_soft_register(struct radeon_device *rdev, 3250 u16 reg_offset, u32 value) 3251 { 3252 struct si_power_info *si_pi = si_get_pi(rdev); 3253 3254 return si_write_smc_sram_dword(rdev, 3255 si_pi->soft_regs_start + reg_offset, 3256 value, si_pi->sram_end); 3257 } 3258 3259 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3260 { 3261 bool ret = false; 3262 u32 tmp, width, row, column, bank, density; 3263 bool is_memory_gddr5, is_special; 3264 3265 tmp = RREG32(MC_SEQ_MISC0); 3266 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3267 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3268 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3269 3270 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3271 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3272 3273 tmp = RREG32(MC_ARB_RAMCFG); 3274 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3275 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3276 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3277 3278 density = (1 << (row + column - 20 + bank)) * width; 3279 3280 if ((rdev->pdev->device == 0x6819) && 3281 is_memory_gddr5 && is_special && (density == 0x400)) 3282 ret = true; 3283 3284 return ret; 3285 } 3286 3287 static void si_get_leakage_vddc(struct radeon_device *rdev) 3288 { 3289 struct si_power_info *si_pi = si_get_pi(rdev); 3290 u16 vddc, count = 0; 3291 int i, ret; 3292 3293 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3294 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3295 3296 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3297 si_pi->leakage_voltage.entries[count].voltage = vddc; 3298 si_pi->leakage_voltage.entries[count].leakage_index = 3299 SISLANDS_LEAKAGE_INDEX0 + i; 3300 count++; 3301 } 3302 } 3303 si_pi->leakage_voltage.count = count; 3304 } 3305 3306 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3307 u32 index, u16 *leakage_voltage) 3308 { 3309 struct si_power_info *si_pi = si_get_pi(rdev); 3310 int i; 3311 3312 if (leakage_voltage == NULL) 3313 return -EINVAL; 3314 3315 if ((index & 0xff00) != 0xff00) 3316 return -EINVAL; 3317 3318 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3319 return -EINVAL; 3320 3321 if (index < SISLANDS_LEAKAGE_INDEX0) 3322 return -EINVAL; 3323 3324 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3325 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3326 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3327 return 0; 3328 } 3329 } 3330 return -EAGAIN; 3331 } 3332 3333 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3334 { 3335 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3336 bool want_thermal_protection; 3337 enum radeon_dpm_event_src dpm_event_src; 3338 3339 switch (sources) { 3340 case 0: 3341 default: 3342 want_thermal_protection = false; 3343 break; 3344 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3345 want_thermal_protection = true; 3346 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3347 break; 3348 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3349 want_thermal_protection = true; 3350 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3351 break; 3352 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3353 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3354 want_thermal_protection = true; 3355 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3356 break; 3357 } 3358 3359 if (want_thermal_protection) { 3360 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3361 if (pi->thermal_protection) 3362 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3363 } else { 3364 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3365 } 3366 } 3367 3368 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3369 enum radeon_dpm_auto_throttle_src source, 3370 bool enable) 3371 { 3372 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3373 3374 if (enable) { 3375 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3376 pi->active_auto_throttle_sources |= 1 << source; 3377 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3378 } 3379 } else { 3380 if (pi->active_auto_throttle_sources & (1 << source)) { 3381 pi->active_auto_throttle_sources &= ~(1 << source); 3382 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3383 } 3384 } 3385 } 3386 3387 static void si_start_dpm(struct radeon_device *rdev) 3388 { 3389 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3390 } 3391 3392 static void si_stop_dpm(struct radeon_device *rdev) 3393 { 3394 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3395 } 3396 3397 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3398 { 3399 if (enable) 3400 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3401 else 3402 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3403 3404 } 3405 3406 #if 0 3407 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3408 u32 thermal_level) 3409 { 3410 PPSMC_Result ret; 3411 3412 if (thermal_level == 0) { 3413 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3414 if (ret == PPSMC_Result_OK) 3415 return 0; 3416 else 3417 return -EINVAL; 3418 } 3419 return 0; 3420 } 3421 3422 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3423 { 3424 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3425 } 3426 #endif 3427 3428 #if 0 3429 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3430 { 3431 if (ac_power) 3432 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3433 0 : -EINVAL; 3434 3435 return 0; 3436 } 3437 #endif 3438 3439 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3440 PPSMC_Msg msg, u32 parameter) 3441 { 3442 WREG32(SMC_SCRATCH0, parameter); 3443 return si_send_msg_to_smc(rdev, msg); 3444 } 3445 3446 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3447 { 3448 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3449 return -EINVAL; 3450 3451 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3452 0 : -EINVAL; 3453 } 3454 3455 int si_dpm_force_performance_level(struct radeon_device *rdev, 3456 enum radeon_dpm_forced_level level) 3457 { 3458 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3459 struct ni_ps *ps = ni_get_ps(rps); 3460 u32 levels = ps->performance_level_count; 3461 3462 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3463 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3464 return -EINVAL; 3465 3466 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3467 return -EINVAL; 3468 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3469 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3470 return -EINVAL; 3471 3472 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3473 return -EINVAL; 3474 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3475 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3476 return -EINVAL; 3477 3478 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3479 return -EINVAL; 3480 } 3481 3482 rdev->pm.dpm.forced_level = level; 3483 3484 return 0; 3485 } 3486 3487 #if 0 3488 static int si_set_boot_state(struct radeon_device *rdev) 3489 { 3490 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3491 0 : -EINVAL; 3492 } 3493 #endif 3494 3495 static int si_set_sw_state(struct radeon_device *rdev) 3496 { 3497 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3498 0 : -EINVAL; 3499 } 3500 3501 static int si_halt_smc(struct radeon_device *rdev) 3502 { 3503 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3504 return -EINVAL; 3505 3506 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3507 0 : -EINVAL; 3508 } 3509 3510 static int si_resume_smc(struct radeon_device *rdev) 3511 { 3512 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3513 return -EINVAL; 3514 3515 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3516 0 : -EINVAL; 3517 } 3518 3519 static void si_dpm_start_smc(struct radeon_device *rdev) 3520 { 3521 si_program_jump_on_start(rdev); 3522 si_start_smc(rdev); 3523 si_start_smc_clock(rdev); 3524 } 3525 3526 static void si_dpm_stop_smc(struct radeon_device *rdev) 3527 { 3528 si_reset_smc(rdev); 3529 si_stop_smc_clock(rdev); 3530 } 3531 3532 static int si_process_firmware_header(struct radeon_device *rdev) 3533 { 3534 struct si_power_info *si_pi = si_get_pi(rdev); 3535 u32 tmp; 3536 int ret; 3537 3538 ret = si_read_smc_sram_dword(rdev, 3539 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3540 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3541 &tmp, si_pi->sram_end); 3542 if (ret) 3543 return ret; 3544 3545 si_pi->state_table_start = tmp; 3546 3547 ret = si_read_smc_sram_dword(rdev, 3548 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3549 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3550 &tmp, si_pi->sram_end); 3551 if (ret) 3552 return ret; 3553 3554 si_pi->soft_regs_start = tmp; 3555 3556 ret = si_read_smc_sram_dword(rdev, 3557 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3558 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3559 &tmp, si_pi->sram_end); 3560 if (ret) 3561 return ret; 3562 3563 si_pi->mc_reg_table_start = tmp; 3564 3565 ret = si_read_smc_sram_dword(rdev, 3566 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3567 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3568 &tmp, si_pi->sram_end); 3569 if (ret) 3570 return ret; 3571 3572 si_pi->fan_table_start = tmp; 3573 3574 ret = si_read_smc_sram_dword(rdev, 3575 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3576 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3577 &tmp, si_pi->sram_end); 3578 if (ret) 3579 return ret; 3580 3581 si_pi->arb_table_start = tmp; 3582 3583 ret = si_read_smc_sram_dword(rdev, 3584 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3585 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3586 &tmp, si_pi->sram_end); 3587 if (ret) 3588 return ret; 3589 3590 si_pi->cac_table_start = tmp; 3591 3592 ret = si_read_smc_sram_dword(rdev, 3593 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3594 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3595 &tmp, si_pi->sram_end); 3596 if (ret) 3597 return ret; 3598 3599 si_pi->dte_table_start = tmp; 3600 3601 ret = si_read_smc_sram_dword(rdev, 3602 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3603 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3604 &tmp, si_pi->sram_end); 3605 if (ret) 3606 return ret; 3607 3608 si_pi->spll_table_start = tmp; 3609 3610 ret = si_read_smc_sram_dword(rdev, 3611 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3612 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3613 &tmp, si_pi->sram_end); 3614 if (ret) 3615 return ret; 3616 3617 si_pi->papm_cfg_table_start = tmp; 3618 3619 return ret; 3620 } 3621 3622 static void si_read_clock_registers(struct radeon_device *rdev) 3623 { 3624 struct si_power_info *si_pi = si_get_pi(rdev); 3625 3626 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3627 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3628 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3629 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3630 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3631 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3632 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3633 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3634 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3635 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3636 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3637 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3638 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3639 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3640 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3641 } 3642 3643 static void si_enable_thermal_protection(struct radeon_device *rdev, 3644 bool enable) 3645 { 3646 if (enable) 3647 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3648 else 3649 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3650 } 3651 3652 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3653 { 3654 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3655 } 3656 3657 #if 0 3658 static int si_enter_ulp_state(struct radeon_device *rdev) 3659 { 3660 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3661 3662 udelay(25000); 3663 3664 return 0; 3665 } 3666 3667 static int si_exit_ulp_state(struct radeon_device *rdev) 3668 { 3669 int i; 3670 3671 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3672 3673 udelay(7000); 3674 3675 for (i = 0; i < rdev->usec_timeout; i++) { 3676 if (RREG32(SMC_RESP_0) == 1) 3677 break; 3678 udelay(1000); 3679 } 3680 3681 return 0; 3682 } 3683 #endif 3684 3685 static int si_notify_smc_display_change(struct radeon_device *rdev, 3686 bool has_display) 3687 { 3688 PPSMC_Msg msg = has_display ? 3689 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3690 3691 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3692 0 : -EINVAL; 3693 } 3694 3695 static void si_program_response_times(struct radeon_device *rdev) 3696 { 3697 u32 voltage_response_time, backbias_response_time __unused, acpi_delay_time, vbi_time_out; 3698 u32 vddc_dly, acpi_dly, vbi_dly; 3699 u32 reference_clock; 3700 3701 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3702 3703 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3704 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3705 3706 if (voltage_response_time == 0) 3707 voltage_response_time = 1000; 3708 3709 acpi_delay_time = 15000; 3710 vbi_time_out = 100000; 3711 3712 reference_clock = radeon_get_xclk(rdev); 3713 3714 vddc_dly = (voltage_response_time * reference_clock) / 100; 3715 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3716 vbi_dly = (vbi_time_out * reference_clock) / 100; 3717 3718 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3719 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3720 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3721 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3722 } 3723 3724 static void si_program_ds_registers(struct radeon_device *rdev) 3725 { 3726 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3727 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3728 3729 if (eg_pi->sclk_deep_sleep) { 3730 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3731 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3732 ~AUTOSCALE_ON_SS_CLEAR); 3733 } 3734 } 3735 3736 static void si_program_display_gap(struct radeon_device *rdev) 3737 { 3738 u32 tmp, pipe; 3739 int i; 3740 3741 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3742 if (rdev->pm.dpm.new_active_crtc_count > 0) 3743 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3744 else 3745 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3746 3747 if (rdev->pm.dpm.new_active_crtc_count > 1) 3748 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3749 else 3750 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3751 3752 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3753 3754 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3755 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3756 3757 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3758 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3759 /* find the first active crtc */ 3760 for (i = 0; i < rdev->num_crtc; i++) { 3761 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3762 break; 3763 } 3764 if (i == rdev->num_crtc) 3765 pipe = 0; 3766 else 3767 pipe = i; 3768 3769 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3770 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3771 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3772 } 3773 3774 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3775 * This can be a problem on PowerXpress systems or if you want to use the card 3776 * for offscreen rendering or compute if there are no crtcs enabled. 3777 */ 3778 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3779 } 3780 3781 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3782 { 3783 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3784 3785 if (enable) { 3786 if (pi->sclk_ss) 3787 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3788 } else { 3789 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3790 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3791 } 3792 } 3793 3794 static void si_setup_bsp(struct radeon_device *rdev) 3795 { 3796 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3797 u32 xclk = radeon_get_xclk(rdev); 3798 3799 r600_calculate_u_and_p(pi->asi, 3800 xclk, 3801 16, 3802 &pi->bsp, 3803 &pi->bsu); 3804 3805 r600_calculate_u_and_p(pi->pasi, 3806 xclk, 3807 16, 3808 &pi->pbsp, 3809 &pi->pbsu); 3810 3811 3812 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3813 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3814 3815 WREG32(CG_BSP, pi->dsp); 3816 } 3817 3818 static void si_program_git(struct radeon_device *rdev) 3819 { 3820 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3821 } 3822 3823 static void si_program_tp(struct radeon_device *rdev) 3824 { 3825 int i; 3826 enum r600_td td = R600_TD_DFLT; 3827 3828 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3829 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3830 3831 if (td == R600_TD_AUTO) 3832 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3833 else 3834 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3835 3836 if (td == R600_TD_UP) 3837 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3838 3839 if (td == R600_TD_DOWN) 3840 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3841 } 3842 3843 static void si_program_tpp(struct radeon_device *rdev) 3844 { 3845 WREG32(CG_TPC, R600_TPC_DFLT); 3846 } 3847 3848 static void si_program_sstp(struct radeon_device *rdev) 3849 { 3850 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3851 } 3852 3853 static void si_enable_display_gap(struct radeon_device *rdev) 3854 { 3855 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3856 3857 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3858 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3859 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3860 3861 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3862 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3863 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3864 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3865 } 3866 3867 static void si_program_vc(struct radeon_device *rdev) 3868 { 3869 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3870 3871 WREG32(CG_FTV, pi->vrc); 3872 } 3873 3874 static void si_clear_vc(struct radeon_device *rdev) 3875 { 3876 WREG32(CG_FTV, 0); 3877 } 3878 3879 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3880 { 3881 u8 mc_para_index; 3882 3883 if (memory_clock < 10000) 3884 mc_para_index = 0; 3885 else if (memory_clock >= 80000) 3886 mc_para_index = 0x0f; 3887 else 3888 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3889 return mc_para_index; 3890 } 3891 3892 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3893 { 3894 u8 mc_para_index; 3895 3896 if (strobe_mode) { 3897 if (memory_clock < 12500) 3898 mc_para_index = 0x00; 3899 else if (memory_clock > 47500) 3900 mc_para_index = 0x0f; 3901 else 3902 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3903 } else { 3904 if (memory_clock < 65000) 3905 mc_para_index = 0x00; 3906 else if (memory_clock > 135000) 3907 mc_para_index = 0x0f; 3908 else 3909 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3910 } 3911 return mc_para_index; 3912 } 3913 3914 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3915 { 3916 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3917 bool strobe_mode = false; 3918 u8 result = 0; 3919 3920 if (mclk <= pi->mclk_strobe_mode_threshold) 3921 strobe_mode = true; 3922 3923 if (pi->mem_gddr5) 3924 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3925 else 3926 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3927 3928 if (strobe_mode) 3929 result |= SISLANDS_SMC_STROBE_ENABLE; 3930 3931 return result; 3932 } 3933 3934 static int si_upload_firmware(struct radeon_device *rdev) 3935 { 3936 struct si_power_info *si_pi = si_get_pi(rdev); 3937 int ret; 3938 3939 si_reset_smc(rdev); 3940 si_stop_smc_clock(rdev); 3941 3942 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3943 3944 return ret; 3945 } 3946 3947 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3948 const struct atom_voltage_table *table, 3949 const struct radeon_phase_shedding_limits_table *limits) 3950 { 3951 u32 data, num_bits, num_levels; 3952 3953 if ((table == NULL) || (limits == NULL)) 3954 return false; 3955 3956 data = table->mask_low; 3957 3958 num_bits = hweight32(data); 3959 3960 if (num_bits == 0) 3961 return false; 3962 3963 num_levels = (1 << num_bits); 3964 3965 if (table->count != num_levels) 3966 return false; 3967 3968 if (limits->count != (num_levels - 1)) 3969 return false; 3970 3971 return true; 3972 } 3973 3974 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3975 u32 max_voltage_steps, 3976 struct atom_voltage_table *voltage_table) 3977 { 3978 unsigned int i, diff; 3979 3980 if (voltage_table->count <= max_voltage_steps) 3981 return; 3982 3983 diff = voltage_table->count - max_voltage_steps; 3984 3985 for (i= 0; i < max_voltage_steps; i++) 3986 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3987 3988 voltage_table->count = max_voltage_steps; 3989 } 3990 3991 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3992 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3993 struct atom_voltage_table *voltage_table) 3994 { 3995 u32 i; 3996 3997 if (voltage_dependency_table == NULL) 3998 return -EINVAL; 3999 4000 voltage_table->mask_low = 0; 4001 voltage_table->phase_delay = 0; 4002 4003 voltage_table->count = voltage_dependency_table->count; 4004 for (i = 0; i < voltage_table->count; i++) { 4005 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4006 voltage_table->entries[i].smio_low = 0; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static int si_construct_voltage_tables(struct radeon_device *rdev) 4013 { 4014 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4015 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4016 struct si_power_info *si_pi = si_get_pi(rdev); 4017 int ret; 4018 4019 if (pi->voltage_control) { 4020 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4021 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4022 if (ret) 4023 return ret; 4024 4025 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4026 si_trim_voltage_table_to_fit_state_table(rdev, 4027 SISLANDS_MAX_NO_VREG_STEPS, 4028 &eg_pi->vddc_voltage_table); 4029 } else if (si_pi->voltage_control_svi2) { 4030 ret = si_get_svi2_voltage_table(rdev, 4031 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4032 &eg_pi->vddc_voltage_table); 4033 if (ret) 4034 return ret; 4035 } else { 4036 return -EINVAL; 4037 } 4038 4039 if (eg_pi->vddci_control) { 4040 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 4041 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4042 if (ret) 4043 return ret; 4044 4045 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4046 si_trim_voltage_table_to_fit_state_table(rdev, 4047 SISLANDS_MAX_NO_VREG_STEPS, 4048 &eg_pi->vddci_voltage_table); 4049 } 4050 if (si_pi->vddci_control_svi2) { 4051 ret = si_get_svi2_voltage_table(rdev, 4052 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4053 &eg_pi->vddci_voltage_table); 4054 if (ret) 4055 return ret; 4056 } 4057 4058 if (pi->mvdd_control) { 4059 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4060 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4061 4062 if (ret) { 4063 pi->mvdd_control = false; 4064 return ret; 4065 } 4066 4067 if (si_pi->mvdd_voltage_table.count == 0) { 4068 pi->mvdd_control = false; 4069 return -EINVAL; 4070 } 4071 4072 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4073 si_trim_voltage_table_to_fit_state_table(rdev, 4074 SISLANDS_MAX_NO_VREG_STEPS, 4075 &si_pi->mvdd_voltage_table); 4076 } 4077 4078 if (si_pi->vddc_phase_shed_control) { 4079 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4080 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4081 if (ret) 4082 si_pi->vddc_phase_shed_control = false; 4083 4084 if ((si_pi->vddc_phase_shed_table.count == 0) || 4085 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4086 si_pi->vddc_phase_shed_control = false; 4087 } 4088 4089 return 0; 4090 } 4091 4092 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4093 const struct atom_voltage_table *voltage_table, 4094 SISLANDS_SMC_STATETABLE *table) 4095 { 4096 unsigned int i; 4097 4098 for (i = 0; i < voltage_table->count; i++) 4099 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4100 } 4101 4102 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4103 SISLANDS_SMC_STATETABLE *table) 4104 { 4105 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4106 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4107 struct si_power_info *si_pi = si_get_pi(rdev); 4108 u8 i; 4109 4110 if (si_pi->voltage_control_svi2) { 4111 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4112 si_pi->svc_gpio_id); 4113 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4114 si_pi->svd_gpio_id); 4115 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4116 2); 4117 } else { 4118 if (eg_pi->vddc_voltage_table.count) { 4119 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4120 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4121 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4122 4123 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4124 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4125 table->maxVDDCIndexInPPTable = i; 4126 break; 4127 } 4128 } 4129 } 4130 4131 if (eg_pi->vddci_voltage_table.count) { 4132 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4133 4134 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4135 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4136 } 4137 4138 4139 if (si_pi->mvdd_voltage_table.count) { 4140 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4141 4142 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4143 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4144 } 4145 4146 if (si_pi->vddc_phase_shed_control) { 4147 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4148 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4149 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4150 4151 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4152 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4153 4154 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4155 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4156 } else { 4157 si_pi->vddc_phase_shed_control = false; 4158 } 4159 } 4160 } 4161 4162 return 0; 4163 } 4164 4165 static int si_populate_voltage_value(struct radeon_device *rdev, 4166 const struct atom_voltage_table *table, 4167 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4168 { 4169 unsigned int i; 4170 4171 for (i = 0; i < table->count; i++) { 4172 if (value <= table->entries[i].value) { 4173 voltage->index = (u8)i; 4174 voltage->value = cpu_to_be16(table->entries[i].value); 4175 break; 4176 } 4177 } 4178 4179 if (i >= table->count) 4180 return -EINVAL; 4181 4182 return 0; 4183 } 4184 4185 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4186 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4187 { 4188 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4189 struct si_power_info *si_pi = si_get_pi(rdev); 4190 4191 if (pi->mvdd_control) { 4192 if (mclk <= pi->mvdd_split_frequency) 4193 voltage->index = 0; 4194 else 4195 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4196 4197 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4198 } 4199 return 0; 4200 } 4201 4202 static int si_get_std_voltage_value(struct radeon_device *rdev, 4203 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4204 u16 *std_voltage) 4205 { 4206 u16 v_index; 4207 bool voltage_found = false; 4208 *std_voltage = be16_to_cpu(voltage->value); 4209 4210 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4211 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4212 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4213 return -EINVAL; 4214 4215 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4216 if (be16_to_cpu(voltage->value) == 4217 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4218 voltage_found = true; 4219 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4220 *std_voltage = 4221 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4222 else 4223 *std_voltage = 4224 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4225 break; 4226 } 4227 } 4228 4229 if (!voltage_found) { 4230 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4231 if (be16_to_cpu(voltage->value) <= 4232 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4233 voltage_found = true; 4234 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4235 *std_voltage = 4236 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4237 else 4238 *std_voltage = 4239 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4240 break; 4241 } 4242 } 4243 } 4244 } else { 4245 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4246 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4247 } 4248 } 4249 4250 return 0; 4251 } 4252 4253 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4254 u16 value, u8 index, 4255 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4256 { 4257 voltage->index = index; 4258 voltage->value = cpu_to_be16(value); 4259 4260 return 0; 4261 } 4262 4263 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4264 const struct radeon_phase_shedding_limits_table *limits, 4265 u16 voltage, u32 sclk, u32 mclk, 4266 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4267 { 4268 unsigned int i; 4269 4270 for (i = 0; i < limits->count; i++) { 4271 if ((voltage <= limits->entries[i].voltage) && 4272 (sclk <= limits->entries[i].sclk) && 4273 (mclk <= limits->entries[i].mclk)) 4274 break; 4275 } 4276 4277 smc_voltage->phase_settings = (u8)i; 4278 4279 return 0; 4280 } 4281 4282 static int si_init_arb_table_index(struct radeon_device *rdev) 4283 { 4284 struct si_power_info *si_pi = si_get_pi(rdev); 4285 u32 tmp; 4286 int ret; 4287 4288 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4289 if (ret) 4290 return ret; 4291 4292 tmp &= 0x00FFFFFF; 4293 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4294 4295 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4296 } 4297 4298 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4299 { 4300 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4301 } 4302 4303 static int si_reset_to_default(struct radeon_device *rdev) 4304 { 4305 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4306 0 : -EINVAL; 4307 } 4308 4309 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4310 { 4311 struct si_power_info *si_pi = si_get_pi(rdev); 4312 u32 tmp; 4313 int ret; 4314 4315 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4316 &tmp, si_pi->sram_end); 4317 if (ret) 4318 return ret; 4319 4320 tmp = (tmp >> 24) & 0xff; 4321 4322 if (tmp == MC_CG_ARB_FREQ_F0) 4323 return 0; 4324 4325 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4326 } 4327 4328 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4329 u32 engine_clock) 4330 { 4331 u32 dram_rows; 4332 u32 dram_refresh_rate; 4333 u32 mc_arb_rfsh_rate; 4334 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4335 4336 if (tmp >= 4) 4337 dram_rows = 16384; 4338 else 4339 dram_rows = 1 << (tmp + 10); 4340 4341 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4342 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4343 4344 return mc_arb_rfsh_rate; 4345 } 4346 4347 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4348 struct rv7xx_pl *pl, 4349 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4350 { 4351 u32 dram_timing; 4352 u32 dram_timing2; 4353 u32 burst_time; 4354 4355 arb_regs->mc_arb_rfsh_rate = 4356 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4357 4358 radeon_atom_set_engine_dram_timings(rdev, 4359 pl->sclk, 4360 pl->mclk); 4361 4362 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4363 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4364 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4365 4366 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4367 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4368 arb_regs->mc_arb_burst_time = (u8)burst_time; 4369 4370 return 0; 4371 } 4372 4373 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4374 struct radeon_ps *radeon_state, 4375 unsigned int first_arb_set) 4376 { 4377 struct si_power_info *si_pi = si_get_pi(rdev); 4378 struct ni_ps *state = ni_get_ps(radeon_state); 4379 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4380 int i, ret = 0; 4381 4382 for (i = 0; i < state->performance_level_count; i++) { 4383 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4384 if (ret) 4385 break; 4386 ret = si_copy_bytes_to_smc(rdev, 4387 si_pi->arb_table_start + 4388 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4389 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4390 (u8 *)&arb_regs, 4391 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4392 si_pi->sram_end); 4393 if (ret) 4394 break; 4395 } 4396 4397 return ret; 4398 } 4399 4400 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4401 struct radeon_ps *radeon_new_state) 4402 { 4403 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4404 SISLANDS_DRIVER_STATE_ARB_INDEX); 4405 } 4406 4407 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4408 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4409 { 4410 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4411 struct si_power_info *si_pi = si_get_pi(rdev); 4412 4413 if (pi->mvdd_control) 4414 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4415 si_pi->mvdd_bootup_value, voltage); 4416 4417 return 0; 4418 } 4419 4420 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4421 struct radeon_ps *radeon_initial_state, 4422 SISLANDS_SMC_STATETABLE *table) 4423 { 4424 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4425 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4426 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4427 struct si_power_info *si_pi = si_get_pi(rdev); 4428 u32 reg; 4429 int ret; 4430 4431 table->initialState.levels[0].mclk.vDLL_CNTL = 4432 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4433 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4434 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4435 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4436 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4437 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4438 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4439 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4440 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4441 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4442 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4443 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4444 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4445 table->initialState.levels[0].mclk.vMPLL_SS = 4446 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4447 table->initialState.levels[0].mclk.vMPLL_SS2 = 4448 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4449 4450 table->initialState.levels[0].mclk.mclk_value = 4451 cpu_to_be32(initial_state->performance_levels[0].mclk); 4452 4453 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4454 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4455 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4456 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4457 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4458 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4459 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4460 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4461 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4462 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4463 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4464 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4465 4466 table->initialState.levels[0].sclk.sclk_value = 4467 cpu_to_be32(initial_state->performance_levels[0].sclk); 4468 4469 table->initialState.levels[0].arbRefreshState = 4470 SISLANDS_INITIAL_STATE_ARB_INDEX; 4471 4472 table->initialState.levels[0].ACIndex = 0; 4473 4474 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4475 initial_state->performance_levels[0].vddc, 4476 &table->initialState.levels[0].vddc); 4477 4478 if (!ret) { 4479 u16 std_vddc; 4480 4481 ret = si_get_std_voltage_value(rdev, 4482 &table->initialState.levels[0].vddc, 4483 &std_vddc); 4484 if (!ret) 4485 si_populate_std_voltage_value(rdev, std_vddc, 4486 table->initialState.levels[0].vddc.index, 4487 &table->initialState.levels[0].std_vddc); 4488 } 4489 4490 if (eg_pi->vddci_control) 4491 si_populate_voltage_value(rdev, 4492 &eg_pi->vddci_voltage_table, 4493 initial_state->performance_levels[0].vddci, 4494 &table->initialState.levels[0].vddci); 4495 4496 if (si_pi->vddc_phase_shed_control) 4497 si_populate_phase_shedding_value(rdev, 4498 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4499 initial_state->performance_levels[0].vddc, 4500 initial_state->performance_levels[0].sclk, 4501 initial_state->performance_levels[0].mclk, 4502 &table->initialState.levels[0].vddc); 4503 4504 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4505 4506 reg = CG_R(0xffff) | CG_L(0); 4507 table->initialState.levels[0].aT = cpu_to_be32(reg); 4508 4509 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4510 4511 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4512 4513 if (pi->mem_gddr5) { 4514 table->initialState.levels[0].strobeMode = 4515 si_get_strobe_mode_settings(rdev, 4516 initial_state->performance_levels[0].mclk); 4517 4518 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4519 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4520 else 4521 table->initialState.levels[0].mcFlags = 0; 4522 } 4523 4524 table->initialState.levelCount = 1; 4525 4526 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4527 4528 table->initialState.levels[0].dpm2.MaxPS = 0; 4529 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4530 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4531 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4532 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4533 4534 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4535 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4536 4537 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4538 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4539 4540 return 0; 4541 } 4542 4543 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4544 SISLANDS_SMC_STATETABLE *table) 4545 { 4546 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4547 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4548 struct si_power_info *si_pi = si_get_pi(rdev); 4549 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4550 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4551 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4552 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4553 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4554 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4555 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4556 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4557 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4558 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4559 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4560 u32 reg; 4561 int ret; 4562 4563 table->ACPIState = table->initialState; 4564 4565 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4566 4567 if (pi->acpi_vddc) { 4568 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4569 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4570 if (!ret) { 4571 u16 std_vddc; 4572 4573 ret = si_get_std_voltage_value(rdev, 4574 &table->ACPIState.levels[0].vddc, &std_vddc); 4575 if (!ret) 4576 si_populate_std_voltage_value(rdev, std_vddc, 4577 table->ACPIState.levels[0].vddc.index, 4578 &table->ACPIState.levels[0].std_vddc); 4579 } 4580 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4581 4582 if (si_pi->vddc_phase_shed_control) { 4583 si_populate_phase_shedding_value(rdev, 4584 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4585 pi->acpi_vddc, 4586 0, 4587 0, 4588 &table->ACPIState.levels[0].vddc); 4589 } 4590 } else { 4591 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4592 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4593 if (!ret) { 4594 u16 std_vddc; 4595 4596 ret = si_get_std_voltage_value(rdev, 4597 &table->ACPIState.levels[0].vddc, &std_vddc); 4598 4599 if (!ret) 4600 si_populate_std_voltage_value(rdev, std_vddc, 4601 table->ACPIState.levels[0].vddc.index, 4602 &table->ACPIState.levels[0].std_vddc); 4603 } 4604 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4605 si_pi->sys_pcie_mask, 4606 si_pi->boot_pcie_gen, 4607 RADEON_PCIE_GEN1); 4608 4609 if (si_pi->vddc_phase_shed_control) 4610 si_populate_phase_shedding_value(rdev, 4611 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4612 pi->min_vddc_in_table, 4613 0, 4614 0, 4615 &table->ACPIState.levels[0].vddc); 4616 } 4617 4618 if (pi->acpi_vddc) { 4619 if (eg_pi->acpi_vddci) 4620 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4621 eg_pi->acpi_vddci, 4622 &table->ACPIState.levels[0].vddci); 4623 } 4624 4625 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4626 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4627 4628 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4629 4630 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4631 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4632 4633 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4634 cpu_to_be32(dll_cntl); 4635 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4636 cpu_to_be32(mclk_pwrmgt_cntl); 4637 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4638 cpu_to_be32(mpll_ad_func_cntl); 4639 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4640 cpu_to_be32(mpll_dq_func_cntl); 4641 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4642 cpu_to_be32(mpll_func_cntl); 4643 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4644 cpu_to_be32(mpll_func_cntl_1); 4645 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4646 cpu_to_be32(mpll_func_cntl_2); 4647 table->ACPIState.levels[0].mclk.vMPLL_SS = 4648 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4649 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4650 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4651 4652 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4653 cpu_to_be32(spll_func_cntl); 4654 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4655 cpu_to_be32(spll_func_cntl_2); 4656 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4657 cpu_to_be32(spll_func_cntl_3); 4658 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4659 cpu_to_be32(spll_func_cntl_4); 4660 4661 table->ACPIState.levels[0].mclk.mclk_value = 0; 4662 table->ACPIState.levels[0].sclk.sclk_value = 0; 4663 4664 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4665 4666 if (eg_pi->dynamic_ac_timing) 4667 table->ACPIState.levels[0].ACIndex = 0; 4668 4669 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4670 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4671 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4672 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4673 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4674 4675 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4676 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4677 4678 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4679 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4680 4681 return 0; 4682 } 4683 4684 static int si_populate_ulv_state(struct radeon_device *rdev, 4685 SISLANDS_SMC_SWSTATE *state) 4686 { 4687 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4688 struct si_power_info *si_pi = si_get_pi(rdev); 4689 struct si_ulv_param *ulv = &si_pi->ulv; 4690 u32 sclk_in_sr = 1350; /* ??? */ 4691 int ret; 4692 4693 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4694 &state->levels[0]); 4695 if (!ret) { 4696 if (eg_pi->sclk_deep_sleep) { 4697 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4698 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4699 else 4700 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4701 } 4702 if (ulv->one_pcie_lane_in_ulv) 4703 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4704 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4705 state->levels[0].ACIndex = 1; 4706 state->levels[0].std_vddc = state->levels[0].vddc; 4707 state->levelCount = 1; 4708 4709 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4710 } 4711 4712 return ret; 4713 } 4714 4715 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4716 { 4717 struct si_power_info *si_pi = si_get_pi(rdev); 4718 struct si_ulv_param *ulv = &si_pi->ulv; 4719 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4720 int ret; 4721 4722 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4723 &arb_regs); 4724 if (ret) 4725 return ret; 4726 4727 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4728 ulv->volt_change_delay); 4729 4730 ret = si_copy_bytes_to_smc(rdev, 4731 si_pi->arb_table_start + 4732 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4733 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4734 (u8 *)&arb_regs, 4735 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4736 si_pi->sram_end); 4737 4738 return ret; 4739 } 4740 4741 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4742 { 4743 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4744 4745 pi->mvdd_split_frequency = 30000; 4746 } 4747 4748 static int si_init_smc_table(struct radeon_device *rdev) 4749 { 4750 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4751 struct si_power_info *si_pi = si_get_pi(rdev); 4752 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4753 const struct si_ulv_param *ulv = &si_pi->ulv; 4754 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4755 int ret; 4756 u32 lane_width; 4757 u32 vr_hot_gpio; 4758 4759 si_populate_smc_voltage_tables(rdev, table); 4760 4761 switch (rdev->pm.int_thermal_type) { 4762 case THERMAL_TYPE_SI: 4763 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4764 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4765 break; 4766 case THERMAL_TYPE_NONE: 4767 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4768 break; 4769 default: 4770 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4771 break; 4772 } 4773 4774 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4775 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4776 4777 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4778 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4779 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4780 } 4781 4782 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4783 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4784 4785 if (pi->mem_gddr5) 4786 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4787 4788 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4789 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4790 4791 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4792 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4793 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4794 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4795 vr_hot_gpio); 4796 } 4797 4798 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4799 if (ret) 4800 return ret; 4801 4802 ret = si_populate_smc_acpi_state(rdev, table); 4803 if (ret) 4804 return ret; 4805 4806 table->driverState = table->initialState; 4807 4808 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4809 SISLANDS_INITIAL_STATE_ARB_INDEX); 4810 if (ret) 4811 return ret; 4812 4813 if (ulv->supported && ulv->pl.vddc) { 4814 ret = si_populate_ulv_state(rdev, &table->ULVState); 4815 if (ret) 4816 return ret; 4817 4818 ret = si_program_ulv_memory_timing_parameters(rdev); 4819 if (ret) 4820 return ret; 4821 4822 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4823 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4824 4825 lane_width = radeon_get_pcie_lanes(rdev); 4826 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4827 } else { 4828 table->ULVState = table->initialState; 4829 } 4830 4831 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4832 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4833 si_pi->sram_end); 4834 } 4835 4836 static int si_calculate_sclk_params(struct radeon_device *rdev, 4837 u32 engine_clock, 4838 SISLANDS_SMC_SCLK_VALUE *sclk) 4839 { 4840 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4841 struct si_power_info *si_pi = si_get_pi(rdev); 4842 struct atom_clock_dividers dividers; 4843 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4844 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4845 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4846 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4847 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4848 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4849 u64 tmp; 4850 u32 reference_clock = rdev->clock.spll.reference_freq; 4851 u32 reference_divider; 4852 u32 fbdiv; 4853 int ret; 4854 4855 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4856 engine_clock, false, ÷rs); 4857 if (ret) 4858 return ret; 4859 4860 reference_divider = 1 + dividers.ref_div; 4861 4862 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4863 do_div(tmp, reference_clock); 4864 fbdiv = (u32) tmp; 4865 4866 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4867 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4868 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4869 4870 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4871 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4872 4873 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4874 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4875 spll_func_cntl_3 |= SPLL_DITHEN; 4876 4877 if (pi->sclk_ss) { 4878 struct radeon_atom_ss ss; 4879 u32 vco_freq = engine_clock * dividers.post_div; 4880 4881 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4882 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4883 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4884 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4885 4886 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4887 cg_spll_spread_spectrum |= CLK_S(clk_s); 4888 cg_spll_spread_spectrum |= SSEN; 4889 4890 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4891 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4892 } 4893 } 4894 4895 sclk->sclk_value = engine_clock; 4896 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4897 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4898 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4899 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4900 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4901 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4902 4903 return 0; 4904 } 4905 4906 static int si_populate_sclk_value(struct radeon_device *rdev, 4907 u32 engine_clock, 4908 SISLANDS_SMC_SCLK_VALUE *sclk) 4909 { 4910 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4911 int ret; 4912 4913 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4914 if (!ret) { 4915 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4916 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4917 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4918 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4919 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4920 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4921 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4922 } 4923 4924 return ret; 4925 } 4926 4927 static int si_populate_mclk_value(struct radeon_device *rdev, 4928 u32 engine_clock, 4929 u32 memory_clock, 4930 SISLANDS_SMC_MCLK_VALUE *mclk, 4931 bool strobe_mode, 4932 bool dll_state_on) 4933 { 4934 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4935 struct si_power_info *si_pi = si_get_pi(rdev); 4936 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4937 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4938 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4939 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4940 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4941 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4942 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4943 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4944 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4945 struct atom_mpll_param mpll_param; 4946 int ret; 4947 4948 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4949 if (ret) 4950 return ret; 4951 4952 mpll_func_cntl &= ~BWCTRL_MASK; 4953 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4954 4955 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4956 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4957 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4958 4959 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4960 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4961 4962 if (pi->mem_gddr5) { 4963 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4964 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4965 YCLK_POST_DIV(mpll_param.post_div); 4966 } 4967 4968 if (pi->mclk_ss) { 4969 struct radeon_atom_ss ss; 4970 u32 freq_nom; 4971 u32 tmp; 4972 u32 reference_clock = rdev->clock.mpll.reference_freq; 4973 4974 if (pi->mem_gddr5) 4975 freq_nom = memory_clock * 4; 4976 else 4977 freq_nom = memory_clock * 2; 4978 4979 tmp = freq_nom / reference_clock; 4980 tmp = tmp * tmp; 4981 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4982 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4983 u32 clks = reference_clock * 5 / ss.rate; 4984 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4985 4986 mpll_ss1 &= ~CLKV_MASK; 4987 mpll_ss1 |= CLKV(clkv); 4988 4989 mpll_ss2 &= ~CLKS_MASK; 4990 mpll_ss2 |= CLKS(clks); 4991 } 4992 } 4993 4994 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4995 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4996 4997 if (dll_state_on) 4998 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4999 else 5000 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5001 5002 mclk->mclk_value = cpu_to_be32(memory_clock); 5003 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5004 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5005 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5006 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5007 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5008 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5009 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5010 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5011 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5012 5013 return 0; 5014 } 5015 5016 static void si_populate_smc_sp(struct radeon_device *rdev, 5017 struct radeon_ps *radeon_state, 5018 SISLANDS_SMC_SWSTATE *smc_state) 5019 { 5020 struct ni_ps *ps = ni_get_ps(radeon_state); 5021 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5022 int i; 5023 5024 for (i = 0; i < ps->performance_level_count - 1; i++) 5025 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5026 5027 smc_state->levels[ps->performance_level_count - 1].bSP = 5028 cpu_to_be32(pi->psp); 5029 } 5030 5031 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 5032 struct rv7xx_pl *pl, 5033 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5034 { 5035 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5036 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5037 struct si_power_info *si_pi = si_get_pi(rdev); 5038 int ret; 5039 bool dll_state_on; 5040 u16 std_vddc; 5041 bool gmc_pg = false; 5042 5043 if (eg_pi->pcie_performance_request && 5044 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 5045 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5046 else 5047 level->gen2PCIE = (u8)pl->pcie_gen; 5048 5049 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 5050 if (ret) 5051 return ret; 5052 5053 level->mcFlags = 0; 5054 5055 if (pi->mclk_stutter_mode_threshold && 5056 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5057 !eg_pi->uvd_enabled && 5058 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5059 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5060 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5061 5062 if (gmc_pg) 5063 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5064 } 5065 5066 if (pi->mem_gddr5) { 5067 if (pl->mclk > pi->mclk_edc_enable_threshold) 5068 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5069 5070 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5071 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5072 5073 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5074 5075 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5076 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5077 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5078 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5079 else 5080 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5081 } else { 5082 dll_state_on = false; 5083 } 5084 } else { 5085 level->strobeMode = si_get_strobe_mode_settings(rdev, 5086 pl->mclk); 5087 5088 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5089 } 5090 5091 ret = si_populate_mclk_value(rdev, 5092 pl->sclk, 5093 pl->mclk, 5094 &level->mclk, 5095 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5096 if (ret) 5097 return ret; 5098 5099 ret = si_populate_voltage_value(rdev, 5100 &eg_pi->vddc_voltage_table, 5101 pl->vddc, &level->vddc); 5102 if (ret) 5103 return ret; 5104 5105 5106 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5107 if (ret) 5108 return ret; 5109 5110 ret = si_populate_std_voltage_value(rdev, std_vddc, 5111 level->vddc.index, &level->std_vddc); 5112 if (ret) 5113 return ret; 5114 5115 if (eg_pi->vddci_control) { 5116 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5117 pl->vddci, &level->vddci); 5118 if (ret) 5119 return ret; 5120 } 5121 5122 if (si_pi->vddc_phase_shed_control) { 5123 ret = si_populate_phase_shedding_value(rdev, 5124 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5125 pl->vddc, 5126 pl->sclk, 5127 pl->mclk, 5128 &level->vddc); 5129 if (ret) 5130 return ret; 5131 } 5132 5133 level->MaxPoweredUpCU = si_pi->max_cu; 5134 5135 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5136 5137 return ret; 5138 } 5139 5140 static int si_populate_smc_t(struct radeon_device *rdev, 5141 struct radeon_ps *radeon_state, 5142 SISLANDS_SMC_SWSTATE *smc_state) 5143 { 5144 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5145 struct ni_ps *state = ni_get_ps(radeon_state); 5146 u32 a_t; 5147 u32 t_l, t_h; 5148 u32 high_bsp; 5149 int i, ret; 5150 5151 if (state->performance_level_count >= 9) 5152 return -EINVAL; 5153 5154 if (state->performance_level_count < 2) { 5155 a_t = CG_R(0xffff) | CG_L(0); 5156 smc_state->levels[0].aT = cpu_to_be32(a_t); 5157 return 0; 5158 } 5159 5160 smc_state->levels[0].aT = cpu_to_be32(0); 5161 5162 for (i = 0; i <= state->performance_level_count - 2; i++) { 5163 ret = r600_calculate_at( 5164 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5165 100 * R600_AH_DFLT, 5166 state->performance_levels[i + 1].sclk, 5167 state->performance_levels[i].sclk, 5168 &t_l, 5169 &t_h); 5170 5171 if (ret) { 5172 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5173 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5174 } 5175 5176 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5177 a_t |= CG_R(t_l * pi->bsp / 20000); 5178 smc_state->levels[i].aT = cpu_to_be32(a_t); 5179 5180 high_bsp = (i == state->performance_level_count - 2) ? 5181 pi->pbsp : pi->bsp; 5182 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5183 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5184 } 5185 5186 return 0; 5187 } 5188 5189 static int si_disable_ulv(struct radeon_device *rdev) 5190 { 5191 struct si_power_info *si_pi = si_get_pi(rdev); 5192 struct si_ulv_param *ulv = &si_pi->ulv; 5193 5194 if (ulv->supported) 5195 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5196 0 : -EINVAL; 5197 5198 return 0; 5199 } 5200 5201 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5202 struct radeon_ps *radeon_state) 5203 { 5204 const struct si_power_info *si_pi = si_get_pi(rdev); 5205 const struct si_ulv_param *ulv = &si_pi->ulv; 5206 const struct ni_ps *state = ni_get_ps(radeon_state); 5207 int i; 5208 5209 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5210 return false; 5211 5212 /* XXX validate against display requirements! */ 5213 5214 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5215 if (rdev->clock.current_dispclk <= 5216 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5217 if (ulv->pl.vddc < 5218 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5219 return false; 5220 } 5221 } 5222 5223 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5224 return false; 5225 5226 return true; 5227 } 5228 5229 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5230 struct radeon_ps *radeon_new_state) 5231 { 5232 const struct si_power_info *si_pi = si_get_pi(rdev); 5233 const struct si_ulv_param *ulv = &si_pi->ulv; 5234 5235 if (ulv->supported) { 5236 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5237 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5238 0 : -EINVAL; 5239 } 5240 return 0; 5241 } 5242 5243 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5244 struct radeon_ps *radeon_state, 5245 SISLANDS_SMC_SWSTATE *smc_state) 5246 { 5247 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5248 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5249 struct si_power_info *si_pi = si_get_pi(rdev); 5250 struct ni_ps *state = ni_get_ps(radeon_state); 5251 int i, ret; 5252 u32 threshold; 5253 u32 sclk_in_sr = 1350; /* ??? */ 5254 5255 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5256 return -EINVAL; 5257 5258 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5259 5260 if (radeon_state->vclk && radeon_state->dclk) { 5261 eg_pi->uvd_enabled = true; 5262 if (eg_pi->smu_uvd_hs) 5263 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5264 } else { 5265 eg_pi->uvd_enabled = false; 5266 } 5267 5268 if (state->dc_compatible) 5269 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5270 5271 smc_state->levelCount = 0; 5272 for (i = 0; i < state->performance_level_count; i++) { 5273 if (eg_pi->sclk_deep_sleep) { 5274 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5275 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5276 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5277 else 5278 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5279 } 5280 } 5281 5282 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5283 &smc_state->levels[i]); 5284 smc_state->levels[i].arbRefreshState = 5285 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5286 5287 if (ret) 5288 return ret; 5289 5290 if (ni_pi->enable_power_containment) 5291 smc_state->levels[i].displayWatermark = 5292 (state->performance_levels[i].sclk < threshold) ? 5293 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5294 else 5295 smc_state->levels[i].displayWatermark = (i < 2) ? 5296 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5297 5298 if (eg_pi->dynamic_ac_timing) 5299 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5300 else 5301 smc_state->levels[i].ACIndex = 0; 5302 5303 smc_state->levelCount++; 5304 } 5305 5306 si_write_smc_soft_register(rdev, 5307 SI_SMC_SOFT_REGISTER_watermark_threshold, 5308 threshold / 512); 5309 5310 si_populate_smc_sp(rdev, radeon_state, smc_state); 5311 5312 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5313 if (ret) 5314 ni_pi->enable_power_containment = false; 5315 5316 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5317 if (ret) 5318 ni_pi->enable_sq_ramping = false; 5319 5320 return si_populate_smc_t(rdev, radeon_state, smc_state); 5321 } 5322 5323 static int si_upload_sw_state(struct radeon_device *rdev, 5324 struct radeon_ps *radeon_new_state) 5325 { 5326 struct si_power_info *si_pi = si_get_pi(rdev); 5327 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5328 int ret; 5329 u32 address = si_pi->state_table_start + 5330 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5331 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5332 ((new_state->performance_level_count - 1) * 5333 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5334 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5335 5336 memset(smc_state, 0, state_size); 5337 5338 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5339 if (ret) 5340 return ret; 5341 5342 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5343 state_size, si_pi->sram_end); 5344 5345 return ret; 5346 } 5347 5348 static int si_upload_ulv_state(struct radeon_device *rdev) 5349 { 5350 struct si_power_info *si_pi = si_get_pi(rdev); 5351 struct si_ulv_param *ulv = &si_pi->ulv; 5352 int ret = 0; 5353 5354 if (ulv->supported && ulv->pl.vddc) { 5355 u32 address = si_pi->state_table_start + 5356 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5357 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5358 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5359 5360 memset(smc_state, 0, state_size); 5361 5362 ret = si_populate_ulv_state(rdev, smc_state); 5363 if (!ret) 5364 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5365 state_size, si_pi->sram_end); 5366 } 5367 5368 return ret; 5369 } 5370 5371 static int si_upload_smc_data(struct radeon_device *rdev) 5372 { 5373 struct radeon_crtc *radeon_crtc = NULL; 5374 int i; 5375 5376 if (rdev->pm.dpm.new_active_crtc_count == 0) 5377 return 0; 5378 5379 for (i = 0; i < rdev->num_crtc; i++) { 5380 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5381 radeon_crtc = rdev->mode_info.crtcs[i]; 5382 break; 5383 } 5384 } 5385 5386 if (radeon_crtc == NULL) 5387 return 0; 5388 5389 if (radeon_crtc->line_time <= 0) 5390 return 0; 5391 5392 if (si_write_smc_soft_register(rdev, 5393 SI_SMC_SOFT_REGISTER_crtc_index, 5394 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5395 return 0; 5396 5397 if (si_write_smc_soft_register(rdev, 5398 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5399 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5400 return 0; 5401 5402 if (si_write_smc_soft_register(rdev, 5403 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5404 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5405 return 0; 5406 5407 return 0; 5408 } 5409 5410 static int si_set_mc_special_registers(struct radeon_device *rdev, 5411 struct si_mc_reg_table *table) 5412 { 5413 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5414 u8 i, j, k; 5415 u32 temp_reg; 5416 5417 for (i = 0, j = table->last; i < table->last; i++) { 5418 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5419 return -EINVAL; 5420 switch (table->mc_reg_address[i].s1 << 2) { 5421 case MC_SEQ_MISC1: 5422 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5423 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5424 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5425 for (k = 0; k < table->num_entries; k++) 5426 table->mc_reg_table_entry[k].mc_data[j] = 5427 ((temp_reg & 0xffff0000)) | 5428 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5429 j++; 5430 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5431 return -EINVAL; 5432 5433 temp_reg = RREG32(MC_PMG_CMD_MRS); 5434 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5435 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5436 for (k = 0; k < table->num_entries; k++) { 5437 table->mc_reg_table_entry[k].mc_data[j] = 5438 (temp_reg & 0xffff0000) | 5439 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5440 if (!pi->mem_gddr5) 5441 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5442 } 5443 j++; 5444 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5445 return -EINVAL; 5446 5447 if (!pi->mem_gddr5) { 5448 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5449 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5450 for (k = 0; k < table->num_entries; k++) 5451 table->mc_reg_table_entry[k].mc_data[j] = 5452 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5453 j++; 5454 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5455 return -EINVAL; 5456 } 5457 break; 5458 case MC_SEQ_RESERVE_M: 5459 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5460 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5461 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5462 for(k = 0; k < table->num_entries; k++) 5463 table->mc_reg_table_entry[k].mc_data[j] = 5464 (temp_reg & 0xffff0000) | 5465 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5466 j++; 5467 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5468 return -EINVAL; 5469 break; 5470 default: 5471 break; 5472 } 5473 } 5474 5475 table->last = j; 5476 5477 return 0; 5478 } 5479 5480 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5481 { 5482 bool result = true; 5483 5484 switch (in_reg) { 5485 case MC_SEQ_RAS_TIMING >> 2: 5486 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5487 break; 5488 case MC_SEQ_CAS_TIMING >> 2: 5489 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5490 break; 5491 case MC_SEQ_MISC_TIMING >> 2: 5492 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5493 break; 5494 case MC_SEQ_MISC_TIMING2 >> 2: 5495 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5496 break; 5497 case MC_SEQ_RD_CTL_D0 >> 2: 5498 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5499 break; 5500 case MC_SEQ_RD_CTL_D1 >> 2: 5501 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5502 break; 5503 case MC_SEQ_WR_CTL_D0 >> 2: 5504 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5505 break; 5506 case MC_SEQ_WR_CTL_D1 >> 2: 5507 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5508 break; 5509 case MC_PMG_CMD_EMRS >> 2: 5510 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5511 break; 5512 case MC_PMG_CMD_MRS >> 2: 5513 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5514 break; 5515 case MC_PMG_CMD_MRS1 >> 2: 5516 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5517 break; 5518 case MC_SEQ_PMG_TIMING >> 2: 5519 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5520 break; 5521 case MC_PMG_CMD_MRS2 >> 2: 5522 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5523 break; 5524 case MC_SEQ_WR_CTL_2 >> 2: 5525 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5526 break; 5527 default: 5528 result = false; 5529 break; 5530 } 5531 5532 return result; 5533 } 5534 5535 static void si_set_valid_flag(struct si_mc_reg_table *table) 5536 { 5537 u8 i, j; 5538 5539 for (i = 0; i < table->last; i++) { 5540 for (j = 1; j < table->num_entries; j++) { 5541 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5542 table->valid_flag |= 1 << i; 5543 break; 5544 } 5545 } 5546 } 5547 } 5548 5549 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5550 { 5551 u32 i; 5552 u16 address; 5553 5554 for (i = 0; i < table->last; i++) 5555 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5556 address : table->mc_reg_address[i].s1; 5557 5558 } 5559 5560 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5561 struct si_mc_reg_table *si_table) 5562 { 5563 u8 i, j; 5564 5565 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5566 return -EINVAL; 5567 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5568 return -EINVAL; 5569 5570 for (i = 0; i < table->last; i++) 5571 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5572 si_table->last = table->last; 5573 5574 for (i = 0; i < table->num_entries; i++) { 5575 si_table->mc_reg_table_entry[i].mclk_max = 5576 table->mc_reg_table_entry[i].mclk_max; 5577 for (j = 0; j < table->last; j++) { 5578 si_table->mc_reg_table_entry[i].mc_data[j] = 5579 table->mc_reg_table_entry[i].mc_data[j]; 5580 } 5581 } 5582 si_table->num_entries = table->num_entries; 5583 5584 return 0; 5585 } 5586 5587 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5588 { 5589 struct si_power_info *si_pi = si_get_pi(rdev); 5590 struct atom_mc_reg_table *table; 5591 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5592 u8 module_index = rv770_get_memory_module_index(rdev); 5593 int ret; 5594 5595 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5596 if (!table) 5597 return -ENOMEM; 5598 5599 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5600 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5601 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5602 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5603 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5604 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5605 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5606 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5607 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5608 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5609 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5610 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5611 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5612 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5613 5614 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5615 if (ret) 5616 goto init_mc_done; 5617 5618 ret = si_copy_vbios_mc_reg_table(table, si_table); 5619 if (ret) 5620 goto init_mc_done; 5621 5622 si_set_s0_mc_reg_index(si_table); 5623 5624 ret = si_set_mc_special_registers(rdev, si_table); 5625 if (ret) 5626 goto init_mc_done; 5627 5628 si_set_valid_flag(si_table); 5629 5630 init_mc_done: 5631 kfree(table); 5632 5633 return ret; 5634 5635 } 5636 5637 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5638 SMC_SIslands_MCRegisters *mc_reg_table) 5639 { 5640 struct si_power_info *si_pi = si_get_pi(rdev); 5641 u32 i, j; 5642 5643 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5644 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5645 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5646 break; 5647 mc_reg_table->address[i].s0 = 5648 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5649 mc_reg_table->address[i].s1 = 5650 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5651 i++; 5652 } 5653 } 5654 mc_reg_table->last = (u8)i; 5655 } 5656 5657 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5658 SMC_SIslands_MCRegisterSet *data, 5659 u32 num_entries, u32 valid_flag) 5660 { 5661 u32 i, j; 5662 5663 for(i = 0, j = 0; j < num_entries; j++) { 5664 if (valid_flag & (1 << j)) { 5665 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5666 i++; 5667 } 5668 } 5669 } 5670 5671 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5672 struct rv7xx_pl *pl, 5673 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5674 { 5675 struct si_power_info *si_pi = si_get_pi(rdev); 5676 u32 i = 0; 5677 5678 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5679 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5680 break; 5681 } 5682 5683 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5684 --i; 5685 5686 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5687 mc_reg_table_data, si_pi->mc_reg_table.last, 5688 si_pi->mc_reg_table.valid_flag); 5689 } 5690 5691 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5692 struct radeon_ps *radeon_state, 5693 SMC_SIslands_MCRegisters *mc_reg_table) 5694 { 5695 struct ni_ps *state = ni_get_ps(radeon_state); 5696 int i; 5697 5698 for (i = 0; i < state->performance_level_count; i++) { 5699 si_convert_mc_reg_table_entry_to_smc(rdev, 5700 &state->performance_levels[i], 5701 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5702 } 5703 } 5704 5705 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5706 struct radeon_ps *radeon_boot_state) 5707 { 5708 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5709 struct si_power_info *si_pi = si_get_pi(rdev); 5710 struct si_ulv_param *ulv = &si_pi->ulv; 5711 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5712 5713 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5714 5715 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5716 5717 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5718 5719 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5720 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5721 5722 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5723 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5724 si_pi->mc_reg_table.last, 5725 si_pi->mc_reg_table.valid_flag); 5726 5727 if (ulv->supported && ulv->pl.vddc != 0) 5728 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5729 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5730 else 5731 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5732 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5733 si_pi->mc_reg_table.last, 5734 si_pi->mc_reg_table.valid_flag); 5735 5736 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5737 5738 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5739 (u8 *)smc_mc_reg_table, 5740 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5741 } 5742 5743 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5744 struct radeon_ps *radeon_new_state) 5745 { 5746 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5747 struct si_power_info *si_pi = si_get_pi(rdev); 5748 u32 address = si_pi->mc_reg_table_start + 5749 offsetof(SMC_SIslands_MCRegisters, 5750 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5751 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5752 5753 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5754 5755 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5756 5757 5758 return si_copy_bytes_to_smc(rdev, address, 5759 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5760 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5761 si_pi->sram_end); 5762 5763 } 5764 5765 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5766 { 5767 if (enable) 5768 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5769 else 5770 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5771 } 5772 5773 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5774 struct radeon_ps *radeon_state) 5775 { 5776 struct ni_ps *state = ni_get_ps(radeon_state); 5777 int i; 5778 u16 pcie_speed, max_speed = 0; 5779 5780 for (i = 0; i < state->performance_level_count; i++) { 5781 pcie_speed = state->performance_levels[i].pcie_gen; 5782 if (max_speed < pcie_speed) 5783 max_speed = pcie_speed; 5784 } 5785 return max_speed; 5786 } 5787 5788 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5789 { 5790 u32 speed_cntl; 5791 5792 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5793 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5794 5795 return (u16)speed_cntl; 5796 } 5797 5798 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5799 struct radeon_ps *radeon_new_state, 5800 struct radeon_ps *radeon_current_state) 5801 { 5802 struct si_power_info *si_pi = si_get_pi(rdev); 5803 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5804 enum radeon_pcie_gen current_link_speed; 5805 5806 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5807 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5808 else 5809 current_link_speed = si_pi->force_pcie_gen; 5810 5811 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5812 si_pi->pspp_notify_required = false; 5813 if (target_link_speed > current_link_speed) { 5814 switch (target_link_speed) { 5815 #if defined(CONFIG_ACPI) 5816 case RADEON_PCIE_GEN3: 5817 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5818 break; 5819 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5820 if (current_link_speed == RADEON_PCIE_GEN2) 5821 break; 5822 case RADEON_PCIE_GEN2: 5823 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5824 break; 5825 #endif 5826 default: 5827 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5828 break; 5829 } 5830 } else { 5831 if (target_link_speed < current_link_speed) 5832 si_pi->pspp_notify_required = true; 5833 } 5834 } 5835 5836 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5837 struct radeon_ps *radeon_new_state, 5838 struct radeon_ps *radeon_current_state) 5839 { 5840 struct si_power_info *si_pi = si_get_pi(rdev); 5841 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5842 u8 request; 5843 5844 if (si_pi->pspp_notify_required) { 5845 if (target_link_speed == RADEON_PCIE_GEN3) 5846 request = PCIE_PERF_REQ_PECI_GEN3; 5847 else if (target_link_speed == RADEON_PCIE_GEN2) 5848 request = PCIE_PERF_REQ_PECI_GEN2; 5849 else 5850 request = PCIE_PERF_REQ_PECI_GEN1; 5851 5852 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5853 (si_get_current_pcie_speed(rdev) > 0)) 5854 return; 5855 5856 #if defined(CONFIG_ACPI) 5857 radeon_acpi_pcie_performance_request(rdev, request, false); 5858 #endif 5859 } 5860 } 5861 5862 #if 0 5863 static int si_ds_request(struct radeon_device *rdev, 5864 bool ds_status_on, u32 count_write) 5865 { 5866 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5867 5868 if (eg_pi->sclk_deep_sleep) { 5869 if (ds_status_on) 5870 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5871 PPSMC_Result_OK) ? 5872 0 : -EINVAL; 5873 else 5874 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5875 PPSMC_Result_OK) ? 0 : -EINVAL; 5876 } 5877 return 0; 5878 } 5879 #endif 5880 5881 static void si_set_max_cu_value(struct radeon_device *rdev) 5882 { 5883 struct si_power_info *si_pi = si_get_pi(rdev); 5884 5885 if (rdev->family == CHIP_VERDE) { 5886 switch (rdev->pdev->device) { 5887 case 0x6820: 5888 case 0x6825: 5889 case 0x6821: 5890 case 0x6823: 5891 case 0x6827: 5892 si_pi->max_cu = 10; 5893 break; 5894 case 0x682D: 5895 case 0x6824: 5896 case 0x682F: 5897 case 0x6826: 5898 si_pi->max_cu = 8; 5899 break; 5900 case 0x6828: 5901 case 0x6830: 5902 case 0x6831: 5903 case 0x6838: 5904 case 0x6839: 5905 case 0x683D: 5906 si_pi->max_cu = 10; 5907 break; 5908 case 0x683B: 5909 case 0x683F: 5910 case 0x6829: 5911 si_pi->max_cu = 8; 5912 break; 5913 default: 5914 si_pi->max_cu = 0; 5915 break; 5916 } 5917 } else { 5918 si_pi->max_cu = 0; 5919 } 5920 } 5921 5922 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5923 struct radeon_clock_voltage_dependency_table *table) 5924 { 5925 u32 i; 5926 int j; 5927 u16 leakage_voltage; 5928 5929 if (table) { 5930 for (i = 0; i < table->count; i++) { 5931 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5932 table->entries[i].v, 5933 &leakage_voltage)) { 5934 case 0: 5935 table->entries[i].v = leakage_voltage; 5936 break; 5937 case -EAGAIN: 5938 return -EINVAL; 5939 case -EINVAL: 5940 default: 5941 break; 5942 } 5943 } 5944 5945 for (j = (table->count - 2); j >= 0; j--) { 5946 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5947 table->entries[j].v : table->entries[j + 1].v; 5948 } 5949 } 5950 return 0; 5951 } 5952 5953 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5954 { 5955 int ret = 0; 5956 5957 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5958 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5959 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5960 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5961 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5962 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5963 return ret; 5964 } 5965 5966 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5967 struct radeon_ps *radeon_new_state, 5968 struct radeon_ps *radeon_current_state) 5969 { 5970 u32 lane_width; 5971 u32 new_lane_width = 5972 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5973 u32 current_lane_width = 5974 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5975 5976 if (new_lane_width != current_lane_width) { 5977 radeon_set_pcie_lanes(rdev, new_lane_width); 5978 lane_width = radeon_get_pcie_lanes(rdev); 5979 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5980 } 5981 } 5982 5983 static void si_set_vce_clock(struct radeon_device *rdev, 5984 struct radeon_ps *new_rps, 5985 struct radeon_ps *old_rps) 5986 { 5987 if ((old_rps->evclk != new_rps->evclk) || 5988 (old_rps->ecclk != new_rps->ecclk)) { 5989 /* turn the clocks on when encoding, off otherwise */ 5990 if (new_rps->evclk || new_rps->ecclk) 5991 vce_v1_0_enable_mgcg(rdev, false); 5992 else 5993 vce_v1_0_enable_mgcg(rdev, true); 5994 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5995 } 5996 } 5997 5998 void si_dpm_setup_asic(struct radeon_device *rdev) 5999 { 6000 int r; 6001 6002 r = si_mc_load_microcode(rdev); 6003 if (r) 6004 DRM_ERROR("Failed to load MC firmware!\n"); 6005 rv770_get_memory_type(rdev); 6006 si_read_clock_registers(rdev); 6007 si_enable_acpi_power_management(rdev); 6008 } 6009 6010 static int si_thermal_enable_alert(struct radeon_device *rdev, 6011 bool enable) 6012 { 6013 u32 thermal_int = RREG32(CG_THERMAL_INT); 6014 6015 if (enable) { 6016 PPSMC_Result result; 6017 6018 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6019 WREG32(CG_THERMAL_INT, thermal_int); 6020 rdev->irq.dpm_thermal = false; 6021 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 6022 if (result != PPSMC_Result_OK) { 6023 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6024 return -EINVAL; 6025 } 6026 } else { 6027 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 6028 WREG32(CG_THERMAL_INT, thermal_int); 6029 rdev->irq.dpm_thermal = true; 6030 } 6031 6032 return 0; 6033 } 6034 6035 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 6036 int min_temp, int max_temp) 6037 { 6038 int low_temp = 0 * 1000; 6039 int high_temp = 255 * 1000; 6040 6041 if (low_temp < min_temp) 6042 low_temp = min_temp; 6043 if (high_temp > max_temp) 6044 high_temp = max_temp; 6045 if (high_temp < low_temp) { 6046 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6047 return -EINVAL; 6048 } 6049 6050 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6051 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6052 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6053 6054 rdev->pm.dpm.thermal.min_temp = low_temp; 6055 rdev->pm.dpm.thermal.max_temp = high_temp; 6056 6057 return 0; 6058 } 6059 6060 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6061 { 6062 struct si_power_info *si_pi = si_get_pi(rdev); 6063 u32 tmp; 6064 6065 if (si_pi->fan_ctrl_is_in_default_mode) { 6066 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6067 si_pi->fan_ctrl_default_mode = tmp; 6068 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6069 si_pi->t_min = tmp; 6070 si_pi->fan_ctrl_is_in_default_mode = false; 6071 } 6072 6073 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6074 tmp |= TMIN(0); 6075 WREG32(CG_FDO_CTRL2, tmp); 6076 6077 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6078 tmp |= FDO_PWM_MODE(mode); 6079 WREG32(CG_FDO_CTRL2, tmp); 6080 } 6081 6082 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6083 { 6084 struct si_power_info *si_pi = si_get_pi(rdev); 6085 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6086 u32 duty100; 6087 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6088 u16 fdo_min, slope1, slope2; 6089 u32 reference_clock, tmp; 6090 int ret; 6091 u64 tmp64; 6092 6093 if (!si_pi->fan_table_start) { 6094 rdev->pm.dpm.fan.ucode_fan_control = false; 6095 return 0; 6096 } 6097 6098 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6099 6100 if (duty100 == 0) { 6101 rdev->pm.dpm.fan.ucode_fan_control = false; 6102 return 0; 6103 } 6104 6105 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6106 do_div(tmp64, 10000); 6107 fdo_min = (u16)tmp64; 6108 6109 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6110 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6111 6112 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6113 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6114 6115 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6116 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6117 6118 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6119 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6120 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6121 6122 fan_table.slope1 = cpu_to_be16(slope1); 6123 fan_table.slope2 = cpu_to_be16(slope2); 6124 6125 fan_table.fdo_min = cpu_to_be16(fdo_min); 6126 6127 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6128 6129 fan_table.hys_up = cpu_to_be16(1); 6130 6131 fan_table.hys_slope = cpu_to_be16(1); 6132 6133 fan_table.temp_resp_lim = cpu_to_be16(5); 6134 6135 reference_clock = radeon_get_xclk(rdev); 6136 6137 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6138 reference_clock) / 1600); 6139 6140 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6141 6142 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6143 fan_table.temp_src = (uint8_t)tmp; 6144 6145 ret = si_copy_bytes_to_smc(rdev, 6146 si_pi->fan_table_start, 6147 (u8 *)(&fan_table), 6148 sizeof(fan_table), 6149 si_pi->sram_end); 6150 6151 if (ret) { 6152 DRM_ERROR("Failed to load fan table to the SMC."); 6153 rdev->pm.dpm.fan.ucode_fan_control = false; 6154 } 6155 6156 return 0; 6157 } 6158 6159 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6160 { 6161 struct si_power_info *si_pi = si_get_pi(rdev); 6162 PPSMC_Result ret; 6163 6164 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6165 if (ret == PPSMC_Result_OK) { 6166 si_pi->fan_is_controlled_by_smc = true; 6167 return 0; 6168 } else { 6169 return -EINVAL; 6170 } 6171 } 6172 6173 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6174 { 6175 struct si_power_info *si_pi = si_get_pi(rdev); 6176 PPSMC_Result ret; 6177 6178 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6179 6180 if (ret == PPSMC_Result_OK) { 6181 si_pi->fan_is_controlled_by_smc = false; 6182 return 0; 6183 } else { 6184 return -EINVAL; 6185 } 6186 } 6187 6188 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6189 u32 *speed) 6190 { 6191 u32 duty, duty100; 6192 u64 tmp64; 6193 6194 if (rdev->pm.no_fan) 6195 return -ENOENT; 6196 6197 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6198 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6199 6200 if (duty100 == 0) 6201 return -EINVAL; 6202 6203 tmp64 = (u64)duty * 100; 6204 do_div(tmp64, duty100); 6205 *speed = (u32)tmp64; 6206 6207 if (*speed > 100) 6208 *speed = 100; 6209 6210 return 0; 6211 } 6212 6213 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6214 u32 speed) 6215 { 6216 struct si_power_info *si_pi = si_get_pi(rdev); 6217 u32 tmp; 6218 u32 duty, duty100; 6219 u64 tmp64; 6220 6221 if (rdev->pm.no_fan) 6222 return -ENOENT; 6223 6224 if (si_pi->fan_is_controlled_by_smc) 6225 return -EINVAL; 6226 6227 if (speed > 100) 6228 return -EINVAL; 6229 6230 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6231 6232 if (duty100 == 0) 6233 return -EINVAL; 6234 6235 tmp64 = (u64)speed * duty100; 6236 do_div(tmp64, 100); 6237 duty = (u32)tmp64; 6238 6239 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6240 tmp |= FDO_STATIC_DUTY(duty); 6241 WREG32(CG_FDO_CTRL0, tmp); 6242 6243 return 0; 6244 } 6245 6246 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6247 { 6248 if (mode) { 6249 /* stop auto-manage */ 6250 if (rdev->pm.dpm.fan.ucode_fan_control) 6251 si_fan_ctrl_stop_smc_fan_control(rdev); 6252 si_fan_ctrl_set_static_mode(rdev, mode); 6253 } else { 6254 /* restart auto-manage */ 6255 if (rdev->pm.dpm.fan.ucode_fan_control) 6256 si_thermal_start_smc_fan_control(rdev); 6257 else 6258 si_fan_ctrl_set_default_mode(rdev); 6259 } 6260 } 6261 6262 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6263 { 6264 struct si_power_info *si_pi = si_get_pi(rdev); 6265 u32 tmp; 6266 6267 if (si_pi->fan_is_controlled_by_smc) 6268 return 0; 6269 6270 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6271 return (tmp >> FDO_PWM_MODE_SHIFT); 6272 } 6273 6274 #if 0 6275 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6276 u32 *speed) 6277 { 6278 u32 tach_period; 6279 u32 xclk = radeon_get_xclk(rdev); 6280 6281 if (rdev->pm.no_fan) 6282 return -ENOENT; 6283 6284 if (rdev->pm.fan_pulses_per_revolution == 0) 6285 return -ENOENT; 6286 6287 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6288 if (tach_period == 0) 6289 return -ENOENT; 6290 6291 *speed = 60 * xclk * 10000 / tach_period; 6292 6293 return 0; 6294 } 6295 6296 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6297 u32 speed) 6298 { 6299 u32 tach_period, tmp; 6300 u32 xclk = radeon_get_xclk(rdev); 6301 6302 if (rdev->pm.no_fan) 6303 return -ENOENT; 6304 6305 if (rdev->pm.fan_pulses_per_revolution == 0) 6306 return -ENOENT; 6307 6308 if ((speed < rdev->pm.fan_min_rpm) || 6309 (speed > rdev->pm.fan_max_rpm)) 6310 return -EINVAL; 6311 6312 if (rdev->pm.dpm.fan.ucode_fan_control) 6313 si_fan_ctrl_stop_smc_fan_control(rdev); 6314 6315 tach_period = 60 * xclk * 10000 / (8 * speed); 6316 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6317 tmp |= TARGET_PERIOD(tach_period); 6318 WREG32(CG_TACH_CTRL, tmp); 6319 6320 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6321 6322 return 0; 6323 } 6324 #endif 6325 6326 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6327 { 6328 struct si_power_info *si_pi = si_get_pi(rdev); 6329 u32 tmp; 6330 6331 if (!si_pi->fan_ctrl_is_in_default_mode) { 6332 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6333 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6334 WREG32(CG_FDO_CTRL2, tmp); 6335 6336 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6337 tmp |= TMIN(si_pi->t_min); 6338 WREG32(CG_FDO_CTRL2, tmp); 6339 si_pi->fan_ctrl_is_in_default_mode = true; 6340 } 6341 } 6342 6343 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6344 { 6345 if (rdev->pm.dpm.fan.ucode_fan_control) { 6346 si_fan_ctrl_start_smc_fan_control(rdev); 6347 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6348 } 6349 } 6350 6351 static void si_thermal_initialize(struct radeon_device *rdev) 6352 { 6353 u32 tmp; 6354 6355 if (rdev->pm.fan_pulses_per_revolution) { 6356 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6357 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6358 WREG32(CG_TACH_CTRL, tmp); 6359 } 6360 6361 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6362 tmp |= TACH_PWM_RESP_RATE(0x28); 6363 WREG32(CG_FDO_CTRL2, tmp); 6364 } 6365 6366 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6367 { 6368 int ret; 6369 6370 si_thermal_initialize(rdev); 6371 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6372 if (ret) 6373 return ret; 6374 ret = si_thermal_enable_alert(rdev, true); 6375 if (ret) 6376 return ret; 6377 if (rdev->pm.dpm.fan.ucode_fan_control) { 6378 ret = si_halt_smc(rdev); 6379 if (ret) 6380 return ret; 6381 ret = si_thermal_setup_fan_table(rdev); 6382 if (ret) 6383 return ret; 6384 ret = si_resume_smc(rdev); 6385 if (ret) 6386 return ret; 6387 si_thermal_start_smc_fan_control(rdev); 6388 } 6389 6390 return 0; 6391 } 6392 6393 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6394 { 6395 if (!rdev->pm.no_fan) { 6396 si_fan_ctrl_set_default_mode(rdev); 6397 si_fan_ctrl_stop_smc_fan_control(rdev); 6398 } 6399 } 6400 6401 int si_dpm_enable(struct radeon_device *rdev) 6402 { 6403 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6404 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6405 struct si_power_info *si_pi = si_get_pi(rdev); 6406 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6407 int ret; 6408 6409 if (si_is_smc_running(rdev)) 6410 return -EINVAL; 6411 if (pi->voltage_control || si_pi->voltage_control_svi2) 6412 si_enable_voltage_control(rdev, true); 6413 if (pi->mvdd_control) 6414 si_get_mvdd_configuration(rdev); 6415 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6416 ret = si_construct_voltage_tables(rdev); 6417 if (ret) { 6418 DRM_ERROR("si_construct_voltage_tables failed\n"); 6419 return ret; 6420 } 6421 } 6422 if (eg_pi->dynamic_ac_timing) { 6423 ret = si_initialize_mc_reg_table(rdev); 6424 if (ret) 6425 eg_pi->dynamic_ac_timing = false; 6426 } 6427 if (pi->dynamic_ss) 6428 si_enable_spread_spectrum(rdev, true); 6429 if (pi->thermal_protection) 6430 si_enable_thermal_protection(rdev, true); 6431 si_setup_bsp(rdev); 6432 si_program_git(rdev); 6433 si_program_tp(rdev); 6434 si_program_tpp(rdev); 6435 si_program_sstp(rdev); 6436 si_enable_display_gap(rdev); 6437 si_program_vc(rdev); 6438 ret = si_upload_firmware(rdev); 6439 if (ret) { 6440 DRM_ERROR("si_upload_firmware failed\n"); 6441 return ret; 6442 } 6443 ret = si_process_firmware_header(rdev); 6444 if (ret) { 6445 DRM_ERROR("si_process_firmware_header failed\n"); 6446 return ret; 6447 } 6448 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6449 if (ret) { 6450 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6451 return ret; 6452 } 6453 ret = si_init_smc_table(rdev); 6454 if (ret) { 6455 DRM_ERROR("si_init_smc_table failed\n"); 6456 return ret; 6457 } 6458 ret = si_init_smc_spll_table(rdev); 6459 if (ret) { 6460 DRM_ERROR("si_init_smc_spll_table failed\n"); 6461 return ret; 6462 } 6463 ret = si_init_arb_table_index(rdev); 6464 if (ret) { 6465 DRM_ERROR("si_init_arb_table_index failed\n"); 6466 return ret; 6467 } 6468 if (eg_pi->dynamic_ac_timing) { 6469 ret = si_populate_mc_reg_table(rdev, boot_ps); 6470 if (ret) { 6471 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6472 return ret; 6473 } 6474 } 6475 ret = si_initialize_smc_cac_tables(rdev); 6476 if (ret) { 6477 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6478 return ret; 6479 } 6480 ret = si_initialize_hardware_cac_manager(rdev); 6481 if (ret) { 6482 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6483 return ret; 6484 } 6485 ret = si_initialize_smc_dte_tables(rdev); 6486 if (ret) { 6487 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6488 return ret; 6489 } 6490 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6491 if (ret) { 6492 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6493 return ret; 6494 } 6495 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6496 if (ret) { 6497 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6498 return ret; 6499 } 6500 si_program_response_times(rdev); 6501 si_program_ds_registers(rdev); 6502 si_dpm_start_smc(rdev); 6503 ret = si_notify_smc_display_change(rdev, false); 6504 if (ret) { 6505 DRM_ERROR("si_notify_smc_display_change failed\n"); 6506 return ret; 6507 } 6508 si_enable_sclk_control(rdev, true); 6509 si_start_dpm(rdev); 6510 6511 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6512 6513 si_thermal_start_thermal_controller(rdev); 6514 6515 ni_update_current_ps(rdev, boot_ps); 6516 6517 return 0; 6518 } 6519 6520 static int si_set_temperature_range(struct radeon_device *rdev) 6521 { 6522 int ret; 6523 6524 ret = si_thermal_enable_alert(rdev, false); 6525 if (ret) 6526 return ret; 6527 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6528 if (ret) 6529 return ret; 6530 ret = si_thermal_enable_alert(rdev, true); 6531 if (ret) 6532 return ret; 6533 6534 return ret; 6535 } 6536 6537 int si_dpm_late_enable(struct radeon_device *rdev) 6538 { 6539 int ret; 6540 6541 ret = si_set_temperature_range(rdev); 6542 if (ret) 6543 return ret; 6544 6545 return ret; 6546 } 6547 6548 void si_dpm_disable(struct radeon_device *rdev) 6549 { 6550 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6551 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6552 6553 if (!si_is_smc_running(rdev)) 6554 return; 6555 si_thermal_stop_thermal_controller(rdev); 6556 si_disable_ulv(rdev); 6557 si_clear_vc(rdev); 6558 if (pi->thermal_protection) 6559 si_enable_thermal_protection(rdev, false); 6560 si_enable_power_containment(rdev, boot_ps, false); 6561 si_enable_smc_cac(rdev, boot_ps, false); 6562 si_enable_spread_spectrum(rdev, false); 6563 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6564 si_stop_dpm(rdev); 6565 si_reset_to_default(rdev); 6566 si_dpm_stop_smc(rdev); 6567 si_force_switch_to_arb_f0(rdev); 6568 6569 ni_update_current_ps(rdev, boot_ps); 6570 } 6571 6572 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6573 { 6574 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6575 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6576 struct radeon_ps *new_ps = &requested_ps; 6577 6578 ni_update_requested_ps(rdev, new_ps); 6579 6580 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6581 6582 return 0; 6583 } 6584 6585 static int si_power_control_set_level(struct radeon_device *rdev) 6586 { 6587 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6588 int ret; 6589 6590 ret = si_restrict_performance_levels_before_switch(rdev); 6591 if (ret) 6592 return ret; 6593 ret = si_halt_smc(rdev); 6594 if (ret) 6595 return ret; 6596 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6597 if (ret) 6598 return ret; 6599 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6600 if (ret) 6601 return ret; 6602 ret = si_resume_smc(rdev); 6603 if (ret) 6604 return ret; 6605 ret = si_set_sw_state(rdev); 6606 if (ret) 6607 return ret; 6608 return 0; 6609 } 6610 6611 int si_dpm_set_power_state(struct radeon_device *rdev) 6612 { 6613 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6614 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6615 struct radeon_ps *old_ps = &eg_pi->current_rps; 6616 int ret; 6617 6618 ret = si_disable_ulv(rdev); 6619 if (ret) { 6620 DRM_ERROR("si_disable_ulv failed\n"); 6621 return ret; 6622 } 6623 ret = si_restrict_performance_levels_before_switch(rdev); 6624 if (ret) { 6625 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6626 return ret; 6627 } 6628 if (eg_pi->pcie_performance_request) 6629 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6630 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6631 ret = si_enable_power_containment(rdev, new_ps, false); 6632 if (ret) { 6633 DRM_ERROR("si_enable_power_containment failed\n"); 6634 return ret; 6635 } 6636 ret = si_enable_smc_cac(rdev, new_ps, false); 6637 if (ret) { 6638 DRM_ERROR("si_enable_smc_cac failed\n"); 6639 return ret; 6640 } 6641 ret = si_halt_smc(rdev); 6642 if (ret) { 6643 DRM_ERROR("si_halt_smc failed\n"); 6644 return ret; 6645 } 6646 ret = si_upload_sw_state(rdev, new_ps); 6647 if (ret) { 6648 DRM_ERROR("si_upload_sw_state failed\n"); 6649 return ret; 6650 } 6651 ret = si_upload_smc_data(rdev); 6652 if (ret) { 6653 DRM_ERROR("si_upload_smc_data failed\n"); 6654 return ret; 6655 } 6656 ret = si_upload_ulv_state(rdev); 6657 if (ret) { 6658 DRM_ERROR("si_upload_ulv_state failed\n"); 6659 return ret; 6660 } 6661 if (eg_pi->dynamic_ac_timing) { 6662 ret = si_upload_mc_reg_table(rdev, new_ps); 6663 if (ret) { 6664 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6665 return ret; 6666 } 6667 } 6668 ret = si_program_memory_timing_parameters(rdev, new_ps); 6669 if (ret) { 6670 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6671 return ret; 6672 } 6673 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6674 6675 ret = si_resume_smc(rdev); 6676 if (ret) { 6677 DRM_ERROR("si_resume_smc failed\n"); 6678 return ret; 6679 } 6680 ret = si_set_sw_state(rdev); 6681 if (ret) { 6682 DRM_ERROR("si_set_sw_state failed\n"); 6683 return ret; 6684 } 6685 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6686 si_set_vce_clock(rdev, new_ps, old_ps); 6687 if (eg_pi->pcie_performance_request) 6688 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6689 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6690 if (ret) { 6691 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6692 return ret; 6693 } 6694 ret = si_enable_smc_cac(rdev, new_ps, true); 6695 if (ret) { 6696 DRM_ERROR("si_enable_smc_cac failed\n"); 6697 return ret; 6698 } 6699 ret = si_enable_power_containment(rdev, new_ps, true); 6700 if (ret) { 6701 DRM_ERROR("si_enable_power_containment failed\n"); 6702 return ret; 6703 } 6704 6705 ret = si_power_control_set_level(rdev); 6706 if (ret) { 6707 DRM_ERROR("si_power_control_set_level failed\n"); 6708 return ret; 6709 } 6710 6711 return 0; 6712 } 6713 6714 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6715 { 6716 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6717 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6718 6719 ni_update_current_ps(rdev, new_ps); 6720 } 6721 6722 #if 0 6723 void si_dpm_reset_asic(struct radeon_device *rdev) 6724 { 6725 si_restrict_performance_levels_before_switch(rdev); 6726 si_disable_ulv(rdev); 6727 si_set_boot_state(rdev); 6728 } 6729 #endif 6730 6731 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6732 { 6733 si_program_display_gap(rdev); 6734 } 6735 6736 union power_info { 6737 struct _ATOM_POWERPLAY_INFO info; 6738 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6739 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6740 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6741 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6742 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6743 }; 6744 6745 union pplib_clock_info { 6746 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6747 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6748 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6749 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6750 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6751 }; 6752 6753 union pplib_power_state { 6754 struct _ATOM_PPLIB_STATE v1; 6755 struct _ATOM_PPLIB_STATE_V2 v2; 6756 }; 6757 6758 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6759 struct radeon_ps *rps, 6760 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6761 u8 table_rev) 6762 { 6763 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6764 rps->class = le16_to_cpu(non_clock_info->usClassification); 6765 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6766 6767 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6768 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6769 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6770 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6771 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6772 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6773 } else { 6774 rps->vclk = 0; 6775 rps->dclk = 0; 6776 } 6777 6778 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6779 rdev->pm.dpm.boot_ps = rps; 6780 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6781 rdev->pm.dpm.uvd_ps = rps; 6782 } 6783 6784 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6785 struct radeon_ps *rps, int index, 6786 union pplib_clock_info *clock_info) 6787 { 6788 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6789 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6790 struct si_power_info *si_pi = si_get_pi(rdev); 6791 struct ni_ps *ps = ni_get_ps(rps); 6792 u16 leakage_voltage; 6793 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6794 int ret; 6795 6796 ps->performance_level_count = index + 1; 6797 6798 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6799 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6800 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6801 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6802 6803 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6804 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6805 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6806 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6807 si_pi->sys_pcie_mask, 6808 si_pi->boot_pcie_gen, 6809 clock_info->si.ucPCIEGen); 6810 6811 /* patch up vddc if necessary */ 6812 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6813 &leakage_voltage); 6814 if (ret == 0) 6815 pl->vddc = leakage_voltage; 6816 6817 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6818 pi->acpi_vddc = pl->vddc; 6819 eg_pi->acpi_vddci = pl->vddci; 6820 si_pi->acpi_pcie_gen = pl->pcie_gen; 6821 } 6822 6823 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6824 index == 0) { 6825 /* XXX disable for A0 tahiti */ 6826 si_pi->ulv.supported = false; 6827 si_pi->ulv.pl = *pl; 6828 si_pi->ulv.one_pcie_lane_in_ulv = false; 6829 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6830 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6831 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6832 } 6833 6834 if (pi->min_vddc_in_table > pl->vddc) 6835 pi->min_vddc_in_table = pl->vddc; 6836 6837 if (pi->max_vddc_in_table < pl->vddc) 6838 pi->max_vddc_in_table = pl->vddc; 6839 6840 /* patch up boot state */ 6841 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6842 u16 vddc, vddci, mvdd; 6843 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6844 pl->mclk = rdev->clock.default_mclk; 6845 pl->sclk = rdev->clock.default_sclk; 6846 pl->vddc = vddc; 6847 pl->vddci = vddci; 6848 si_pi->mvdd_bootup_value = mvdd; 6849 } 6850 6851 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6852 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6853 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6854 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6855 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6856 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6857 } 6858 } 6859 6860 static int si_parse_power_table(struct radeon_device *rdev) 6861 { 6862 struct radeon_mode_info *mode_info = &rdev->mode_info; 6863 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6864 union pplib_power_state *power_state; 6865 int i, j, k, non_clock_array_index, clock_array_index; 6866 union pplib_clock_info *clock_info; 6867 struct _StateArray *state_array; 6868 struct _ClockInfoArray *clock_info_array; 6869 struct _NonClockInfoArray *non_clock_info_array; 6870 union power_info *power_info; 6871 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6872 u16 data_offset; 6873 u8 frev, crev; 6874 u8 *power_state_offset; 6875 struct ni_ps *ps; 6876 6877 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6878 &frev, &crev, &data_offset)) 6879 return -EINVAL; 6880 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6881 6882 state_array = (struct _StateArray *) 6883 (mode_info->atom_context->bios + data_offset + 6884 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6885 clock_info_array = (struct _ClockInfoArray *) 6886 (mode_info->atom_context->bios + data_offset + 6887 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6888 non_clock_info_array = (struct _NonClockInfoArray *) 6889 (mode_info->atom_context->bios + data_offset + 6890 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6891 6892 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6893 state_array->ucNumEntries, GFP_KERNEL); 6894 if (!rdev->pm.dpm.ps) 6895 return -ENOMEM; 6896 power_state_offset = (u8 *)state_array->states; 6897 for (i = 0; i < state_array->ucNumEntries; i++) { 6898 u8 *idx; 6899 power_state = (union pplib_power_state *)power_state_offset; 6900 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6901 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6902 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6903 if (!rdev->pm.power_state[i].clock_info) 6904 return -EINVAL; 6905 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6906 if (ps == NULL) { 6907 kfree(rdev->pm.dpm.ps); 6908 return -ENOMEM; 6909 } 6910 rdev->pm.dpm.ps[i].ps_priv = ps; 6911 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6912 non_clock_info, 6913 non_clock_info_array->ucEntrySize); 6914 k = 0; 6915 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6916 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6917 clock_array_index = idx[j]; 6918 if (clock_array_index >= clock_info_array->ucNumEntries) 6919 continue; 6920 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6921 break; 6922 clock_info = (union pplib_clock_info *) 6923 ((u8 *)&clock_info_array->clockInfo[0] + 6924 (clock_array_index * clock_info_array->ucEntrySize)); 6925 si_parse_pplib_clock_info(rdev, 6926 &rdev->pm.dpm.ps[i], k, 6927 clock_info); 6928 k++; 6929 } 6930 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6931 } 6932 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6933 6934 /* fill in the vce power states */ 6935 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6936 u32 sclk, mclk; 6937 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6938 clock_info = (union pplib_clock_info *) 6939 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6940 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6941 sclk |= clock_info->si.ucEngineClockHigh << 16; 6942 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6943 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6944 rdev->pm.dpm.vce_states[i].sclk = sclk; 6945 rdev->pm.dpm.vce_states[i].mclk = mclk; 6946 } 6947 6948 return 0; 6949 } 6950 6951 int si_dpm_init(struct radeon_device *rdev) 6952 { 6953 struct rv7xx_power_info *pi; 6954 struct evergreen_power_info *eg_pi; 6955 struct ni_power_info *ni_pi; 6956 struct si_power_info *si_pi; 6957 struct atom_clock_dividers dividers; 6958 int ret; 6959 u32 mask; 6960 6961 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6962 if (si_pi == NULL) 6963 return -ENOMEM; 6964 rdev->pm.dpm.priv = si_pi; 6965 ni_pi = &si_pi->ni; 6966 eg_pi = &ni_pi->eg; 6967 pi = &eg_pi->rv7xx; 6968 6969 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6970 if (ret) 6971 si_pi->sys_pcie_mask = 0; 6972 else 6973 si_pi->sys_pcie_mask = mask; 6974 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6975 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6976 6977 si_set_max_cu_value(rdev); 6978 6979 rv770_get_max_vddc(rdev); 6980 si_get_leakage_vddc(rdev); 6981 si_patch_dependency_tables_based_on_leakage(rdev); 6982 6983 pi->acpi_vddc = 0; 6984 eg_pi->acpi_vddci = 0; 6985 pi->min_vddc_in_table = 0; 6986 pi->max_vddc_in_table = 0; 6987 6988 ret = r600_get_platform_caps(rdev); 6989 if (ret) 6990 return ret; 6991 6992 ret = r600_parse_extended_power_table(rdev); 6993 if (ret) 6994 return ret; 6995 6996 ret = si_parse_power_table(rdev); 6997 if (ret) 6998 return ret; 6999 7000 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7001 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 7002 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 7003 r600_free_extended_power_table(rdev); 7004 return -ENOMEM; 7005 } 7006 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7007 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7008 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7009 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7010 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7011 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7012 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7013 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7014 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7015 7016 if (rdev->pm.dpm.voltage_response_time == 0) 7017 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7018 if (rdev->pm.dpm.backbias_response_time == 0) 7019 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7020 7021 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 7022 0, false, ÷rs); 7023 if (ret) 7024 pi->ref_div = dividers.ref_div + 1; 7025 else 7026 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7027 7028 eg_pi->smu_uvd_hs = false; 7029 7030 pi->mclk_strobe_mode_threshold = 40000; 7031 if (si_is_special_1gb_platform(rdev)) 7032 pi->mclk_stutter_mode_threshold = 0; 7033 else 7034 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7035 pi->mclk_edc_enable_threshold = 40000; 7036 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7037 7038 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7039 7040 pi->voltage_control = 7041 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7042 VOLTAGE_OBJ_GPIO_LUT); 7043 if (!pi->voltage_control) { 7044 si_pi->voltage_control_svi2 = 7045 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7046 VOLTAGE_OBJ_SVID2); 7047 if (si_pi->voltage_control_svi2) 7048 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7049 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7050 } 7051 7052 pi->mvdd_control = 7053 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7054 VOLTAGE_OBJ_GPIO_LUT); 7055 7056 eg_pi->vddci_control = 7057 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7058 VOLTAGE_OBJ_GPIO_LUT); 7059 if (!eg_pi->vddci_control) 7060 si_pi->vddci_control_svi2 = 7061 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7062 VOLTAGE_OBJ_SVID2); 7063 7064 si_pi->vddc_phase_shed_control = 7065 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7066 VOLTAGE_OBJ_PHASE_LUT); 7067 7068 rv770_get_engine_memory_ss(rdev); 7069 7070 pi->asi = RV770_ASI_DFLT; 7071 pi->pasi = CYPRESS_HASI_DFLT; 7072 pi->vrc = SISLANDS_VRC_DFLT; 7073 7074 pi->gfx_clock_gating = true; 7075 7076 eg_pi->sclk_deep_sleep = true; 7077 si_pi->sclk_deep_sleep_above_low = false; 7078 7079 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7080 pi->thermal_protection = true; 7081 else 7082 pi->thermal_protection = false; 7083 7084 eg_pi->dynamic_ac_timing = true; 7085 7086 eg_pi->light_sleep = true; 7087 #if defined(CONFIG_ACPI) 7088 eg_pi->pcie_performance_request = 7089 radeon_acpi_is_pcie_performance_request_supported(rdev); 7090 #else 7091 eg_pi->pcie_performance_request = false; 7092 #endif 7093 7094 si_pi->sram_end = SMC_RAM_END; 7095 7096 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7097 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7098 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7099 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7100 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7101 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7102 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7103 7104 si_initialize_powertune_defaults(rdev); 7105 7106 /* make sure dc limits are valid */ 7107 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7108 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7109 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7110 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7111 7112 si_pi->fan_ctrl_is_in_default_mode = true; 7113 7114 return 0; 7115 } 7116 7117 void si_dpm_fini(struct radeon_device *rdev) 7118 { 7119 int i; 7120 7121 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7122 kfree(rdev->pm.dpm.ps[i].ps_priv); 7123 } 7124 kfree(rdev->pm.dpm.ps); 7125 kfree(rdev->pm.dpm.priv); 7126 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7127 r600_free_extended_power_table(rdev); 7128 } 7129 7130 #ifdef CONFIG_DEBUG_FS 7131 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7132 struct seq_file *m) 7133 { 7134 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7135 struct radeon_ps *rps = &eg_pi->current_rps; 7136 struct ni_ps *ps = ni_get_ps(rps); 7137 struct rv7xx_pl *pl; 7138 u32 current_index = 7139 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7140 CURRENT_STATE_INDEX_SHIFT; 7141 7142 if (current_index >= ps->performance_level_count) { 7143 seq_printf(m, "invalid dpm profile %d\n", current_index); 7144 } else { 7145 pl = &ps->performance_levels[current_index]; 7146 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7147 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7148 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7149 } 7150 } 7151 #endif 7152 7153 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7154 { 7155 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7156 struct radeon_ps *rps = &eg_pi->current_rps; 7157 struct ni_ps *ps = ni_get_ps(rps); 7158 struct rv7xx_pl *pl; 7159 u32 current_index = 7160 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7161 CURRENT_STATE_INDEX_SHIFT; 7162 7163 if (current_index >= ps->performance_level_count) { 7164 return 0; 7165 } else { 7166 pl = &ps->performance_levels[current_index]; 7167 return pl->sclk; 7168 } 7169 } 7170 7171 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7172 { 7173 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7174 struct radeon_ps *rps = &eg_pi->current_rps; 7175 struct ni_ps *ps = ni_get_ps(rps); 7176 struct rv7xx_pl *pl; 7177 u32 current_index = 7178 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7179 CURRENT_STATE_INDEX_SHIFT; 7180 7181 if (current_index >= ps->performance_level_count) { 7182 return 0; 7183 } else { 7184 pl = &ps->performance_levels[current_index]; 7185 return pl->mclk; 7186 } 7187 } 7188
Indexes created Sat Oct 25 16:10:12 GMT 2025