1 /* $NetBSD: radeon_si_smc.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: radeon_si_smc.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $"); 29 30 #include <linux/firmware.h> 31 32 #include "radeon.h" 33 #include "sid.h" 34 #include "ppsmc.h" 35 #include "radeon_ucode.h" 36 #include "sislands_smc.h" 37 38 static int si_set_smc_sram_address(struct radeon_device *rdev, 39 u32 smc_address, u32 limit) 40 { 41 if (smc_address & 3) 42 return -EINVAL; 43 if ((smc_address + 3) > limit) 44 return -EINVAL; 45 46 WREG32(SMC_IND_INDEX_0, smc_address); 47 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 48 49 return 0; 50 } 51 52 int si_copy_bytes_to_smc(struct radeon_device *rdev, 53 u32 smc_start_address, 54 const u8 *src, u32 byte_count, u32 limit) 55 { 56 unsigned long flags; 57 int ret = 0; 58 u32 data, original_data, addr, extra_shift; 59 60 if (smc_start_address & 3) 61 return -EINVAL; 62 if ((smc_start_address + byte_count) > limit) 63 return -EINVAL; 64 65 addr = smc_start_address; 66 67 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 68 while (byte_count >= 4) { 69 /* SMC address space is BE */ 70 data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 71 72 ret = si_set_smc_sram_address(rdev, addr, limit); 73 if (ret) 74 goto done; 75 76 WREG32(SMC_IND_DATA_0, data); 77 78 src += 4; 79 byte_count -= 4; 80 addr += 4; 81 } 82 83 /* RMW for the final bytes */ 84 if (byte_count > 0) { 85 data = 0; 86 87 ret = si_set_smc_sram_address(rdev, addr, limit); 88 if (ret) 89 goto done; 90 91 original_data = RREG32(SMC_IND_DATA_0); 92 93 extra_shift = 8 * (4 - byte_count); 94 95 while (byte_count > 0) { 96 /* SMC address space is BE */ 97 data = (data << 8) + *src++; 98 byte_count--; 99 } 100 101 data <<= extra_shift; 102 103 data |= (original_data & ~((~0UL) << extra_shift)); 104 105 ret = si_set_smc_sram_address(rdev, addr, limit); 106 if (ret) 107 goto done; 108 109 WREG32(SMC_IND_DATA_0, data); 110 } 111 112 done: 113 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 114 115 return ret; 116 } 117 118 void si_start_smc(struct radeon_device *rdev) 119 { 120 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 121 122 tmp &= ~RST_REG; 123 124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 125 } 126 127 void si_reset_smc(struct radeon_device *rdev) 128 { 129 u32 tmp; 130 131 RREG32(CB_CGTT_SCLK_CTRL); 132 RREG32(CB_CGTT_SCLK_CTRL); 133 RREG32(CB_CGTT_SCLK_CTRL); 134 RREG32(CB_CGTT_SCLK_CTRL); 135 136 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 137 tmp |= RST_REG; 138 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); 139 } 140 141 int si_program_jump_on_start(struct radeon_device *rdev) 142 { 143 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 }; 144 145 return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1); 146 } 147 148 void si_stop_smc_clock(struct radeon_device *rdev) 149 { 150 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 151 152 tmp |= CK_DISABLE; 153 154 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 155 } 156 157 void si_start_smc_clock(struct radeon_device *rdev) 158 { 159 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 160 161 tmp &= ~CK_DISABLE; 162 163 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); 164 } 165 166 bool si_is_smc_running(struct radeon_device *rdev) 167 { 168 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); 169 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 170 171 if (!(rst & RST_REG) && !(clk & CK_DISABLE)) 172 return true; 173 174 return false; 175 } 176 177 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) 178 { 179 u32 tmp; 180 int i; 181 182 if (!si_is_smc_running(rdev)) 183 return PPSMC_Result_Failed; 184 185 WREG32(SMC_MESSAGE_0, msg); 186 187 for (i = 0; i < rdev->usec_timeout; i++) { 188 tmp = RREG32(SMC_RESP_0); 189 if (tmp != 0) 190 break; 191 udelay(1); 192 } 193 tmp = RREG32(SMC_RESP_0); 194 195 return (PPSMC_Result)tmp; 196 } 197 198 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev) 199 { 200 u32 tmp; 201 int i; 202 203 if (!si_is_smc_running(rdev)) 204 return PPSMC_Result_OK; 205 206 for (i = 0; i < rdev->usec_timeout; i++) { 207 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); 208 if ((tmp & CKEN) == 0) 209 break; 210 udelay(1); 211 } 212 213 return PPSMC_Result_OK; 214 } 215 216 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) 217 { 218 unsigned long flags; 219 u32 ucode_start_address; 220 u32 ucode_size; 221 const u8 *src; 222 u32 data; 223 224 if (!rdev->smc_fw) 225 return -EINVAL; 226 227 if (rdev->new_fw) { 228 const struct smc_firmware_header_v1_0 *hdr = 229 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data; 230 231 radeon_ucode_print_smc_hdr(&hdr->header); 232 233 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); 234 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 235 src = (const u8 *) 236 (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 237 } else { 238 switch (rdev->family) { 239 case CHIP_TAHITI: 240 ucode_start_address = TAHITI_SMC_UCODE_START; 241 ucode_size = TAHITI_SMC_UCODE_SIZE; 242 break; 243 case CHIP_PITCAIRN: 244 ucode_start_address = PITCAIRN_SMC_UCODE_START; 245 ucode_size = PITCAIRN_SMC_UCODE_SIZE; 246 break; 247 case CHIP_VERDE: 248 ucode_start_address = VERDE_SMC_UCODE_START; 249 ucode_size = VERDE_SMC_UCODE_SIZE; 250 break; 251 case CHIP_OLAND: 252 ucode_start_address = OLAND_SMC_UCODE_START; 253 ucode_size = OLAND_SMC_UCODE_SIZE; 254 break; 255 case CHIP_HAINAN: 256 ucode_start_address = HAINAN_SMC_UCODE_START; 257 ucode_size = HAINAN_SMC_UCODE_SIZE; 258 break; 259 default: 260 DRM_ERROR("unknown asic in smc ucode loader\n"); 261 BUG(); 262 } 263 src = (const u8 *)rdev->smc_fw->data; 264 } 265 266 if (ucode_size & 3) 267 return -EINVAL; 268 269 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 270 WREG32(SMC_IND_INDEX_0, ucode_start_address); 271 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); 272 while (ucode_size >= 4) { 273 /* SMC address space is BE */ 274 data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; 275 276 WREG32(SMC_IND_DATA_0, data); 277 278 src += 4; 279 ucode_size -= 4; 280 } 281 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); 282 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 283 284 return 0; 285 } 286 287 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 288 u32 *value, u32 limit) 289 { 290 unsigned long flags; 291 int ret; 292 293 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 294 ret = si_set_smc_sram_address(rdev, smc_address, limit); 295 if (ret == 0) 296 *value = RREG32(SMC_IND_DATA_0); 297 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 298 299 return ret; 300 } 301 302 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, 303 u32 value, u32 limit) 304 { 305 unsigned long flags; 306 int ret; 307 308 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 309 ret = si_set_smc_sram_address(rdev, smc_address, limit); 310 if (ret == 0) 311 WREG32(SMC_IND_DATA_0, value); 312 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 313 314 return ret; 315 } 316
Indexes created Sat Sep 20 22:09:52 GMT 2025