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      1 /*	$NetBSD: rv740d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2011 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef RV740_H
     26 #define RV740_H
     27 
     28 #define	CG_SPLL_FUNC_CNTL				0x600
     29 #define		SPLL_RESET				(1 << 0)
     30 #define		SPLL_SLEEP				(1 << 1)
     31 #define		SPLL_BYPASS_EN				(1 << 3)
     32 #define		SPLL_REF_DIV(x)				((x) << 4)
     33 #define		SPLL_REF_DIV_MASK			(0x3f << 4)
     34 #define		SPLL_PDIV_A(x)				((x) << 20)
     35 #define		SPLL_PDIV_A_MASK			(0x7f << 20)
     36 #define	CG_SPLL_FUNC_CNTL_2				0x604
     37 #define		SCLK_MUX_SEL(x)				((x) << 0)
     38 #define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
     39 #define	CG_SPLL_FUNC_CNTL_3				0x608
     40 #define		SPLL_FB_DIV(x)				((x) << 0)
     41 #define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
     42 #define		SPLL_DITHEN				(1 << 28)
     43 
     44 #define	MPLL_CNTL_MODE					0x61c
     45 #define		SS_SSEN					(1 << 24)
     46 
     47 #define	MPLL_AD_FUNC_CNTL				0x624
     48 #define		CLKF(x)					((x) << 0)
     49 #define		CLKF_MASK				(0x7f << 0)
     50 #define		CLKR(x)					((x) << 7)
     51 #define		CLKR_MASK				(0x1f << 7)
     52 #define		CLKFRAC(x)				((x) << 12)
     53 #define		CLKFRAC_MASK				(0x1f << 12)
     54 #define		YCLK_POST_DIV(x)			((x) << 17)
     55 #define		YCLK_POST_DIV_MASK			(3 << 17)
     56 #define		IBIAS(x)				((x) << 20)
     57 #define		IBIAS_MASK				(0x3ff << 20)
     58 #define		RESET					(1 << 30)
     59 #define		PDNB					(1 << 31)
     60 #define	MPLL_AD_FUNC_CNTL_2				0x628
     61 #define		BYPASS					(1 << 19)
     62 #define		BIAS_GEN_PDNB				(1 << 24)
     63 #define		RESET_EN				(1 << 25)
     64 #define		VCO_MODE				(1 << 29)
     65 #define	MPLL_DQ_FUNC_CNTL				0x62c
     66 #define	MPLL_DQ_FUNC_CNTL_2				0x630
     67 
     68 #define	MCLK_PWRMGT_CNTL				0x648
     69 #define		DLL_SPEED(x)				((x) << 0)
     70 #define		DLL_SPEED_MASK				(0x1f << 0)
     71 #       define MPLL_PWRMGT_OFF                          (1 << 5)
     72 #       define DLL_READY                                (1 << 6)
     73 #       define MC_INT_CNTL                              (1 << 7)
     74 #       define MRDCKA0_SLEEP                            (1 << 8)
     75 #       define MRDCKA1_SLEEP                            (1 << 9)
     76 #       define MRDCKB0_SLEEP                            (1 << 10)
     77 #       define MRDCKB1_SLEEP                            (1 << 11)
     78 #       define MRDCKC0_SLEEP                            (1 << 12)
     79 #       define MRDCKC1_SLEEP                            (1 << 13)
     80 #       define MRDCKD0_SLEEP                            (1 << 14)
     81 #       define MRDCKD1_SLEEP                            (1 << 15)
     82 #       define MRDCKA0_RESET                            (1 << 16)
     83 #       define MRDCKA1_RESET                            (1 << 17)
     84 #       define MRDCKB0_RESET                            (1 << 18)
     85 #       define MRDCKB1_RESET                            (1 << 19)
     86 #       define MRDCKC0_RESET                            (1 << 20)
     87 #       define MRDCKC1_RESET                            (1 << 21)
     88 #       define MRDCKD0_RESET                            (1 << 22)
     89 #       define MRDCKD1_RESET                            (1 << 23)
     90 #       define DLL_READY_READ                           (1 << 24)
     91 #       define USE_DISPLAY_GAP                          (1 << 25)
     92 #       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)
     93 #       define MPLL_TURNOFF_D2                          (1 << 28)
     94 #define	DLL_CNTL					0x64c
     95 #       define MRDCKA0_BYPASS                           (1 << 24)
     96 #       define MRDCKA1_BYPASS                           (1 << 25)
     97 #       define MRDCKB0_BYPASS                           (1 << 26)
     98 #       define MRDCKB1_BYPASS                           (1 << 27)
     99 #       define MRDCKC0_BYPASS                           (1 << 28)
    100 #       define MRDCKC1_BYPASS                           (1 << 29)
    101 #       define MRDCKD0_BYPASS                           (1 << 30)
    102 #       define MRDCKD1_BYPASS                           (1 << 31)
    103 
    104 #define	CG_SPLL_SPREAD_SPECTRUM				0x790
    105 #define		SSEN					(1 << 0)
    106 #define		CLK_S(x)				((x) << 4)
    107 #define		CLK_S_MASK				(0xfff << 4)
    108 #define	CG_SPLL_SPREAD_SPECTRUM_2			0x794
    109 #define		CLK_V(x)				((x) << 0)
    110 #define		CLK_V_MASK				(0x3ffffff << 0)
    111 
    112 #define	MPLL_SS1					0x85c
    113 #define		CLKV(x)					((x) << 0)
    114 #define		CLKV_MASK				(0x3ffffff << 0)
    115 #define	MPLL_SS2					0x860
    116 #define		CLKS(x)					((x) << 0)
    117 #define		CLKS_MASK				(0xfff << 0)
    118 
    119 #endif
    120