rv740d.h revision 1.1.1.1.2.2
1 1.1.1.1.2.2 tls /* 2 1.1.1.1.2.2 tls * Copyright 2011 Advanced Micro Devices, Inc. 3 1.1.1.1.2.2 tls * 4 1.1.1.1.2.2 tls * Permission is hereby granted, free of charge, to any person obtaining a 5 1.1.1.1.2.2 tls * copy of this software and associated documentation files (the "Software"), 6 1.1.1.1.2.2 tls * to deal in the Software without restriction, including without limitation 7 1.1.1.1.2.2 tls * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 1.1.1.1.2.2 tls * and/or sell copies of the Software, and to permit persons to whom the 9 1.1.1.1.2.2 tls * Software is furnished to do so, subject to the following conditions: 10 1.1.1.1.2.2 tls * 11 1.1.1.1.2.2 tls * The above copyright notice and this permission notice shall be included in 12 1.1.1.1.2.2 tls * all copies or substantial portions of the Software. 13 1.1.1.1.2.2 tls * 14 1.1.1.1.2.2 tls * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 1.1.1.1.2.2 tls * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 1.1.1.1.2.2 tls * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 1.1.1.1.2.2 tls * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 1.1.1.1.2.2 tls * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 1.1.1.1.2.2 tls * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 1.1.1.1.2.2 tls * OTHER DEALINGS IN THE SOFTWARE. 21 1.1.1.1.2.2 tls * 22 1.1.1.1.2.2 tls */ 23 1.1.1.1.2.2 tls #ifndef RV740_H 24 1.1.1.1.2.2 tls #define RV740_H 25 1.1.1.1.2.2 tls 26 1.1.1.1.2.2 tls #define CG_SPLL_FUNC_CNTL 0x600 27 1.1.1.1.2.2 tls #define SPLL_RESET (1 << 0) 28 1.1.1.1.2.2 tls #define SPLL_SLEEP (1 << 1) 29 1.1.1.1.2.2 tls #define SPLL_BYPASS_EN (1 << 3) 30 1.1.1.1.2.2 tls #define SPLL_REF_DIV(x) ((x) << 4) 31 1.1.1.1.2.2 tls #define SPLL_REF_DIV_MASK (0x3f << 4) 32 1.1.1.1.2.2 tls #define SPLL_PDIV_A(x) ((x) << 20) 33 1.1.1.1.2.2 tls #define SPLL_PDIV_A_MASK (0x7f << 20) 34 1.1.1.1.2.2 tls #define CG_SPLL_FUNC_CNTL_2 0x604 35 1.1.1.1.2.2 tls #define SCLK_MUX_SEL(x) ((x) << 0) 36 1.1.1.1.2.2 tls #define SCLK_MUX_SEL_MASK (0x1ff << 0) 37 1.1.1.1.2.2 tls #define CG_SPLL_FUNC_CNTL_3 0x608 38 1.1.1.1.2.2 tls #define SPLL_FB_DIV(x) ((x) << 0) 39 1.1.1.1.2.2 tls #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 40 1.1.1.1.2.2 tls #define SPLL_DITHEN (1 << 28) 41 1.1.1.1.2.2 tls 42 1.1.1.1.2.2 tls #define MPLL_CNTL_MODE 0x61c 43 1.1.1.1.2.2 tls #define SS_SSEN (1 << 24) 44 1.1.1.1.2.2 tls 45 1.1.1.1.2.2 tls #define MPLL_AD_FUNC_CNTL 0x624 46 1.1.1.1.2.2 tls #define CLKF(x) ((x) << 0) 47 1.1.1.1.2.2 tls #define CLKF_MASK (0x7f << 0) 48 1.1.1.1.2.2 tls #define CLKR(x) ((x) << 7) 49 1.1.1.1.2.2 tls #define CLKR_MASK (0x1f << 7) 50 1.1.1.1.2.2 tls #define CLKFRAC(x) ((x) << 12) 51 1.1.1.1.2.2 tls #define CLKFRAC_MASK (0x1f << 12) 52 1.1.1.1.2.2 tls #define YCLK_POST_DIV(x) ((x) << 17) 53 1.1.1.1.2.2 tls #define YCLK_POST_DIV_MASK (3 << 17) 54 1.1.1.1.2.2 tls #define IBIAS(x) ((x) << 20) 55 1.1.1.1.2.2 tls #define IBIAS_MASK (0x3ff << 20) 56 1.1.1.1.2.2 tls #define RESET (1 << 30) 57 1.1.1.1.2.2 tls #define PDNB (1 << 31) 58 1.1.1.1.2.2 tls #define MPLL_AD_FUNC_CNTL_2 0x628 59 1.1.1.1.2.2 tls #define BYPASS (1 << 19) 60 1.1.1.1.2.2 tls #define BIAS_GEN_PDNB (1 << 24) 61 1.1.1.1.2.2 tls #define RESET_EN (1 << 25) 62 1.1.1.1.2.2 tls #define VCO_MODE (1 << 29) 63 1.1.1.1.2.2 tls #define MPLL_DQ_FUNC_CNTL 0x62c 64 1.1.1.1.2.2 tls #define MPLL_DQ_FUNC_CNTL_2 0x630 65 1.1.1.1.2.2 tls 66 1.1.1.1.2.2 tls #define MCLK_PWRMGT_CNTL 0x648 67 1.1.1.1.2.2 tls #define DLL_SPEED(x) ((x) << 0) 68 1.1.1.1.2.2 tls #define DLL_SPEED_MASK (0x1f << 0) 69 1.1.1.1.2.2 tls # define MPLL_PWRMGT_OFF (1 << 5) 70 1.1.1.1.2.2 tls # define DLL_READY (1 << 6) 71 1.1.1.1.2.2 tls # define MC_INT_CNTL (1 << 7) 72 1.1.1.1.2.2 tls # define MRDCKA0_SLEEP (1 << 8) 73 1.1.1.1.2.2 tls # define MRDCKA1_SLEEP (1 << 9) 74 1.1.1.1.2.2 tls # define MRDCKB0_SLEEP (1 << 10) 75 1.1.1.1.2.2 tls # define MRDCKB1_SLEEP (1 << 11) 76 1.1.1.1.2.2 tls # define MRDCKC0_SLEEP (1 << 12) 77 1.1.1.1.2.2 tls # define MRDCKC1_SLEEP (1 << 13) 78 1.1.1.1.2.2 tls # define MRDCKD0_SLEEP (1 << 14) 79 1.1.1.1.2.2 tls # define MRDCKD1_SLEEP (1 << 15) 80 1.1.1.1.2.2 tls # define MRDCKA0_RESET (1 << 16) 81 1.1.1.1.2.2 tls # define MRDCKA1_RESET (1 << 17) 82 1.1.1.1.2.2 tls # define MRDCKB0_RESET (1 << 18) 83 1.1.1.1.2.2 tls # define MRDCKB1_RESET (1 << 19) 84 1.1.1.1.2.2 tls # define MRDCKC0_RESET (1 << 20) 85 1.1.1.1.2.2 tls # define MRDCKC1_RESET (1 << 21) 86 1.1.1.1.2.2 tls # define MRDCKD0_RESET (1 << 22) 87 1.1.1.1.2.2 tls # define MRDCKD1_RESET (1 << 23) 88 1.1.1.1.2.2 tls # define DLL_READY_READ (1 << 24) 89 1.1.1.1.2.2 tls # define USE_DISPLAY_GAP (1 << 25) 90 1.1.1.1.2.2 tls # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 91 1.1.1.1.2.2 tls # define MPLL_TURNOFF_D2 (1 << 28) 92 1.1.1.1.2.2 tls #define DLL_CNTL 0x64c 93 1.1.1.1.2.2 tls # define MRDCKA0_BYPASS (1 << 24) 94 1.1.1.1.2.2 tls # define MRDCKA1_BYPASS (1 << 25) 95 1.1.1.1.2.2 tls # define MRDCKB0_BYPASS (1 << 26) 96 1.1.1.1.2.2 tls # define MRDCKB1_BYPASS (1 << 27) 97 1.1.1.1.2.2 tls # define MRDCKC0_BYPASS (1 << 28) 98 1.1.1.1.2.2 tls # define MRDCKC1_BYPASS (1 << 29) 99 1.1.1.1.2.2 tls # define MRDCKD0_BYPASS (1 << 30) 100 1.1.1.1.2.2 tls # define MRDCKD1_BYPASS (1 << 31) 101 1.1.1.1.2.2 tls 102 1.1.1.1.2.2 tls #define CG_SPLL_SPREAD_SPECTRUM 0x790 103 1.1.1.1.2.2 tls #define SSEN (1 << 0) 104 1.1.1.1.2.2 tls #define CLK_S(x) ((x) << 4) 105 1.1.1.1.2.2 tls #define CLK_S_MASK (0xfff << 4) 106 1.1.1.1.2.2 tls #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 107 1.1.1.1.2.2 tls #define CLK_V(x) ((x) << 0) 108 1.1.1.1.2.2 tls #define CLK_V_MASK (0x3ffffff << 0) 109 1.1.1.1.2.2 tls 110 1.1.1.1.2.2 tls #define MPLL_SS1 0x85c 111 1.1.1.1.2.2 tls #define CLKV(x) ((x) << 0) 112 1.1.1.1.2.2 tls #define CLKV_MASK (0x3ffffff << 0) 113 1.1.1.1.2.2 tls #define MPLL_SS2 0x860 114 1.1.1.1.2.2 tls #define CLKS(x) ((x) << 0) 115 1.1.1.1.2.2 tls #define CLKS_MASK (0xfff << 0) 116 1.1.1.1.2.2 tls 117 1.1.1.1.2.2 tls #endif 118
Indexes created Thu Oct 23 22:10:10 GMT 2025