smu7.h revision 1.1.1.1.2.2
1 1.1.1.1.2.2 tls /* 2 1.1.1.1.2.2 tls * Copyright 2013 Advanced Micro Devices, Inc. 3 1.1.1.1.2.2 tls * 4 1.1.1.1.2.2 tls * Permission is hereby granted, free of charge, to any person obtaining a 5 1.1.1.1.2.2 tls * copy of this software and associated documentation files (the "Software"), 6 1.1.1.1.2.2 tls * to deal in the Software without restriction, including without limitation 7 1.1.1.1.2.2 tls * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 1.1.1.1.2.2 tls * and/or sell copies of the Software, and to permit persons to whom the 9 1.1.1.1.2.2 tls * Software is furnished to do so, subject to the following conditions: 10 1.1.1.1.2.2 tls * 11 1.1.1.1.2.2 tls * The above copyright notice and this permission notice shall be included in 12 1.1.1.1.2.2 tls * all copies or substantial portions of the Software. 13 1.1.1.1.2.2 tls * 14 1.1.1.1.2.2 tls * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 1.1.1.1.2.2 tls * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 1.1.1.1.2.2 tls * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 1.1.1.1.2.2 tls * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 1.1.1.1.2.2 tls * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 1.1.1.1.2.2 tls * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 1.1.1.1.2.2 tls * OTHER DEALINGS IN THE SOFTWARE. 21 1.1.1.1.2.2 tls * 22 1.1.1.1.2.2 tls */ 23 1.1.1.1.2.2 tls 24 1.1.1.1.2.2 tls #ifndef SMU7_H 25 1.1.1.1.2.2 tls #define SMU7_H 26 1.1.1.1.2.2 tls 27 1.1.1.1.2.2 tls #pragma pack(push, 1) 28 1.1.1.1.2.2 tls 29 1.1.1.1.2.2 tls #define SMU7_CONTEXT_ID_SMC 1 30 1.1.1.1.2.2 tls #define SMU7_CONTEXT_ID_VBIOS 2 31 1.1.1.1.2.2 tls 32 1.1.1.1.2.2 tls 33 1.1.1.1.2.2 tls #define SMU7_CONTEXT_ID_SMC 1 34 1.1.1.1.2.2 tls #define SMU7_CONTEXT_ID_VBIOS 2 35 1.1.1.1.2.2 tls 36 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_VDDC 8 37 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_VDDCI 4 38 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_MVDD 4 39 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_VDDNB 8 40 1.1.1.1.2.2 tls 41 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 42 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 43 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 44 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 45 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 46 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 47 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 48 1.1.1.1.2.2 tls #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 49 1.1.1.1.2.2 tls #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 50 1.1.1.1.2.2 tls 51 1.1.1.1.2.2 tls #define DPM_NO_LIMIT 0 52 1.1.1.1.2.2 tls #define DPM_NO_UP 1 53 1.1.1.1.2.2 tls #define DPM_GO_DOWN 2 54 1.1.1.1.2.2 tls #define DPM_GO_UP 3 55 1.1.1.1.2.2 tls 56 1.1.1.1.2.2 tls #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 57 1.1.1.1.2.2 tls #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 58 1.1.1.1.2.2 tls 59 1.1.1.1.2.2 tls #define GPIO_CLAMP_MODE_VRHOT 1 60 1.1.1.1.2.2 tls #define GPIO_CLAMP_MODE_THERM 2 61 1.1.1.1.2.2 tls #define GPIO_CLAMP_MODE_DC 4 62 1.1.1.1.2.2 tls 63 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 64 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 65 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 66 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 67 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 68 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 69 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 70 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 71 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 72 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 73 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 74 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 75 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 76 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 77 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 78 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 79 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 80 1.1.1.1.2.2 tls #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 81 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 82 1.1.1.1.2.2 tls #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 83 1.1.1.1.2.2 tls 84 1.1.1.1.2.2 tls 85 1.1.1.1.2.2 tls struct SMU7_PIDController 86 1.1.1.1.2.2 tls { 87 1.1.1.1.2.2 tls uint32_t Ki; 88 1.1.1.1.2.2 tls int32_t LFWindupUL; 89 1.1.1.1.2.2 tls int32_t LFWindupLL; 90 1.1.1.1.2.2 tls uint32_t StatePrecision; 91 1.1.1.1.2.2 tls uint32_t LfPrecision; 92 1.1.1.1.2.2 tls uint32_t LfOffset; 93 1.1.1.1.2.2 tls uint32_t MaxState; 94 1.1.1.1.2.2 tls uint32_t MaxLfFraction; 95 1.1.1.1.2.2 tls uint32_t StateShift; 96 1.1.1.1.2.2 tls }; 97 1.1.1.1.2.2 tls 98 1.1.1.1.2.2 tls typedef struct SMU7_PIDController SMU7_PIDController; 99 1.1.1.1.2.2 tls 100 1.1.1.1.2.2 tls // ------------------------------------------------------------------------------------------------------------------------- 101 1.1.1.1.2.2 tls #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 102 1.1.1.1.2.2 tls 103 1.1.1.1.2.2 tls #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 104 1.1.1.1.2.2 tls #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 105 1.1.1.1.2.2 tls #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 106 1.1.1.1.2.2 tls #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 107 1.1.1.1.2.2 tls #define SMU7_UVD_DPM_CONFIG_MASK 0x10 108 1.1.1.1.2.2 tls #define SMU7_VCE_DPM_CONFIG_MASK 0x20 109 1.1.1.1.2.2 tls #define SMU7_ACP_DPM_CONFIG_MASK 0x40 110 1.1.1.1.2.2 tls #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 111 1.1.1.1.2.2 tls #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 112 1.1.1.1.2.2 tls 113 1.1.1.1.2.2 tls #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 114 1.1.1.1.2.2 tls #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 115 1.1.1.1.2.2 tls #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 116 1.1.1.1.2.2 tls #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 117 1.1.1.1.2.2 tls #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 118 1.1.1.1.2.2 tls #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 119 1.1.1.1.2.2 tls 120 1.1.1.1.2.2 tls struct SMU7_Firmware_Header 121 1.1.1.1.2.2 tls { 122 1.1.1.1.2.2 tls uint32_t Digest[5]; 123 1.1.1.1.2.2 tls uint32_t Version; 124 1.1.1.1.2.2 tls uint32_t HeaderSize; 125 1.1.1.1.2.2 tls uint32_t Flags; 126 1.1.1.1.2.2 tls uint32_t EntryPoint; 127 1.1.1.1.2.2 tls uint32_t CodeSize; 128 1.1.1.1.2.2 tls uint32_t ImageSize; 129 1.1.1.1.2.2 tls 130 1.1.1.1.2.2 tls uint32_t Rtos; 131 1.1.1.1.2.2 tls uint32_t SoftRegisters; 132 1.1.1.1.2.2 tls uint32_t DpmTable; 133 1.1.1.1.2.2 tls uint32_t FanTable; 134 1.1.1.1.2.2 tls uint32_t CacConfigTable; 135 1.1.1.1.2.2 tls uint32_t CacStatusTable; 136 1.1.1.1.2.2 tls 137 1.1.1.1.2.2 tls uint32_t mcRegisterTable; 138 1.1.1.1.2.2 tls 139 1.1.1.1.2.2 tls uint32_t mcArbDramTimingTable; 140 1.1.1.1.2.2 tls 141 1.1.1.1.2.2 tls uint32_t PmFuseTable; 142 1.1.1.1.2.2 tls uint32_t Globals; 143 1.1.1.1.2.2 tls uint32_t Reserved[42]; 144 1.1.1.1.2.2 tls uint32_t Signature; 145 1.1.1.1.2.2 tls }; 146 1.1.1.1.2.2 tls 147 1.1.1.1.2.2 tls typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 148 1.1.1.1.2.2 tls 149 1.1.1.1.2.2 tls #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 150 1.1.1.1.2.2 tls 151 1.1.1.1.2.2 tls enum DisplayConfig { 152 1.1.1.1.2.2 tls PowerDown = 1, 153 1.1.1.1.2.2 tls DP54x4, 154 1.1.1.1.2.2 tls DP54x2, 155 1.1.1.1.2.2 tls DP54x1, 156 1.1.1.1.2.2 tls DP27x4, 157 1.1.1.1.2.2 tls DP27x2, 158 1.1.1.1.2.2 tls DP27x1, 159 1.1.1.1.2.2 tls HDMI297, 160 1.1.1.1.2.2 tls HDMI162, 161 1.1.1.1.2.2 tls LVDS, 162 1.1.1.1.2.2 tls DP324x4, 163 1.1.1.1.2.2 tls DP324x2, 164 1.1.1.1.2.2 tls DP324x1 165 1.1.1.1.2.2 tls }; 166 1.1.1.1.2.2 tls 167 1.1.1.1.2.2 tls #pragma pack(pop) 168 1.1.1.1.2.2 tls 169 1.1.1.1.2.2 tls #endif 170 1.1.1.1.2.2 tls 171
Indexes created Thu Oct 23 22:10:10 GMT 2025