1 /* $NetBSD: drm.h,v 1.7 2021/12/20 12:56:07 riastradh Exp $ */ 2 3 /** 4 * \file drm.h 5 * Header for the Direct Rendering Manager 6 * 7 * \author Rickard E. (Rik) Faith <faith (at) valinux.com> 8 * 9 * \par Acknowledgments: 10 * Dec 1999, Richard Henderson <rth (at) twiddle.net>, move to generic \c cmpxchg. 11 */ 12 13 /* 14 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 15 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 16 * All rights reserved. 17 * 18 * Permission is hereby granted, free of charge, to any person obtaining a 19 * copy of this software and associated documentation files (the "Software"), 20 * to deal in the Software without restriction, including without limitation 21 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 22 * and/or sell copies of the Software, and to permit persons to whom the 23 * Software is furnished to do so, subject to the following conditions: 24 * 25 * The above copyright notice and this permission notice (including the next 26 * paragraph) shall be included in all copies or substantial portions of the 27 * Software. 28 * 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 32 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 33 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 34 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 35 * OTHER DEALINGS IN THE SOFTWARE. 36 */ 37 38 #ifndef _DRM_H_ 39 #define _DRM_H_ 40 41 #if defined(__linux__) && defined(__KERNEL__) 42 43 #include <linux/types.h> 44 #include <asm/ioctl.h> 45 typedef unsigned int drm_handle_t; 46 47 #elif defined(__linux__) 48 49 #include <linux/types.h> 50 #include <asm/ioctl.h> 51 52 /* XXX Why was this historically different between Linux and BSD? */ 53 typedef unsigned int drm_handle_t; 54 55 #endif 56 57 #ifdef __NetBSD__ 58 #include <sys/stdint.h> 59 #include <sys/ioccom.h> 60 #include <sys/types.h> 61 #include <sys/fcntl.h> 62 63 #ifdef _KERNEL 64 65 #include <sys/types.h> 66 #include <sys/file.h> 67 #define pipe pipe_drmhack /* see intel_display.h */ 68 69 #include <linux/types.h> 70 #include <asm/ioctl.h> 71 #else 72 typedef int8_t __s8; 73 typedef uint8_t __u8; 74 typedef int16_t __s16; 75 typedef uint16_t __u16; 76 typedef int32_t __s32; 77 typedef uint32_t __u32; 78 typedef int64_t __s64; 79 typedef uint64_t __u64; 80 81 #endif 82 # ifndef __user 83 # define __user 84 # endif 85 86 typedef size_t __kernel_size_t; 87 typedef unsigned long drm_handle_t; 88 89 #endif 90 91 #if defined(__cplusplus) 92 extern "C" { 93 #endif 94 95 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 96 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 97 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 98 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 99 100 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 101 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 102 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 103 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 104 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 105 106 typedef unsigned int drm_context_t; 107 typedef unsigned int drm_drawable_t; 108 typedef unsigned int drm_magic_t; 109 110 /** 111 * Cliprect. 112 * 113 * \warning: If you change this structure, make sure you change 114 * XF86DRIClipRectRec in the server as well 115 * 116 * \note KW: Actually it's illegal to change either for 117 * backwards-compatibility reasons. 118 */ 119 struct drm_clip_rect { 120 unsigned short x1; 121 unsigned short y1; 122 unsigned short x2; 123 unsigned short y2; 124 }; 125 126 /** 127 * Drawable information. 128 */ 129 struct drm_drawable_info { 130 unsigned int num_rects; 131 struct drm_clip_rect *rects; 132 }; 133 134 /** 135 * Texture region, 136 */ 137 struct drm_tex_region { 138 unsigned char next; 139 unsigned char prev; 140 unsigned char in_use; 141 unsigned char padding; 142 unsigned int age; 143 }; 144 145 /** 146 * Hardware lock. 147 * 148 * The lock structure is a simple cache-line aligned integer. To avoid 149 * processor bus contention on a multiprocessor system, there should not be any 150 * other data stored in the same cache line. 151 */ 152 struct drm_hw_lock { 153 __volatile__ unsigned int lock; /**< lock variable */ 154 char padding[60]; /**< Pad to cache line */ 155 }; 156 157 /** 158 * DRM_IOCTL_VERSION ioctl argument type. 159 * 160 * \sa drmGetVersion(). 161 */ 162 struct drm_version { 163 int version_major; /**< Major version */ 164 int version_minor; /**< Minor version */ 165 int version_patchlevel; /**< Patch level */ 166 __kernel_size_t name_len; /**< Length of name buffer */ 167 char __user *name; /**< Name of driver */ 168 __kernel_size_t date_len; /**< Length of date buffer */ 169 char __user *date; /**< User-space buffer to hold date */ 170 __kernel_size_t desc_len; /**< Length of desc buffer */ 171 char __user *desc; /**< User-space buffer to hold desc */ 172 }; 173 174 /** 175 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 176 * 177 * \sa drmGetBusid() and drmSetBusId(). 178 */ 179 struct drm_unique { 180 __kernel_size_t unique_len; /**< Length of unique */ 181 char __user *unique; /**< Unique name for driver instantiation */ 182 }; 183 184 struct drm_list { 185 int count; /**< Length of user-space structures */ 186 struct drm_version __user *version; 187 }; 188 189 struct drm_block { 190 int unused; 191 }; 192 193 /** 194 * DRM_IOCTL_CONTROL ioctl argument type. 195 * 196 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 197 */ 198 struct drm_control { 199 enum { 200 DRM_ADD_COMMAND, 201 DRM_RM_COMMAND, 202 DRM_INST_HANDLER, 203 DRM_UNINST_HANDLER 204 } func; 205 int irq; 206 }; 207 208 /** 209 * Type of memory to map. 210 */ 211 enum drm_map_type { 212 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 213 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 214 _DRM_SHM = 2, /**< shared, cached */ 215 _DRM_AGP = 3, /**< AGP/GART */ 216 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 217 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 218 }; 219 220 /** 221 * Memory mapping flags. 222 */ 223 enum drm_map_flags { 224 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 225 _DRM_READ_ONLY = 0x02, 226 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 227 _DRM_KERNEL = 0x08, /**< kernel requires access */ 228 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 229 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 230 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 231 _DRM_DRIVER = 0x80 /**< Managed by driver */ 232 }; 233 234 struct drm_ctx_priv_map { 235 unsigned int ctx_id; /**< Context requesting private mapping */ 236 void *handle; /**< Handle of map */ 237 }; 238 239 /** 240 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 241 * argument type. 242 * 243 * \sa drmAddMap(). 244 */ 245 struct drm_map { 246 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 247 unsigned long size; /**< Requested physical size (bytes) */ 248 enum drm_map_type type; /**< Type of memory to map */ 249 enum drm_map_flags flags; /**< Flags */ 250 void *handle; /**< User-space: "Handle" to pass to mmap() */ 251 /**< Kernel-space: kernel-virtual address */ 252 int mtrr; /**< MTRR slot used */ 253 /* Private data */ 254 }; 255 256 /** 257 * DRM_IOCTL_GET_CLIENT ioctl argument type. 258 */ 259 struct drm_client { 260 int idx; /**< Which client desired? */ 261 int auth; /**< Is client authenticated? */ 262 unsigned long pid; /**< Process ID */ 263 unsigned long uid; /**< User ID */ 264 unsigned long magic; /**< Magic */ 265 unsigned long iocs; /**< Ioctl count */ 266 }; 267 268 enum drm_stat_type { 269 _DRM_STAT_LOCK, 270 _DRM_STAT_OPENS, 271 _DRM_STAT_CLOSES, 272 _DRM_STAT_IOCTLS, 273 _DRM_STAT_LOCKS, 274 _DRM_STAT_UNLOCKS, 275 _DRM_STAT_VALUE, /**< Generic value */ 276 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 277 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 278 279 _DRM_STAT_IRQ, /**< IRQ */ 280 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 281 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 282 _DRM_STAT_DMA, /**< DMA */ 283 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 284 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 285 /* Add to the *END* of the list */ 286 }; 287 288 /** 289 * DRM_IOCTL_GET_STATS ioctl argument type. 290 */ 291 struct drm_stats { 292 unsigned long count; 293 struct { 294 unsigned long value; 295 enum drm_stat_type type; 296 } data[15]; 297 }; 298 299 /** 300 * Hardware locking flags. 301 */ 302 enum drm_lock_flags { 303 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 304 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 305 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 306 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 307 /* These *HALT* flags aren't supported yet 308 -- they will be used to support the 309 full-screen DGA-like mode. */ 310 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 311 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 312 }; 313 314 /** 315 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 316 * 317 * \sa drmGetLock() and drmUnlock(). 318 */ 319 struct drm_lock { 320 int context; 321 enum drm_lock_flags flags; 322 }; 323 324 /** 325 * DMA flags 326 * 327 * \warning 328 * These values \e must match xf86drm.h. 329 * 330 * \sa drm_dma. 331 */ 332 enum drm_dma_flags { 333 /* Flags for DMA buffer dispatch */ 334 _DRM_DMA_BLOCK = 0x01, /**< 335 * Block until buffer dispatched. 336 * 337 * \note The buffer may not yet have 338 * been processed by the hardware -- 339 * getting a hardware lock with the 340 * hardware quiescent will ensure 341 * that the buffer has been 342 * processed. 343 */ 344 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 345 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 346 347 /* Flags for DMA buffer request */ 348 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 349 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 350 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 351 }; 352 353 /** 354 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 355 * 356 * \sa drmAddBufs(). 357 */ 358 struct drm_buf_desc { 359 int count; /**< Number of buffers of this size */ 360 int size; /**< Size in bytes */ 361 int low_mark; /**< Low water mark */ 362 int high_mark; /**< High water mark */ 363 enum { 364 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 365 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 366 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 367 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 368 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 369 } flags; 370 unsigned long agp_start; /**< 371 * Start address of where the AGP buffers are 372 * in the AGP aperture 373 */ 374 }; 375 376 /** 377 * DRM_IOCTL_INFO_BUFS ioctl argument type. 378 */ 379 struct drm_buf_info { 380 int count; /**< Entries in list */ 381 struct drm_buf_desc __user *list; 382 }; 383 384 /** 385 * DRM_IOCTL_FREE_BUFS ioctl argument type. 386 */ 387 struct drm_buf_free { 388 int count; 389 int __user *list; 390 }; 391 392 /** 393 * Buffer information 394 * 395 * \sa drm_buf_map. 396 */ 397 struct drm_buf_pub { 398 int idx; /**< Index into the master buffer list */ 399 int total; /**< Buffer size */ 400 int used; /**< Amount of buffer in use (for DMA) */ 401 void __user *address; /**< Address of buffer */ 402 }; 403 404 /** 405 * DRM_IOCTL_MAP_BUFS ioctl argument type. 406 */ 407 struct drm_buf_map { 408 int count; /**< Length of the buffer list */ 409 #ifdef __cplusplus 410 void __user *virt; 411 #else 412 void __user *virtual; /**< Mmap'd area in user-virtual */ 413 #endif 414 struct drm_buf_pub __user *list; /**< Buffer information */ 415 }; 416 417 /** 418 * DRM_IOCTL_DMA ioctl argument type. 419 * 420 * Indices here refer to the offset into the buffer list in drm_buf_get. 421 * 422 * \sa drmDMA(). 423 */ 424 struct drm_dma { 425 int context; /**< Context handle */ 426 int send_count; /**< Number of buffers to send */ 427 int __user *send_indices; /**< List of handles to buffers */ 428 int __user *send_sizes; /**< Lengths of data to send */ 429 enum drm_dma_flags flags; /**< Flags */ 430 int request_count; /**< Number of buffers requested */ 431 int request_size; /**< Desired size for buffers */ 432 int __user *request_indices; /**< Buffer information */ 433 int __user *request_sizes; 434 int granted_count; /**< Number of buffers granted */ 435 }; 436 437 enum drm_ctx_flags { 438 _DRM_CONTEXT_PRESERVED = 0x01, 439 _DRM_CONTEXT_2DONLY = 0x02 440 }; 441 442 /** 443 * DRM_IOCTL_ADD_CTX ioctl argument type. 444 * 445 * \sa drmCreateContext() and drmDestroyContext(). 446 */ 447 struct drm_ctx { 448 drm_context_t handle; 449 enum drm_ctx_flags flags; 450 }; 451 452 /** 453 * DRM_IOCTL_RES_CTX ioctl argument type. 454 */ 455 struct drm_ctx_res { 456 int count; 457 struct drm_ctx __user *contexts; 458 }; 459 460 /** 461 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 462 */ 463 struct drm_draw { 464 drm_drawable_t handle; 465 }; 466 467 /** 468 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 469 */ 470 typedef enum { 471 DRM_DRAWABLE_CLIPRECTS 472 } drm_drawable_info_type_t; 473 474 struct drm_update_draw { 475 drm_drawable_t handle; 476 unsigned int type; 477 unsigned int num; 478 unsigned long long data; 479 }; 480 481 /** 482 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 483 */ 484 struct drm_auth { 485 drm_magic_t magic; 486 }; 487 488 /** 489 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 490 * 491 * \sa drmGetInterruptFromBusID(). 492 */ 493 struct drm_irq_busid { 494 int irq; /**< IRQ number */ 495 int busnum; /**< bus number */ 496 int devnum; /**< device number */ 497 int funcnum; /**< function number */ 498 }; 499 500 enum drm_vblank_seq_type { 501 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 502 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 503 /* bits 1-6 are reserved for high crtcs */ 504 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 505 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 506 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 507 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 508 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 509 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 510 }; 511 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 512 513 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 514 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 515 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 516 517 struct drm_wait_vblank_request { 518 enum drm_vblank_seq_type type; 519 unsigned int sequence; 520 unsigned long signal; 521 }; 522 523 struct drm_wait_vblank_reply { 524 enum drm_vblank_seq_type type; 525 unsigned int sequence; 526 long tval_sec; 527 long tval_usec; 528 }; 529 530 /** 531 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 532 * 533 * \sa drmWaitVBlank(). 534 */ 535 union drm_wait_vblank { 536 struct drm_wait_vblank_request request; 537 struct drm_wait_vblank_reply reply; 538 }; 539 540 #define _DRM_PRE_MODESET 1 541 #define _DRM_POST_MODESET 2 542 543 /** 544 * DRM_IOCTL_MODESET_CTL ioctl argument type 545 * 546 * \sa drmModesetCtl(). 547 */ 548 struct drm_modeset_ctl { 549 __u32 crtc; 550 __u32 cmd; 551 }; 552 553 /** 554 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 555 * 556 * \sa drmAgpEnable(). 557 */ 558 struct drm_agp_mode { 559 unsigned long mode; /**< AGP mode */ 560 }; 561 562 /** 563 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 564 * 565 * \sa drmAgpAlloc() and drmAgpFree(). 566 */ 567 struct drm_agp_buffer { 568 unsigned long size; /**< In bytes -- will round to page boundary */ 569 unsigned long handle; /**< Used for binding / unbinding */ 570 unsigned long type; /**< Type of memory to allocate */ 571 unsigned long physical; /**< Physical used by i810 */ 572 }; 573 574 /** 575 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 576 * 577 * \sa drmAgpBind() and drmAgpUnbind(). 578 */ 579 struct drm_agp_binding { 580 unsigned long handle; /**< From drm_agp_buffer */ 581 unsigned long offset; /**< In bytes -- will round to page boundary */ 582 }; 583 584 /** 585 * DRM_IOCTL_AGP_INFO ioctl argument type. 586 * 587 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 588 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 589 * drmAgpVendorId() and drmAgpDeviceId(). 590 */ 591 struct drm_agp_info { 592 int agp_version_major; 593 int agp_version_minor; 594 unsigned long mode; 595 unsigned long aperture_base; /* physical address */ 596 unsigned long aperture_size; /* bytes */ 597 unsigned long memory_allowed; /* bytes */ 598 unsigned long memory_used; 599 600 /* PCI information */ 601 unsigned short id_vendor; 602 unsigned short id_device; 603 }; 604 605 /** 606 * DRM_IOCTL_SG_ALLOC ioctl argument type. 607 */ 608 struct drm_scatter_gather { 609 unsigned long size; /**< In bytes -- will round to page boundary */ 610 unsigned long handle; /**< Used for mapping / unmapping */ 611 }; 612 613 /** 614 * DRM_IOCTL_SET_VERSION ioctl argument type. 615 */ 616 struct drm_set_version { 617 int drm_di_major; 618 int drm_di_minor; 619 int drm_dd_major; 620 int drm_dd_minor; 621 }; 622 623 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 624 struct drm_gem_close { 625 /** Handle of the object to be closed. */ 626 __u32 handle; 627 __u32 pad; 628 }; 629 630 /** DRM_IOCTL_GEM_FLINK ioctl argument type */ 631 struct drm_gem_flink { 632 /** Handle for the object being named */ 633 __u32 handle; 634 635 /** Returned global name */ 636 __u32 name; 637 }; 638 639 /** DRM_IOCTL_GEM_OPEN ioctl argument type */ 640 struct drm_gem_open { 641 /** Name of object being opened */ 642 __u32 name; 643 644 /** Returned handle for the object */ 645 __u32 handle; 646 647 /** Returned size of the object */ 648 __u64 size; 649 }; 650 651 #define DRM_CAP_DUMB_BUFFER 0x1 652 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 653 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 654 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 655 #define DRM_CAP_PRIME 0x5 656 #define DRM_PRIME_CAP_IMPORT 0x1 657 #define DRM_PRIME_CAP_EXPORT 0x2 658 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 659 #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 660 /* 661 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 662 * combination for the hardware cursor. The intention is that a hardware 663 * agnostic userspace can query a cursor plane size to use. 664 * 665 * Note that the cross-driver contract is to merely return a valid size; 666 * drivers are free to attach another meaning on top, eg. i915 returns the 667 * maximum plane size. 668 */ 669 #define DRM_CAP_CURSOR_WIDTH 0x8 670 #define DRM_CAP_CURSOR_HEIGHT 0x9 671 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 672 #define DRM_CAP_PAGE_FLIP_TARGET 0x11 673 #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 674 #define DRM_CAP_SYNCOBJ 0x13 675 #define DRM_CAP_SYNCOBJ_TIMELINE 0x14 676 677 /** DRM_IOCTL_GET_CAP ioctl argument type */ 678 struct drm_get_cap { 679 __u64 capability; 680 __u64 value; 681 }; 682 683 /** 684 * DRM_CLIENT_CAP_STEREO_3D 685 * 686 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 687 * monitor by advertising the supported 3D layouts in the flags of struct 688 * drm_mode_modeinfo. 689 */ 690 #define DRM_CLIENT_CAP_STEREO_3D 1 691 692 /** 693 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 694 * 695 * If set to 1, the DRM core will expose all planes (overlay, primary, and 696 * cursor) to userspace. 697 */ 698 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 699 700 /** 701 * DRM_CLIENT_CAP_ATOMIC 702 * 703 * If set to 1, the DRM core will expose atomic properties to userspace 704 */ 705 #define DRM_CLIENT_CAP_ATOMIC 3 706 707 /** 708 * DRM_CLIENT_CAP_ASPECT_RATIO 709 * 710 * If set to 1, the DRM core will provide aspect ratio information in modes. 711 */ 712 #define DRM_CLIENT_CAP_ASPECT_RATIO 4 713 714 /** 715 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 716 * 717 * If set to 1, the DRM core will expose special connectors to be used for 718 * writing back to memory the scene setup in the commit. Depends on client 719 * also supporting DRM_CLIENT_CAP_ATOMIC 720 */ 721 #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 722 723 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 724 struct drm_set_client_cap { 725 __u64 capability; 726 __u64 value; 727 }; 728 729 #define DRM_RDWR O_RDWR 730 #define DRM_CLOEXEC O_CLOEXEC 731 struct drm_prime_handle { 732 __u32 handle; 733 734 /** Flags.. only applicable for handle->fd */ 735 __u32 flags; 736 737 /** Returned dmabuf file descriptor */ 738 __s32 fd; 739 }; 740 741 struct drm_syncobj_create { 742 __u32 handle; 743 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 744 __u32 flags; 745 }; 746 747 struct drm_syncobj_destroy { 748 __u32 handle; 749 __u32 pad; 750 }; 751 752 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 753 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 754 struct drm_syncobj_handle { 755 __u32 handle; 756 __u32 flags; 757 758 __s32 fd; 759 __u32 pad; 760 }; 761 762 struct drm_syncobj_transfer { 763 __u32 src_handle; 764 __u32 dst_handle; 765 __u64 src_point; 766 __u64 dst_point; 767 __u32 flags; 768 __u32 pad; 769 }; 770 771 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 772 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 773 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ 774 struct drm_syncobj_wait { 775 __u64 handles; 776 /* absolute timeout */ 777 __s64 timeout_nsec; 778 __u32 count_handles; 779 __u32 flags; 780 __u32 first_signaled; /* only valid when not waiting all */ 781 __u32 pad; 782 }; 783 784 struct drm_syncobj_timeline_wait { 785 __u64 handles; 786 /* wait on specific timeline point for every handles*/ 787 __u64 points; 788 /* absolute timeout */ 789 __s64 timeout_nsec; 790 __u32 count_handles; 791 __u32 flags; 792 __u32 first_signaled; /* only valid when not waiting all */ 793 __u32 pad; 794 }; 795 796 797 struct drm_syncobj_array { 798 __u64 handles; 799 __u32 count_handles; 800 __u32 pad; 801 }; 802 803 #define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ 804 struct drm_syncobj_timeline_array { 805 __u64 handles; 806 __u64 points; 807 __u32 count_handles; 808 __u32 flags; 809 }; 810 811 812 /* Query current scanout sequence number */ 813 struct drm_crtc_get_sequence { 814 __u32 crtc_id; /* requested crtc_id */ 815 __u32 active; /* return: crtc output is active */ 816 __u64 sequence; /* return: most recent vblank sequence */ 817 __s64 sequence_ns; /* return: most recent time of first pixel out */ 818 }; 819 820 /* Queue event to be delivered at specified sequence. Time stamp marks 821 * when the first pixel of the refresh cycle leaves the display engine 822 * for the display 823 */ 824 #define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 825 #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 826 827 struct drm_crtc_queue_sequence { 828 __u32 crtc_id; 829 __u32 flags; 830 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 831 __u64 user_data; /* user data passed to event */ 832 }; 833 834 #if defined(__cplusplus) 835 } 836 #endif 837 838 #include "drm_mode.h" 839 840 #if defined(__cplusplus) 841 extern "C" { 842 #endif 843 844 #define DRM_IOCTL_BASE 'd' 845 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 846 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 847 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 848 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 849 850 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 851 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 852 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 853 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 854 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 855 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 856 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 857 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 858 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 859 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 860 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 861 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 862 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 863 #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 864 865 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 866 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 867 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 868 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 869 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 870 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 871 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 872 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 873 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 874 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 875 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 876 877 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 878 879 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 880 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 881 882 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 883 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 884 885 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 886 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 887 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 888 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 889 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 890 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 891 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 892 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 893 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 894 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 895 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 896 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 897 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 898 899 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 900 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 901 902 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 903 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 904 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 905 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 906 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 907 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 908 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 909 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 910 911 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 912 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 913 914 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 915 916 #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 917 #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 918 919 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 920 921 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 922 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 923 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 924 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 925 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 926 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 927 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 928 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 929 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 930 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 931 932 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 933 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 934 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 935 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 936 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 937 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 938 #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 939 #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 940 941 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 942 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 943 #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 944 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 945 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 946 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 947 #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 948 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 949 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 950 #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 951 #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 952 #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 953 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 954 955 #ifdef __NetBSD__ 956 /* 957 * Instrumenting mmap is trickier than just making an ioctl to do it. 958 */ 959 struct drm_mmap { 960 void *dnm_addr; /* in/out */ 961 size_t dnm_size; /* in */ 962 int dnm_prot; /* in */ 963 int dnm_flags; /* in */ 964 off_t dnm_offset; /* in */ 965 }; 966 #define DRM_IOCTL_MMAP DRM_IOWR(0xff, struct drm_mmap) 967 #endif 968 #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 969 #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 970 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 971 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 972 #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 973 #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 974 #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 975 976 #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 977 #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 978 #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 979 #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 980 981 #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) 982 #define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) 983 #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) 984 #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) 985 986 /** 987 * Device specific ioctls should only be in their respective headers 988 * The device specific ioctl range is from 0x40 to 0x9f. 989 * Generic IOCTLS restart at 0xA0. 990 * 991 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 992 * drmCommandReadWrite(). 993 */ 994 #define DRM_COMMAND_BASE 0x40 995 #define DRM_COMMAND_END 0xA0 996 997 /** 998 * Header for events written back to userspace on the drm fd. The 999 * type defines the type of event, the length specifies the total 1000 * length of the event (including the header), and user_data is 1001 * typically a 64 bit value passed with the ioctl that triggered the 1002 * event. A read on the drm fd will always only return complete 1003 * events, that is, if for example the read buffer is 100 bytes, and 1004 * there are two 64 byte events pending, only one will be returned. 1005 * 1006 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 1007 * up are chipset specific. 1008 */ 1009 struct drm_event { 1010 __u32 type; 1011 __u32 length; 1012 }; 1013 1014 #define DRM_EVENT_VBLANK 0x01 1015 #define DRM_EVENT_FLIP_COMPLETE 0x02 1016 #define DRM_EVENT_CRTC_SEQUENCE 0x03 1017 1018 struct drm_event_vblank { 1019 struct drm_event base; 1020 __u64 user_data; 1021 __u32 tv_sec; 1022 __u32 tv_usec; 1023 __u32 sequence; 1024 __u32 crtc_id; /* 0 on older kernels that do not support this */ 1025 }; 1026 1027 /* Event delivered at sequence. Time stamp marks when the first pixel 1028 * of the refresh cycle leaves the display engine for the display 1029 */ 1030 struct drm_event_crtc_sequence { 1031 struct drm_event base; 1032 __u64 user_data; 1033 __s64 time_ns; 1034 __u64 sequence; 1035 }; 1036 1037 /* typedef area */ 1038 #ifndef __KERNEL__ 1039 typedef struct drm_clip_rect drm_clip_rect_t; 1040 typedef struct drm_drawable_info drm_drawable_info_t; 1041 typedef struct drm_tex_region drm_tex_region_t; 1042 typedef struct drm_hw_lock drm_hw_lock_t; 1043 typedef struct drm_version drm_version_t; 1044 typedef struct drm_unique drm_unique_t; 1045 typedef struct drm_list drm_list_t; 1046 typedef struct drm_block drm_block_t; 1047 typedef struct drm_control drm_control_t; 1048 typedef enum drm_map_type drm_map_type_t; 1049 typedef enum drm_map_flags drm_map_flags_t; 1050 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 1051 typedef struct drm_map drm_map_t; 1052 typedef struct drm_client drm_client_t; 1053 typedef enum drm_stat_type drm_stat_type_t; 1054 typedef struct drm_stats drm_stats_t; 1055 typedef enum drm_lock_flags drm_lock_flags_t; 1056 typedef struct drm_lock drm_lock_t; 1057 typedef enum drm_dma_flags drm_dma_flags_t; 1058 typedef struct drm_buf_desc drm_buf_desc_t; 1059 typedef struct drm_buf_info drm_buf_info_t; 1060 typedef struct drm_buf_free drm_buf_free_t; 1061 typedef struct drm_buf_pub drm_buf_pub_t; 1062 typedef struct drm_buf_map drm_buf_map_t; 1063 typedef struct drm_dma drm_dma_t; 1064 typedef union drm_wait_vblank drm_wait_vblank_t; 1065 typedef struct drm_agp_mode drm_agp_mode_t; 1066 typedef enum drm_ctx_flags drm_ctx_flags_t; 1067 typedef struct drm_ctx drm_ctx_t; 1068 typedef struct drm_ctx_res drm_ctx_res_t; 1069 typedef struct drm_draw drm_draw_t; 1070 typedef struct drm_update_draw drm_update_draw_t; 1071 typedef struct drm_auth drm_auth_t; 1072 typedef struct drm_irq_busid drm_irq_busid_t; 1073 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1074 1075 typedef struct drm_agp_buffer drm_agp_buffer_t; 1076 typedef struct drm_agp_binding drm_agp_binding_t; 1077 typedef struct drm_agp_info drm_agp_info_t; 1078 typedef struct drm_scatter_gather drm_scatter_gather_t; 1079 typedef struct drm_set_version drm_set_version_t; 1080 #endif 1081 1082 #if defined(__cplusplus) 1083 } 1084 #endif 1085 1086 #endif 1087
Indexes created Sat Sep 20 22:09:52 GMT 2025