1 /* $NetBSD: mga_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */ 2 3 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- 4 * Created: Tue Jan 25 01:50:01 1999 by jhartmann (at) precisioninsight.com 5 * 6 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 7 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 8 * All rights reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice (including the next 18 * paragraph) shall be included in all copies or substantial portions of the 19 * Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 * OTHER DEALINGS IN THE SOFTWARE. 28 * 29 * Authors: 30 * Jeff Hartmann <jhartmann (at) valinux.com> 31 * Keith Whitwell <keith (at) tungstengraphics.com> 32 * 33 * Rewritten by: 34 * Gareth Hughes <gareth (at) valinux.com> 35 */ 36 37 #ifndef __MGA_DRM_H__ 38 #define __MGA_DRM_H__ 39 40 #include "drm.h" 41 42 #if defined(__cplusplus) 43 extern "C" { 44 #endif 45 46 /* WARNING: If you change any of these defines, make sure to change the 47 * defines in the Xserver file (mga_sarea.h) 48 */ 49 50 #ifndef __MGA_SAREA_DEFINES__ 51 #define __MGA_SAREA_DEFINES__ 52 53 /* WARP pipe flags 54 */ 55 #define MGA_F 0x1 /* fog */ 56 #define MGA_A 0x2 /* alpha */ 57 #define MGA_S 0x4 /* specular */ 58 #define MGA_T2 0x8 /* multitexture */ 59 60 #define MGA_WARP_TGZ 0 61 #define MGA_WARP_TGZF (MGA_F) 62 #define MGA_WARP_TGZA (MGA_A) 63 #define MGA_WARP_TGZAF (MGA_F|MGA_A) 64 #define MGA_WARP_TGZS (MGA_S) 65 #define MGA_WARP_TGZSF (MGA_S|MGA_F) 66 #define MGA_WARP_TGZSA (MGA_S|MGA_A) 67 #define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) 68 #define MGA_WARP_T2GZ (MGA_T2) 69 #define MGA_WARP_T2GZF (MGA_T2|MGA_F) 70 #define MGA_WARP_T2GZA (MGA_T2|MGA_A) 71 #define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) 72 #define MGA_WARP_T2GZS (MGA_T2|MGA_S) 73 #define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) 74 #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 75 #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 76 77 #define MGA_MAX_G200_PIPES 8 /* no multitex */ 78 #define MGA_MAX_G400_PIPES 16 79 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 80 #define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 81 82 #define MGA_CARD_TYPE_G200 1 83 #define MGA_CARD_TYPE_G400 2 84 #define MGA_CARD_TYPE_G450 3 /* not currently used */ 85 #define MGA_CARD_TYPE_G550 4 86 87 #define MGA_FRONT 0x1 88 #define MGA_BACK 0x2 89 #define MGA_DEPTH 0x4 90 91 /* What needs to be changed for the current vertex dma buffer? 92 */ 93 #define MGA_UPLOAD_CONTEXT 0x1 94 #define MGA_UPLOAD_TEX0 0x2 95 #define MGA_UPLOAD_TEX1 0x4 96 #define MGA_UPLOAD_PIPE 0x8 97 #define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 98 #define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 99 #define MGA_UPLOAD_2D 0x40 100 #define MGA_WAIT_AGE 0x80 /* handled client-side */ 101 #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 102 #if 0 103 #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock 104 quiescent */ 105 #endif 106 107 /* 32 buffers of 64k each, total 2 meg. 108 */ 109 #define MGA_BUFFER_SIZE (1 << 16) 110 #define MGA_NUM_BUFFERS 128 111 112 /* Keep these small for testing. 113 */ 114 #define MGA_NR_SAREA_CLIPRECTS 8 115 116 /* 2 heaps (1 for card, 1 for agp), each divided into up to 128 117 * regions, subject to a minimum region size of (1<<16) == 64k. 118 * 119 * Clients may subdivide regions internally, but when sharing between 120 * clients, the region size is the minimum granularity. 121 */ 122 123 #define MGA_CARD_HEAP 0 124 #define MGA_AGP_HEAP 1 125 #define MGA_NR_TEX_HEAPS 2 126 #define MGA_NR_TEX_REGIONS 16 127 #define MGA_LOG_MIN_TEX_REGION_SIZE 16 128 129 #define DRM_MGA_IDLE_RETRY 2048 130 131 #endif /* __MGA_SAREA_DEFINES__ */ 132 133 /* Setup registers for 3D context 134 */ 135 typedef struct { 136 unsigned int dstorg; 137 unsigned int maccess; 138 unsigned int plnwt; 139 unsigned int dwgctl; 140 unsigned int alphactrl; 141 unsigned int fogcolor; 142 unsigned int wflag; 143 unsigned int tdualstage0; 144 unsigned int tdualstage1; 145 unsigned int fcol; 146 unsigned int stencil; 147 unsigned int stencilctl; 148 } drm_mga_context_regs_t; 149 150 /* Setup registers for 2D, X server 151 */ 152 typedef struct { 153 unsigned int pitch; 154 } drm_mga_server_regs_t; 155 156 /* Setup registers for each texture unit 157 */ 158 typedef struct { 159 unsigned int texctl; 160 unsigned int texctl2; 161 unsigned int texfilter; 162 unsigned int texbordercol; 163 unsigned int texorg; 164 unsigned int texwidth; 165 unsigned int texheight; 166 unsigned int texorg1; 167 unsigned int texorg2; 168 unsigned int texorg3; 169 unsigned int texorg4; 170 } drm_mga_texture_regs_t; 171 172 /* General aging mechanism 173 */ 174 typedef struct { 175 unsigned int head; /* Position of head pointer */ 176 unsigned int wrap; /* Primary DMA wrap count */ 177 } drm_mga_age_t; 178 179 typedef struct _drm_mga_sarea { 180 /* The channel for communication of state information to the kernel 181 * on firing a vertex dma buffer. 182 */ 183 drm_mga_context_regs_t context_state; 184 drm_mga_server_regs_t server_state; 185 drm_mga_texture_regs_t tex_state[2]; 186 unsigned int warp_pipe; 187 unsigned int dirty; 188 unsigned int vertsize; 189 190 /* The current cliprects, or a subset thereof. 191 */ 192 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; 193 unsigned int nbox; 194 195 /* Information about the most recently used 3d drawable. The 196 * client fills in the req_* fields, the server fills in the 197 * exported_ fields and puts the cliprects into boxes, above. 198 * 199 * The client clears the exported_drawable field before 200 * clobbering the boxes data. 201 */ 202 unsigned int req_drawable; /* the X drawable id */ 203 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 204 205 unsigned int exported_drawable; 206 unsigned int exported_index; 207 unsigned int exported_stamp; 208 unsigned int exported_buffers; 209 unsigned int exported_nfront; 210 unsigned int exported_nback; 211 int exported_back_x, exported_front_x, exported_w; 212 int exported_back_y, exported_front_y, exported_h; 213 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 214 215 /* Counters for aging textures and for client-side throttling. 216 */ 217 unsigned int status[4]; 218 unsigned int last_wrap; 219 220 drm_mga_age_t last_frame; 221 unsigned int last_enqueue; /* last time a buffer was enqueued */ 222 unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 223 unsigned int last_quiescent; /* */ 224 225 /* LRU lists for texture memory in agp space and on the card. 226 */ 227 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; 228 unsigned int texAge[MGA_NR_TEX_HEAPS]; 229 230 /* Mechanism to validate card state. 231 */ 232 int ctxOwner; 233 } drm_mga_sarea_t; 234 235 /* MGA specific ioctls 236 * The device specific ioctl range is 0x40 to 0x79. 237 */ 238 #define DRM_MGA_INIT 0x00 239 #define DRM_MGA_FLUSH 0x01 240 #define DRM_MGA_RESET 0x02 241 #define DRM_MGA_SWAP 0x03 242 #define DRM_MGA_CLEAR 0x04 243 #define DRM_MGA_VERTEX 0x05 244 #define DRM_MGA_INDICES 0x06 245 #define DRM_MGA_ILOAD 0x07 246 #define DRM_MGA_BLIT 0x08 247 #define DRM_MGA_GETPARAM 0x09 248 249 /* 3.2: 250 * ioctls for operating on fences. 251 */ 252 #define DRM_MGA_SET_FENCE 0x0a 253 #define DRM_MGA_WAIT_FENCE 0x0b 254 #define DRM_MGA_DMA_BOOTSTRAP 0x0c 255 256 #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 257 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) 258 #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 259 #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) 260 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) 261 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) 262 #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) 263 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 264 #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 265 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 266 #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) 267 #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) 268 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 269 270 typedef struct _drm_mga_warp_index { 271 int installed; 272 unsigned long phys_addr; 273 int size; 274 } drm_mga_warp_index_t; 275 276 typedef struct drm_mga_init { 277 enum { 278 MGA_INIT_DMA = 0x01, 279 MGA_CLEANUP_DMA = 0x02 280 } func; 281 282 unsigned long sarea_priv_offset; 283 284 int chipset; 285 int sgram; 286 287 unsigned int maccess; 288 289 unsigned int fb_cpp; 290 unsigned int front_offset, front_pitch; 291 unsigned int back_offset, back_pitch; 292 293 unsigned int depth_cpp; 294 unsigned int depth_offset, depth_pitch; 295 296 unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 297 unsigned int texture_size[MGA_NR_TEX_HEAPS]; 298 299 unsigned long fb_offset; 300 unsigned long mmio_offset; 301 unsigned long status_offset; 302 unsigned long warp_offset; 303 unsigned long primary_offset; 304 unsigned long buffers_offset; 305 } drm_mga_init_t; 306 307 typedef struct drm_mga_dma_bootstrap { 308 /** 309 * \name AGP texture region 310 * 311 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will 312 * be filled in with the actual AGP texture settings. 313 * 314 * \warning 315 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode 316 * is zero, it means that PCI memory (most likely through the use of 317 * an IOMMU) is being used for "AGP" textures. 318 */ 319 /*@{ */ 320 unsigned long texture_handle; /**< Handle used to map AGP textures. */ 321 __u32 texture_size; /**< Size of the AGP texture region. */ 322 /*@} */ 323 324 /** 325 * Requested size of the primary DMA region. 326 * 327 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 328 * filled in with the actual AGP mode. If AGP was not available 329 */ 330 __u32 primary_size; 331 332 /** 333 * Requested number of secondary DMA buffers. 334 * 335 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 336 * filled in with the actual number of secondary DMA buffers 337 * allocated. Particularly when PCI DMA is used, this may be 338 * (subtantially) less than the number requested. 339 */ 340 __u32 secondary_bin_count; 341 342 /** 343 * Requested size of each secondary DMA buffer. 344 * 345 * While the kernel \b is free to reduce 346 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 347 * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 348 */ 349 __u32 secondary_bin_size; 350 351 /** 352 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 353 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is 354 * zero, it means that PCI DMA should be used, even if AGP is 355 * possible. 356 * 357 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 358 * filled in with the actual AGP mode. If AGP was not available 359 * (i.e., PCI DMA was used), this value will be zero. 360 */ 361 __u32 agp_mode; 362 363 /** 364 * Desired AGP GART size, measured in megabytes. 365 */ 366 __u8 agp_size; 367 } drm_mga_dma_bootstrap_t; 368 369 typedef struct drm_mga_clear { 370 unsigned int flags; 371 unsigned int clear_color; 372 unsigned int clear_depth; 373 unsigned int color_mask; 374 unsigned int depth_mask; 375 } drm_mga_clear_t; 376 377 typedef struct drm_mga_vertex { 378 int idx; /* buffer to queue */ 379 int used; /* bytes in use */ 380 int discard; /* client finished with buffer? */ 381 } drm_mga_vertex_t; 382 383 typedef struct drm_mga_indices { 384 int idx; /* buffer to queue */ 385 unsigned int start; 386 unsigned int end; 387 int discard; /* client finished with buffer? */ 388 } drm_mga_indices_t; 389 390 typedef struct drm_mga_iload { 391 int idx; 392 unsigned int dstorg; 393 unsigned int length; 394 } drm_mga_iload_t; 395 396 typedef struct _drm_mga_blit { 397 unsigned int planemask; 398 unsigned int srcorg; 399 unsigned int dstorg; 400 int src_pitch, dst_pitch; 401 int delta_sx, delta_sy; 402 int delta_dx, delta_dy; 403 int height, ydir; /* flip image vertically */ 404 int source_pitch, dest_pitch; 405 } drm_mga_blit_t; 406 407 /* 3.1: An ioctl to get parameters that aren't available to the 3d 408 * client any other way. 409 */ 410 #define MGA_PARAM_IRQ_NR 1 411 412 /* 3.2: Query the actual card type. The DDX only distinguishes between 413 * G200 chips and non-G200 chips, which it calls G400. It turns out that 414 * there are some very sublte differences between the G4x0 chips and the G550 415 * chips. Using this parameter query, a client-side driver can detect the 416 * difference between a G4x0 and a G550. 417 */ 418 #define MGA_PARAM_CARD_TYPE 2 419 420 typedef struct drm_mga_getparam { 421 int param; 422 void __user *value; 423 } drm_mga_getparam_t; 424 425 #if defined(__cplusplus) 426 } 427 #endif 428 429 #endif 430
Indexes created Sat Sep 20 22:09:52 GMT 2025