1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Device Tree Include file for Marvell Armada XP family SoC 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni (a] free-electrons.com> 8 * 9 * Contains definitions specific to the Armada XP MV78260 SoC that are not 10 * common to all Armada XP SoCs. 11 */ 12 13 #include "armada-xp.dtsi" 14 15 / { 16 model = "Marvell Armada XP MV78260 SoC"; 17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 enable-method = "marvell,armada-xp-smp"; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "marvell,sheeva-v7"; 33 reg = <0>; 34 clocks = <&cpuclk 0>; 35 clock-latency = <1000000>; 36 }; 37 38 cpu@1 { 39 device_type = "cpu"; 40 compatible = "marvell,sheeva-v7"; 41 reg = <1>; 42 clocks = <&cpuclk 1>; 43 clock-latency = <1000000>; 44 }; 45 }; 46 47 soc { 48 /* 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be 50 * configured as x4 or quad x1 lanes. One unit is 51 * x4 only. 52 */ 53 pciec: pcie@82000000 { 54 compatible = "marvell,armada-xp-pcie"; 55 status = "disabled"; 56 device_type = "pci"; 57 58 #address-cells = <3>; 59 #size-cells = <2>; 60 61 msi-parent = <&mpic>; 62 bus-range = <0x00 0xff>; 63 64 ranges = 65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 82 83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 91 92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 94 95 pcie1: pcie@1,0 { 96 device_type = "pci"; 97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 98 reg = <0x0800 0 0 0 0>; 99 #address-cells = <3>; 100 #size-cells = <2>; 101 #interrupt-cells = <1>; 102 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 103 0x81000000 0 0 0x81000000 0x1 0 1 0>; 104 bus-range = <0x00 0xff>; 105 interrupt-map-mask = <0 0 0 0>; 106 interrupt-map = <0 0 0 0 &mpic 58>; 107 marvell,pcie-port = <0>; 108 marvell,pcie-lane = <0>; 109 clocks = <&gateclk 5>; 110 status = "disabled"; 111 }; 112 113 pcie2: pcie@2,0 { 114 device_type = "pci"; 115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 116 reg = <0x1000 0 0 0 0>; 117 #address-cells = <3>; 118 #size-cells = <2>; 119 #interrupt-cells = <1>; 120 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 121 0x81000000 0 0 0x81000000 0x2 0 1 0>; 122 bus-range = <0x00 0xff>; 123 interrupt-map-mask = <0 0 0 0>; 124 interrupt-map = <0 0 0 0 &mpic 59>; 125 marvell,pcie-port = <0>; 126 marvell,pcie-lane = <1>; 127 clocks = <&gateclk 6>; 128 status = "disabled"; 129 }; 130 131 pcie3: pcie@3,0 { 132 device_type = "pci"; 133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 134 reg = <0x1800 0 0 0 0>; 135 #address-cells = <3>; 136 #size-cells = <2>; 137 #interrupt-cells = <1>; 138 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 139 0x81000000 0 0 0x81000000 0x3 0 1 0>; 140 bus-range = <0x00 0xff>; 141 interrupt-map-mask = <0 0 0 0>; 142 interrupt-map = <0 0 0 0 &mpic 60>; 143 marvell,pcie-port = <0>; 144 marvell,pcie-lane = <2>; 145 clocks = <&gateclk 7>; 146 status = "disabled"; 147 }; 148 149 pcie4: pcie@4,0 { 150 device_type = "pci"; 151 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 152 reg = <0x2000 0 0 0 0>; 153 #address-cells = <3>; 154 #size-cells = <2>; 155 #interrupt-cells = <1>; 156 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 157 0x81000000 0 0 0x81000000 0x4 0 1 0>; 158 bus-range = <0x00 0xff>; 159 interrupt-map-mask = <0 0 0 0>; 160 interrupt-map = <0 0 0 0 &mpic 61>; 161 marvell,pcie-port = <0>; 162 marvell,pcie-lane = <3>; 163 clocks = <&gateclk 8>; 164 status = "disabled"; 165 }; 166 167 pcie5: pcie@5,0 { 168 device_type = "pci"; 169 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 170 reg = <0x2800 0 0 0 0>; 171 #address-cells = <3>; 172 #size-cells = <2>; 173 #interrupt-cells = <1>; 174 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 175 0x81000000 0 0 0x81000000 0x5 0 1 0>; 176 bus-range = <0x00 0xff>; 177 interrupt-map-mask = <0 0 0 0>; 178 interrupt-map = <0 0 0 0 &mpic 62>; 179 marvell,pcie-port = <1>; 180 marvell,pcie-lane = <0>; 181 clocks = <&gateclk 9>; 182 status = "disabled"; 183 }; 184 185 pcie6: pcie@6,0 { 186 device_type = "pci"; 187 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; 188 reg = <0x3000 0 0 0 0>; 189 #address-cells = <3>; 190 #size-cells = <2>; 191 #interrupt-cells = <1>; 192 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 193 0x81000000 0 0 0x81000000 0x6 0 1 0>; 194 bus-range = <0x00 0xff>; 195 interrupt-map-mask = <0 0 0 0>; 196 interrupt-map = <0 0 0 0 &mpic 63>; 197 marvell,pcie-port = <1>; 198 marvell,pcie-lane = <1>; 199 clocks = <&gateclk 10>; 200 status = "disabled"; 201 }; 202 203 pcie7: pcie@7,0 { 204 device_type = "pci"; 205 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; 206 reg = <0x3800 0 0 0 0>; 207 #address-cells = <3>; 208 #size-cells = <2>; 209 #interrupt-cells = <1>; 210 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 211 0x81000000 0 0 0x81000000 0x7 0 1 0>; 212 bus-range = <0x00 0xff>; 213 interrupt-map-mask = <0 0 0 0>; 214 interrupt-map = <0 0 0 0 &mpic 64>; 215 marvell,pcie-port = <1>; 216 marvell,pcie-lane = <2>; 217 clocks = <&gateclk 11>; 218 status = "disabled"; 219 }; 220 221 pcie8: pcie@8,0 { 222 device_type = "pci"; 223 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; 224 reg = <0x4000 0 0 0 0>; 225 #address-cells = <3>; 226 #size-cells = <2>; 227 #interrupt-cells = <1>; 228 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 229 0x81000000 0 0 0x81000000 0x8 0 1 0>; 230 bus-range = <0x00 0xff>; 231 interrupt-map-mask = <0 0 0 0>; 232 interrupt-map = <0 0 0 0 &mpic 65>; 233 marvell,pcie-port = <1>; 234 marvell,pcie-lane = <3>; 235 clocks = <&gateclk 12>; 236 status = "disabled"; 237 }; 238 239 pcie9: pcie@9,0 { 240 device_type = "pci"; 241 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 242 reg = <0x4800 0 0 0 0>; 243 #address-cells = <3>; 244 #size-cells = <2>; 245 #interrupt-cells = <1>; 246 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 247 0x81000000 0 0 0x81000000 0x9 0 1 0>; 248 bus-range = <0x00 0xff>; 249 interrupt-map-mask = <0 0 0 0>; 250 interrupt-map = <0 0 0 0 &mpic 99>; 251 marvell,pcie-port = <2>; 252 marvell,pcie-lane = <0>; 253 clocks = <&gateclk 26>; 254 status = "disabled"; 255 }; 256 }; 257 258 internal-regs { 259 gpio0: gpio@18100 { 260 compatible = "marvell,armada-370-gpio", 261 "marvell,orion-gpio"; 262 reg = <0x18100 0x40>, <0x181c0 0x08>; 263 reg-names = "gpio", "pwm"; 264 ngpios = <32>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 #pwm-cells = <2>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 interrupts = <82>, <83>, <84>, <85>; 271 clocks = <&coreclk 0>; 272 }; 273 274 gpio1: gpio@18140 { 275 compatible = "marvell,armada-370-gpio", 276 "marvell,orion-gpio"; 277 reg = <0x18140 0x40>, <0x181c8 0x08>; 278 reg-names = "gpio", "pwm"; 279 ngpios = <32>; 280 gpio-controller; 281 #gpio-cells = <2>; 282 #pwm-cells = <2>; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 interrupts = <87>, <88>, <89>, <90>; 286 clocks = <&coreclk 0>; 287 }; 288 289 gpio2: gpio@18180 { 290 compatible = "marvell,armada-370-gpio", 291 "marvell,orion-gpio"; 292 reg = <0x18180 0x40>; 293 ngpios = <3>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 interrupts = <91>; 299 }; 300 301 eth3: ethernet@34000 { 302 compatible = "marvell,armada-xp-neta"; 303 reg = <0x34000 0x4000>; 304 interrupts = <14>; 305 clocks = <&gateclk 1>; 306 status = "disabled"; 307 }; 308 }; 309 }; 310 }; 311 312 &pinctrl { 313 compatible = "marvell,mv78260-pinctrl"; 314 }; 315
Indexes created Sun Oct 12 09:09:55 GMT 2025