1 1.1 jmcneill // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 1.1 jmcneill /* 3 1.1 jmcneill * Copyright (c) 2014 Protonic Holland 4 1.1 jmcneill * Copyright (c) 2020 Oleksij Rempel <kernel (a] pengutronix.de>, Pengutronix 5 1.1 jmcneill */ 6 1.1 jmcneill 7 1.1 jmcneill #include <dt-bindings/display/sdtv-standards.h> 8 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 9 1.1 jmcneill #include <dt-bindings/input/input.h> 10 1.1 jmcneill #include <dt-bindings/leds/common.h> 11 1.1 jmcneill #include <dt-bindings/media/tvp5150.h> 12 1.1 jmcneill #include <dt-bindings/sound/fsl-imx-audmux.h> 13 1.1 jmcneill 14 1.1 jmcneill / { 15 1.1 jmcneill chosen { 16 1.1 jmcneill stdout-path = &uart4; 17 1.1 jmcneill }; 18 1.1 jmcneill 19 1.1 jmcneill backlight: backlight { 20 1.1 jmcneill compatible = "pwm-backlight"; 21 1.1 jmcneill pinctrl-names = "default"; 22 1.1 jmcneill pinctrl-0 = <&pinctrl_backlight>; 23 1.1 jmcneill pwms = <&pwm1 0 5000000 0>; 24 1.1 jmcneill brightness-levels = <0 16 64 255>; 25 1.1 jmcneill num-interpolated-steps = <16>; 26 1.1 jmcneill default-brightness-level = <1>; 27 1.1 jmcneill power-supply = <®_3v3>; 28 1.1 jmcneill enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 29 1.1 jmcneill }; 30 1.1 jmcneill 31 1.1 jmcneill connector { 32 1.1 jmcneill compatible = "composite-video-connector"; 33 1.1 jmcneill label = "Composite0"; 34 1.1 jmcneill sdtv-standards = <SDTV_STD_PAL_B>; 35 1.1 jmcneill 36 1.1 jmcneill port { 37 1.1 jmcneill comp0_out: endpoint { 38 1.1 jmcneill remote-endpoint = <&tvp5150_comp0_in>; 39 1.1 jmcneill }; 40 1.1 jmcneill }; 41 1.1 jmcneill }; 42 1.1 jmcneill 43 1.1 jmcneill counter-0 { 44 1.1 jmcneill compatible = "interrupt-counter"; 45 1.1 jmcneill pinctrl-names = "default"; 46 1.1 jmcneill pinctrl-0 = <&pinctrl_counter0>; 47 1.1 jmcneill gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 48 1.1 jmcneill }; 49 1.1 jmcneill 50 1.1 jmcneill counter-1 { 51 1.1 jmcneill compatible = "interrupt-counter"; 52 1.1 jmcneill pinctrl-names = "default"; 53 1.1 jmcneill pinctrl-0 = <&pinctrl_counter1>; 54 1.1 jmcneill gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 55 1.1 jmcneill }; 56 1.1 jmcneill 57 1.1 jmcneill counter-2 { 58 1.1 jmcneill compatible = "interrupt-counter"; 59 1.1 jmcneill pinctrl-names = "default"; 60 1.1 jmcneill pinctrl-0 = <&pinctrl_counter2>; 61 1.1 jmcneill gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 62 1.1 jmcneill }; 63 1.1 jmcneill 64 1.1 jmcneill gpio-keys { 65 1.1 jmcneill compatible = "gpio-keys"; 66 1.1 jmcneill autorepeat; 67 1.1 jmcneill 68 1.1 jmcneill power { 69 1.1 jmcneill label = "Power Button"; 70 1.1 jmcneill gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 71 1.1 jmcneill linux,code = <KEY_POWER>; 72 1.1 jmcneill wakeup-source; 73 1.1 jmcneill }; 74 1.1 jmcneill }; 75 1.1 jmcneill 76 1.1 jmcneill leds { 77 1.1 jmcneill compatible = "gpio-leds"; 78 1.1 jmcneill pinctrl-names = "default"; 79 1.1 jmcneill pinctrl-0 = <&pinctrl_leds>; 80 1.1 jmcneill 81 1.1 jmcneill led-0 { 82 1.1 jmcneill label = "LED_DI0_DEBUG_0"; 83 1.1 jmcneill function = LED_FUNCTION_HEARTBEAT; 84 1.1 jmcneill gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 85 1.1 jmcneill linux,default-trigger = "heartbeat"; 86 1.1 jmcneill }; 87 1.1 jmcneill 88 1.1 jmcneill led-1 { 89 1.1 jmcneill label = "LED_DI0_DEBUG_1"; 90 1.1 jmcneill function = LED_FUNCTION_DISK; 91 1.1 jmcneill gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; 92 1.1 jmcneill linux,default-trigger = "disk-activity"; 93 1.1 jmcneill }; 94 1.1 jmcneill 95 1.1 jmcneill led-2 { 96 1.1 jmcneill label = "POWER_LED"; 97 1.1 jmcneill function = LED_FUNCTION_POWER; 98 1.1 jmcneill gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; 99 1.1 jmcneill default-state = "on"; 100 1.1 jmcneill }; 101 1.1 jmcneill }; 102 1.1 jmcneill 103 1.1 jmcneill panel { 104 1.1 jmcneill compatible = "kyo,tcg121xglp"; 105 1.1 jmcneill backlight = <&backlight>; 106 1.1 jmcneill power-supply = <®_3v3>; 107 1.1 jmcneill 108 1.1 jmcneill port { 109 1.1 jmcneill panel_in: endpoint { 110 1.1 jmcneill remote-endpoint = <&lvds0_out>; 111 1.1 jmcneill }; 112 1.1 jmcneill }; 113 1.1 jmcneill }; 114 1.1 jmcneill 115 1.1 jmcneill reg_1v8: regulator-1v8 { 116 1.1 jmcneill compatible = "regulator-fixed"; 117 1.1 jmcneill regulator-name = "1v8"; 118 1.1 jmcneill regulator-min-microvolt = <1800000>; 119 1.1 jmcneill regulator-max-microvolt = <1800000>; 120 1.1 jmcneill }; 121 1.1 jmcneill 122 1.1 jmcneill reg_3v3: regulator-3v3 { 123 1.1 jmcneill compatible = "regulator-fixed"; 124 1.1 jmcneill regulator-name = "3v3"; 125 1.1 jmcneill regulator-min-microvolt = <3300000>; 126 1.1 jmcneill regulator-max-microvolt = <3300000>; 127 1.1 jmcneill }; 128 1.1 jmcneill 129 1.1 jmcneill reg_h1_vbus: regulator-h1-vbus { 130 1.1 jmcneill compatible = "regulator-fixed"; 131 1.1 jmcneill regulator-name = "h1-vbus"; 132 1.1 jmcneill regulator-min-microvolt = <5000000>; 133 1.1 jmcneill regulator-max-microvolt = <5000000>; 134 1.1 jmcneill gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 135 1.1 jmcneill enable-active-high; 136 1.1 jmcneill }; 137 1.1 jmcneill 138 1.1 jmcneill reg_otg_vbus: regulator-otg-vbus { 139 1.1 jmcneill compatible = "regulator-fixed"; 140 1.1 jmcneill regulator-name = "otg-vbus"; 141 1.1 jmcneill regulator-min-microvolt = <5000000>; 142 1.1 jmcneill regulator-max-microvolt = <5000000>; 143 1.1 jmcneill gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 144 1.1 jmcneill enable-active-high; 145 1.1 jmcneill }; 146 1.1 jmcneill 147 1.1 jmcneill reg_wifi: regulator-wifi { 148 1.1 jmcneill compatible = "regulator-fixed"; 149 1.1 jmcneill pinctrl-names = "default"; 150 1.1 jmcneill pinctrl-0 = <&pinctrl_wifi_npd>; 151 1.1 jmcneill regulator-name = "wifi"; 152 1.1 jmcneill regulator-min-microvolt = <1800000>; 153 1.1 jmcneill regulator-max-microvolt = <1800000>; 154 1.1 jmcneill gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; 155 1.1 jmcneill enable-active-high; 156 1.1 jmcneill startup-delay-us = <70000>; 157 1.1 jmcneill }; 158 1.1 jmcneill 159 1.1 jmcneill sound { 160 1.1 jmcneill compatible = "simple-audio-card"; 161 1.1 jmcneill simple-audio-card,name = "prti6q-sgtl5000"; 162 1.1 jmcneill simple-audio-card,format = "i2s"; 163 1.1 jmcneill simple-audio-card,widgets = 164 1.1 jmcneill "Microphone", "Microphone Jack", 165 1.1 jmcneill "Line", "Line In Jack", 166 1.1 jmcneill "Headphone", "Headphone Jack", 167 1.1 jmcneill "Speaker", "External Speaker"; 168 1.1 jmcneill simple-audio-card,routing = 169 1.1 jmcneill "MIC_IN", "Microphone Jack", 170 1.1 jmcneill "LINE_IN", "Line In Jack", 171 1.1 jmcneill "Headphone Jack", "HP_OUT", 172 1.1 jmcneill "External Speaker", "LINE_OUT"; 173 1.1 jmcneill 174 1.1 jmcneill simple-audio-card,cpu { 175 1.1 jmcneill sound-dai = <&ssi1>; 176 1.1 jmcneill system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ 177 1.1 jmcneill }; 178 1.1 jmcneill 179 1.1 jmcneill simple-audio-card,codec { 180 1.1 jmcneill sound-dai = <&codec>; 181 1.1 jmcneill bitclock-master; 182 1.1 jmcneill frame-master; 183 1.1 jmcneill }; 184 1.1 jmcneill }; 185 1.1 jmcneill }; 186 1.1 jmcneill 187 1.1 jmcneill &audmux { 188 1.1 jmcneill pinctrl-names = "default"; 189 1.1 jmcneill pinctrl-0 = <&pinctrl_audmux>; 190 1.1 jmcneill status = "okay"; 191 1.1 jmcneill 192 1.1 jmcneill mux-ssi1 { 193 1.1 jmcneill fsl,audmux-port = <0>; 194 1.1 jmcneill fsl,port-config = < 195 1.1 jmcneill IMX_AUDMUX_V2_PTCR_SYN 0 196 1.1 jmcneill IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 197 1.1 jmcneill IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 198 1.1 jmcneill IMX_AUDMUX_V2_PTCR_TFSDIR 0 199 1.1 jmcneill IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 200 1.1 jmcneill >; 201 1.1 jmcneill }; 202 1.1 jmcneill 203 1.1 jmcneill mux-pins3 { 204 1.1 jmcneill fsl,audmux-port = <2>; 205 1.1 jmcneill fsl,port-config = < 206 1.1 jmcneill IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 207 1.1 jmcneill 0 IMX_AUDMUX_V2_PDCR_TXRXEN 208 1.1 jmcneill >; 209 1.1 jmcneill }; 210 1.1 jmcneill }; 211 1.1 jmcneill 212 1.1 jmcneill &can1 { 213 1.1 jmcneill pinctrl-names = "default"; 214 1.1 jmcneill pinctrl-0 = <&pinctrl_can1>; 215 1.1 jmcneill status = "okay"; 216 1.1 jmcneill }; 217 1.1 jmcneill 218 1.1 jmcneill &can2 { 219 1.1 jmcneill pinctrl-names = "default"; 220 1.1 jmcneill pinctrl-0 = <&pinctrl_can2>; 221 1.1 jmcneill status = "okay"; 222 1.1 jmcneill }; 223 1.1 jmcneill 224 1.1 jmcneill &clks { 225 1.1 jmcneill assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; 226 1.1 jmcneill assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; 227 1.1 jmcneill }; 228 1.1 jmcneill 229 1.1 jmcneill &ecspi1 { 230 1.1 jmcneill cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 231 1.1 jmcneill pinctrl-names = "default"; 232 1.1 jmcneill pinctrl-0 = <&pinctrl_ecspi1>; 233 1.1 jmcneill status = "okay"; 234 1.1 jmcneill 235 1.1 jmcneill flash@0 { 236 1.1 jmcneill compatible = "jedec,spi-nor"; 237 1.1 jmcneill reg = <0>; 238 1.1 jmcneill spi-max-frequency = <20000000>; 239 1.1 jmcneill }; 240 1.1 jmcneill }; 241 1.1 jmcneill 242 1.1 jmcneill &fec { 243 1.1 jmcneill pinctrl-names = "default"; 244 1.1 jmcneill pinctrl-0 = <&pinctrl_enet>; 245 1.1 jmcneill phy-mode = "rgmii-id"; 246 1.1 jmcneill phy-handle = <&rgmii_phy>; 247 1.1 jmcneill status = "okay"; 248 1.1 jmcneill 249 1.1 jmcneill mdio { 250 1.1 jmcneill #address-cells = <1>; 251 1.1 jmcneill #size-cells = <0>; 252 1.1 jmcneill 253 1.1 jmcneill /* Microchip KSZ9031RNX PHY */ 254 1.1 jmcneill rgmii_phy: ethernet-phy@0 { 255 1.1 jmcneill reg = <0>; 256 1.1 jmcneill interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 257 1.1 jmcneill reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 258 1.1 jmcneill reset-assert-us = <10000>; 259 1.1 jmcneill reset-deassert-us = <300>; 260 1.1 jmcneill }; 261 1.1 jmcneill }; 262 1.1 jmcneill }; 263 1.1 jmcneill 264 1.1 jmcneill &gpio1 { 265 1.1 jmcneill gpio-line-names = 266 1.1 jmcneill "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", 267 1.1 jmcneill "CAM2_MIRROR", "", "", "SMBALERT", 268 1.1 jmcneill "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3", 269 1.1 jmcneill "SDIO_D2", "SDIO_D1", "SDIO_D0", 270 1.1 jmcneill "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", 271 1.1 jmcneill "SD1_DATA3", "", "", 272 1.1 jmcneill "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "", 273 1.1 jmcneill "WL_IRQ", "ETH_MDC"; 274 1.1 jmcneill }; 275 1.1 jmcneill 276 1.1 jmcneill &gpio2 { 277 1.1 jmcneill gpio-line-names = 278 1.1 jmcneill "count0", "count1", "count2", "", "", "", "", "", 279 1.1 jmcneill "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", 280 1.1 jmcneill "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", 281 1.1 jmcneill "", "", "", "", "", "", "", "ON_SWITCH", 282 1.1 jmcneill "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; 283 1.1 jmcneill }; 284 1.1 jmcneill 285 1.1 jmcneill &gpio3 { 286 1.1 jmcneill gpio-line-names = 287 1.1 jmcneill "", "", "", "", "", "", "", "", 288 1.1 jmcneill "", "", "", "", "", "", "", "", 289 1.1 jmcneill "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", 290 1.1 jmcneill "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", 291 1.1 jmcneill "", "", "", "", "", "", "", ""; 292 1.1 jmcneill }; 293 1.1 jmcneill 294 1.1 jmcneill &gpio4 { 295 1.1 jmcneill gpio-line-names = 296 1.1 jmcneill "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", 297 1.1 jmcneill "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", 298 1.1 jmcneill "CAN2_SR", "CAN2_TX", "CAN2_RX", 299 1.1 jmcneill "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", 300 1.1 jmcneill "", "", "", "", "BL_EN", "BL_PWM", "", ""; 301 1.1 jmcneill }; 302 1.1 jmcneill 303 1.1 jmcneill &gpio5 { 304 1.1 jmcneill gpio-line-names = 305 1.1 jmcneill "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS", 306 1.1 jmcneill "PCIE_RESET", "", "", "", "", "", "", "", 307 1.1 jmcneill "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", 308 1.1 jmcneill "I2S_BITCLK", "I2S_DOUT", 309 1.1 jmcneill "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", 310 1.1 jmcneill "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; 311 1.1 jmcneill }; 312 1.1 jmcneill 313 1.1 jmcneill &gpio6 { 314 1.1 jmcneill gpio-line-names = 315 1.1 jmcneill "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", 316 1.1 jmcneill "ITU656_D6", "ITU656_D7", "", "", 317 1.1 jmcneill "", "", "", "", "", "", "", "", 318 1.1 jmcneill "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", 319 1.1 jmcneill "RGMII_TD3", 320 1.1 jmcneill "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", 321 1.1 jmcneill "RGMII_RD2", "RGMII_RD3", "", ""; 322 1.1 jmcneill }; 323 1.1 jmcneill 324 1.1 jmcneill &gpio7 { 325 1.1 jmcneill gpio-line-names = 326 1.1 jmcneill "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", 327 1.1 jmcneill "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", 328 1.1 jmcneill "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", 329 1.1 jmcneill "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", 330 1.1 jmcneill "", "", "", "", "", "", "", ""; 331 1.1 jmcneill }; 332 1.1 jmcneill 333 1.1 jmcneill &i2c1 { 334 1.1 jmcneill clock-frequency = <100000>; 335 1.1 jmcneill pinctrl-names = "default"; 336 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c1>; 337 1.1 jmcneill status = "okay"; 338 1.1 jmcneill 339 1.1 jmcneill codec: audio-codec@a { 340 1.1 jmcneill compatible = "fsl,sgtl5000"; 341 1.1 jmcneill reg = <0xa>; 342 1.1 jmcneill #sound-dai-cells = <0>; 343 1.1 jmcneill clocks = <&clks 201>; 344 1.1 jmcneill VDDA-supply = <®_3v3>; 345 1.1 jmcneill VDDIO-supply = <®_3v3>; 346 1.1 jmcneill VDDD-supply = <®_1v8>; 347 1.1 jmcneill }; 348 1.1 jmcneill 349 1.1 jmcneill video-decoder@5c { 350 1.1 jmcneill compatible = "ti,tvp5150"; 351 1.1 jmcneill reg = <0x5c>; 352 1.1 jmcneill #address-cells = <1>; 353 1.1 jmcneill #size-cells = <0>; 354 1.1 jmcneill 355 1.1 jmcneill port@0 { 356 1.1 jmcneill reg = <0>; 357 1.1 jmcneill 358 1.1 jmcneill tvp5150_comp0_in: endpoint { 359 1.1 jmcneill remote-endpoint = <&comp0_out>; 360 1.1 jmcneill }; 361 1.1 jmcneill }; 362 1.1 jmcneill 363 1.1 jmcneill /* Output port 2 is video output pad */ 364 1.1 jmcneill port@2 { 365 1.1 jmcneill reg = <2>; 366 1.1 jmcneill 367 1.1 jmcneill tvp5151_to_ipu1_csi0_mux: endpoint { 368 1.1 jmcneill remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 369 1.1 jmcneill }; 370 1.1 jmcneill }; 371 1.1 jmcneill }; 372 1.1 jmcneill }; 373 1.1 jmcneill 374 1.1 jmcneill &i2c3 { 375 1.1 jmcneill clock-frequency = <100000>; 376 1.1 jmcneill pinctrl-names = "default"; 377 1.1 jmcneill pinctrl-0 = <&pinctrl_i2c3>; 378 1.1 jmcneill status = "okay"; 379 1.1 jmcneill 380 1.1 jmcneill adc@49 { 381 1.1 jmcneill compatible = "ti,ads1015"; 382 1.1 jmcneill reg = <0x49>; 383 1.1 jmcneill #address-cells = <1>; 384 1.1 jmcneill #size-cells = <0>; 385 1.1 jmcneill 386 1.1 jmcneill channel@4 { 387 1.1 jmcneill reg = <4>; 388 1.1 jmcneill ti,gain = <3>; 389 1.1 jmcneill ti,datarate = <3>; 390 1.1 jmcneill }; 391 1.1 jmcneill 392 1.1 jmcneill channel@5 { 393 1.1 jmcneill reg = <5>; 394 1.1 jmcneill ti,gain = <3>; 395 1.1 jmcneill ti,datarate = <3>; 396 1.1 jmcneill }; 397 1.1 jmcneill 398 1.1 jmcneill channel@6 { 399 1.1 jmcneill reg = <6>; 400 1.1 jmcneill ti,gain = <3>; 401 1.1 jmcneill ti,datarate = <3>; 402 1.1 jmcneill }; 403 1.1 jmcneill 404 1.1 jmcneill channel@7 { 405 1.1 jmcneill reg = <7>; 406 1.1 jmcneill ti,gain = <3>; 407 1.1 jmcneill ti,datarate = <3>; 408 1.1 jmcneill }; 409 1.1 jmcneill }; 410 1.1 jmcneill 411 1.1 jmcneill rtc@51 { 412 1.1 jmcneill compatible = "nxp,pcf8563"; 413 1.1 jmcneill reg = <0x51>; 414 1.1 jmcneill }; 415 1.1 jmcneill 416 1.1 jmcneill temperature-sensor@70 { 417 1.1 jmcneill compatible = "ti,tmp103"; 418 1.1 jmcneill reg = <0x70>; 419 1.1 jmcneill }; 420 1.1 jmcneill }; 421 1.1 jmcneill 422 1.1 jmcneill &ipu1_csi0 { 423 1.1 jmcneill pinctrl-names = "default"; 424 1.1 jmcneill pinctrl-0 = <&pinctrl_ipu1_csi0>; 425 1.1 jmcneill status = "okay"; 426 1.1 jmcneill }; 427 1.1 jmcneill 428 1.1 jmcneill &ipu1_csi0_mux_from_parallel_sensor { 429 1.1 jmcneill remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; 430 1.1 jmcneill }; 431 1.1 jmcneill 432 1.1 jmcneill &ldb { 433 1.1 jmcneill status = "okay"; 434 1.1 jmcneill 435 1.1 jmcneill lvds-channel@0 { 436 1.1 jmcneill status = "okay"; 437 1.1 jmcneill 438 1.1 jmcneill port@4 { 439 1.1 jmcneill reg = <4>; 440 1.1 jmcneill 441 1.1 jmcneill lvds0_out: endpoint { 442 1.1 jmcneill remote-endpoint = <&panel_in>; 443 1.1 jmcneill }; 444 1.1 jmcneill }; 445 1.1 jmcneill }; 446 1.1 jmcneill }; 447 1.1 jmcneill 448 1.1 jmcneill &pcie { 449 1.1 jmcneill status = "okay"; 450 1.1 jmcneill }; 451 1.1 jmcneill 452 1.1 jmcneill &pwm1 { 453 1.1 jmcneill pinctrl-names = "default"; 454 1.1 jmcneill pinctrl-0 = <&pinctrl_pwm1>; 455 1.1 jmcneill status = "okay"; 456 1.1 jmcneill }; 457 1.1 jmcneill 458 1.1 jmcneill &ssi1 { 459 1.1 jmcneill #sound-dai-cells = <0>; 460 1.1 jmcneill fsl,mode = "ac97-slave"; 461 1.1 jmcneill status = "okay"; 462 1.1 jmcneill }; 463 1.1 jmcneill 464 1.1 jmcneill &uart1 { 465 1.1 jmcneill pinctrl-names = "default"; 466 1.1 jmcneill pinctrl-0 = <&pinctrl_uart1>; 467 1.1 jmcneill status = "okay"; 468 1.1 jmcneill }; 469 1.1 jmcneill 470 1.1 jmcneill &uart2 { 471 1.1 jmcneill pinctrl-names = "default"; 472 1.1 jmcneill pinctrl-0 = <&pinctrl_uart2>; 473 1.1 jmcneill status = "okay"; 474 1.1 jmcneill }; 475 1.1 jmcneill 476 1.1 jmcneill &uart3 { 477 1.1 jmcneill pinctrl-names = "default"; 478 1.1 jmcneill pinctrl-0 = <&pinctrl_uart3>; 479 1.1 jmcneill status = "okay"; 480 1.1 jmcneill }; 481 1.1 jmcneill 482 1.1 jmcneill &uart4 { 483 1.1 jmcneill pinctrl-names = "default"; 484 1.1 jmcneill pinctrl-0 = <&pinctrl_uart4>; 485 1.1 jmcneill status = "okay"; 486 1.1 jmcneill }; 487 1.1 jmcneill 488 1.1 jmcneill &uart5 { 489 1.1 jmcneill pinctrl-names = "default"; 490 1.1 jmcneill pinctrl-0 = <&pinctrl_uart5>; 491 1.1 jmcneill status = "okay"; 492 1.1 jmcneill }; 493 1.1 jmcneill 494 1.1 jmcneill &usbh1 { 495 1.1 jmcneill vbus-supply = <®_h1_vbus>; 496 1.1 jmcneill pinctrl-names = "default"; 497 1.1 jmcneill phy_type = "utmi"; 498 1.1 jmcneill dr_mode = "host"; 499 1.1 jmcneill status = "okay"; 500 1.1 jmcneill }; 501 1.1 jmcneill 502 1.1 jmcneill &usbotg { 503 1.1 jmcneill vbus-supply = <®_otg_vbus>; 504 1.1 jmcneill pinctrl-names = "default"; 505 1.1 jmcneill pinctrl-0 = <&pinctrl_usbotg>; 506 1.1 jmcneill phy_type = "utmi"; 507 1.1 jmcneill dr_mode = "host"; 508 1.1 jmcneill disable-over-current; 509 1.1 jmcneill status = "okay"; 510 1.1 jmcneill }; 511 1.1 jmcneill 512 1.1 jmcneill &usdhc1 { 513 1.1 jmcneill pinctrl-names = "default"; 514 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc1>; 515 1.1 jmcneill cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 516 1.1 jmcneill no-1-8-v; 517 1.1 jmcneill disable-wp; 518 1.1 jmcneill cap-sd-highspeed; 519 1.1 jmcneill no-mmc; 520 1.1 jmcneill no-sdio; 521 1.1 jmcneill status = "okay"; 522 1.1 jmcneill }; 523 1.1 jmcneill 524 1.1 jmcneill &usdhc2 { 525 1.1 jmcneill pinctrl-names = "default"; 526 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc2>; 527 1.1 jmcneill vmmc-supply = <®_wifi>; 528 1.1 jmcneill non-removable; 529 1.1 jmcneill cap-power-off-card; 530 1.1 jmcneill keep-power-in-suspend; 531 1.1 jmcneill no-1-8-v; 532 1.1 jmcneill no-mmc; 533 1.1 jmcneill no-sd; 534 1.1 jmcneill status = "okay"; 535 1.1 jmcneill 536 1.1 jmcneill wifi { 537 1.1 jmcneill compatible = "ti,wl1271"; 538 1.1 jmcneill interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; 539 1.1 jmcneill ref-clock-frequency = "38400000"; 540 1.1 jmcneill tcxo-clock-frequency = "19200000"; 541 1.1 jmcneill }; 542 1.1 jmcneill }; 543 1.1 jmcneill 544 1.1 jmcneill &usdhc3 { 545 1.1 jmcneill pinctrl-names = "default"; 546 1.1 jmcneill pinctrl-0 = <&pinctrl_usdhc3>; 547 1.1 jmcneill bus-width = <8>; 548 1.1 jmcneill no-1-8-v; 549 1.1 jmcneill non-removable; 550 1.1 jmcneill no-sd; 551 1.1 jmcneill no-sdio; 552 1.1 jmcneill status = "okay"; 553 1.1 jmcneill }; 554 1.1 jmcneill 555 1.1 jmcneill &iomuxc { 556 1.1 jmcneill pinctrl-names = "default"; 557 1.1 jmcneill pinctrl-0 = <&pinctrl_hog>; 558 1.1 jmcneill 559 1.1 jmcneill pinctrl_audmux: audmuxgrp { 560 1.1 jmcneill fsl,pins = < 561 1.1 jmcneill /* SGTL5000 sys_mclk */ 562 1.1 jmcneill MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 563 1.1 jmcneill MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 564 1.1 jmcneill MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 565 1.1 jmcneill MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 566 1.1 jmcneill MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 567 1.1 jmcneill >; 568 1.1 jmcneill }; 569 1.1 jmcneill 570 1.1 jmcneill pinctrl_backlight: backlightgrp { 571 1.1 jmcneill fsl,pins = < 572 1.1 jmcneill MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 573 1.1 jmcneill >; 574 1.1 jmcneill }; 575 1.1 jmcneill 576 1.1 jmcneill pinctrl_can1: can1grp { 577 1.1 jmcneill fsl,pins = < 578 1.1 jmcneill MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 579 1.1 jmcneill MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 580 1.1 jmcneill /* CAN1_SR */ 581 1.1 jmcneill MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 582 1.1 jmcneill /* CAN1_TERM */ 583 1.1 jmcneill MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 584 1.1 jmcneill >; 585 1.1 jmcneill }; 586 1.1 jmcneill 587 1.1 jmcneill pinctrl_can2: can2grp { 588 1.1 jmcneill fsl,pins = < 589 1.1 jmcneill MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 590 1.1 jmcneill MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 591 1.1 jmcneill /* CAN2_SR */ 592 1.1 jmcneill MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 593 1.1 jmcneill >; 594 1.1 jmcneill }; 595 1.1 jmcneill 596 1.1 jmcneill pinctrl_counter0: counter0grp { 597 1.1 jmcneill fsl,pins = < 598 1.1 jmcneill MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 599 1.1 jmcneill >; 600 1.1 jmcneill }; 601 1.1 jmcneill 602 1.1 jmcneill pinctrl_counter1: counter1grp { 603 1.1 jmcneill fsl,pins = < 604 1.1 jmcneill MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 605 1.1 jmcneill >; 606 1.1 jmcneill }; 607 1.1 jmcneill 608 1.1 jmcneill pinctrl_counter2: counter2grp { 609 1.1 jmcneill fsl,pins = < 610 1.1 jmcneill MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 611 1.1 jmcneill >; 612 1.1 jmcneill }; 613 1.1 jmcneill 614 1.1 jmcneill pinctrl_ecspi1: ecspi1grp { 615 1.1 jmcneill fsl,pins = < 616 1.1 jmcneill MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 617 1.1 jmcneill MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 618 1.1 jmcneill MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 619 1.1 jmcneill /* CS */ 620 1.1 jmcneill MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 621 1.1 jmcneill >; 622 1.1 jmcneill }; 623 1.1 jmcneill 624 1.1 jmcneill pinctrl_enet: enetgrp { 625 1.1 jmcneill fsl,pins = < 626 1.1 jmcneill MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 627 1.1 jmcneill MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 628 1.1 jmcneill MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 629 1.1 jmcneill MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 630 1.1 jmcneill MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 631 1.1 jmcneill MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 632 1.1 jmcneill MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 633 1.1 jmcneill MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 634 1.1 jmcneill MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 635 1.1 jmcneill MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 636 1.1 jmcneill MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 637 1.1 jmcneill MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 638 1.1 jmcneill MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 639 1.1 jmcneill MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 640 1.1 jmcneill MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 641 1.1 jmcneill /* Phy reset */ 642 1.1 jmcneill MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 643 1.1 jmcneill MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 644 1.1 jmcneill >; 645 1.1 jmcneill }; 646 1.1 jmcneill 647 1.1 jmcneill pinctrl_hog: hoggrp { 648 1.1 jmcneill fsl,pins = < 649 1.1 jmcneill /* ITU656_nRESET */ 650 1.1 jmcneill MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 651 1.1 jmcneill /* CAM1_MIRROR */ 652 1.1 jmcneill MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 653 1.1 jmcneill /* CAM2_MIRROR */ 654 1.1 jmcneill MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 655 1.1 jmcneill /* CAM_nDETECT */ 656 1.1 jmcneill MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 657 1.1 jmcneill /* nON_SWITCH */ 658 1.1 jmcneill MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 659 1.1 jmcneill /* ISB_IN1 */ 660 1.1 jmcneill MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 661 1.1 jmcneill /* ISB_nIN2 */ 662 1.1 jmcneill MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 663 1.1 jmcneill /* WARN_LIGHT */ 664 1.1 jmcneill MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 665 1.1 jmcneill /* ON2_FB */ 666 1.1 jmcneill MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 667 1.1 jmcneill /* YACO_nIRQ */ 668 1.1 jmcneill MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 669 1.1 jmcneill /* YACO_BOOT0 */ 670 1.1 jmcneill MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 671 1.1 jmcneill /* YACO_nRESET */ 672 1.1 jmcneill MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 673 1.1 jmcneill /* FORCE_ON1 */ 674 1.1 jmcneill MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 675 1.1 jmcneill /* AUDIO_nRESET */ 676 1.1 jmcneill MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 677 1.1 jmcneill /* ITU656_nPDN */ 678 1.1 jmcneill MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 679 1.1 jmcneill 680 1.1 jmcneill /* HW revision detect */ 681 1.1 jmcneill /* REV_ID0 */ 682 1.1 jmcneill MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 683 1.1 jmcneill /* REV_ID1 */ 684 1.1 jmcneill MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 685 1.1 jmcneill /* REV_ID2 */ 686 1.1 jmcneill MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 687 1.1 jmcneill /* REV_ID3 */ 688 1.1 jmcneill MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 689 1.1 jmcneill /* REV_ID4 */ 690 1.1 jmcneill MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 691 1.1 jmcneill 692 1.1 jmcneill /* New in HW revision 1 */ 693 1.1 jmcneill /* ON1_FB */ 694 1.1 jmcneill MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 695 1.1 jmcneill /* DIP1_FB */ 696 1.1 jmcneill MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 697 1.1 jmcneill 698 1.1 jmcneill /* New in UT2: FIXME: ISB PWM should start off, PD */ 699 1.1 jmcneill /* ISB_LED_PWM */ 700 1.1 jmcneill MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0 701 1.1 jmcneill >; 702 1.1 jmcneill }; 703 1.1 jmcneill 704 1.1 jmcneill pinctrl_i2c1: i2c1grp { 705 1.1 jmcneill fsl,pins = < 706 1.1 jmcneill MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 707 1.1 jmcneill MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 708 1.1 jmcneill >; 709 1.1 jmcneill }; 710 1.1 jmcneill 711 1.1 jmcneill pinctrl_i2c3: i2c3grp { 712 1.1 jmcneill fsl,pins = < 713 1.1 jmcneill MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 714 1.1 jmcneill MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 715 1.1 jmcneill >; 716 1.1 jmcneill }; 717 1.1 jmcneill 718 1.1 jmcneill pinctrl_ipu1_csi0: ipu1csi0grp { 719 1.1 jmcneill fsl,pins = < 720 1.1 jmcneill MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 721 1.1 jmcneill MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 722 1.1 jmcneill MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 723 1.1 jmcneill MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 724 1.1 jmcneill MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 725 1.1 jmcneill MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 726 1.1 jmcneill MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 727 1.1 jmcneill MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 728 1.1 jmcneill MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 729 1.1 jmcneill >; 730 1.1 jmcneill }; 731 1.1 jmcneill 732 1.1 jmcneill pinctrl_leds: ledsgrp { 733 1.1 jmcneill fsl,pins = < 734 1.1 jmcneill /* DEBUG0 */ 735 1.1 jmcneill MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 736 1.1 jmcneill /* DEBUG1 */ 737 1.1 jmcneill MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 738 1.1 jmcneill /* POWER_LED */ 739 1.1 jmcneill MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 740 1.1 jmcneill >; 741 1.1 jmcneill }; 742 1.1 jmcneill 743 1.1 jmcneill pinctrl_pwm1: pwm1grp { 744 1.1 jmcneill fsl,pins = < 745 1.1 jmcneill MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 746 1.1 jmcneill >; 747 1.1 jmcneill }; 748 1.1 jmcneill 749 1.1 jmcneill /* YaCO AUX Uart */ 750 1.1 jmcneill pinctrl_uart1: uart1grp { 751 1.1 jmcneill fsl,pins = < 752 1.1 jmcneill MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 753 1.1 jmcneill MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 754 1.1 jmcneill >; 755 1.1 jmcneill }; 756 1.1 jmcneill 757 1.1 jmcneill pinctrl_uart2: uart2grp { 758 1.1 jmcneill fsl,pins = < 759 1.1 jmcneill MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 760 1.1 jmcneill MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 761 1.1 jmcneill MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 762 1.1 jmcneill MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 763 1.1 jmcneill >; 764 1.1 jmcneill }; 765 1.1 jmcneill 766 1.1 jmcneill /* YaCO Touchscreen UART */ 767 1.1 jmcneill pinctrl_uart3: uart3grp { 768 1.1 jmcneill fsl,pins = < 769 1.1 jmcneill MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 770 1.1 jmcneill MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 771 1.1 jmcneill >; 772 1.1 jmcneill }; 773 1.1 jmcneill 774 1.1 jmcneill pinctrl_uart4: uart4grp { 775 1.1 jmcneill fsl,pins = < 776 1.1 jmcneill MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 777 1.1 jmcneill MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 778 1.1 jmcneill >; 779 1.1 jmcneill }; 780 1.1 jmcneill 781 1.1 jmcneill pinctrl_uart5: uart5grp { 782 1.1 jmcneill fsl,pins = < 783 1.1 jmcneill MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 784 1.1 jmcneill MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 785 1.1 jmcneill >; 786 1.1 jmcneill }; 787 1.1 jmcneill 788 1.1 jmcneill pinctrl_usbotg: usbotggrp { 789 1.1 jmcneill fsl,pins = < 790 1.1 jmcneill MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 791 1.1 jmcneill /* power enable, high active */ 792 1.1 jmcneill MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 793 1.1 jmcneill >; 794 1.1 jmcneill }; 795 1.1 jmcneill 796 1.1 jmcneill pinctrl_usdhc1: usdhc1grp { 797 1.1 jmcneill fsl,pins = < 798 1.1 jmcneill MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 799 1.1 jmcneill MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 800 1.1 jmcneill MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 801 1.1 jmcneill MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 802 1.1 jmcneill MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 803 1.1 jmcneill MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 804 1.1 jmcneill MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 805 1.1 jmcneill >; 806 1.1 jmcneill }; 807 1.1 jmcneill 808 1.1 jmcneill pinctrl_usdhc2: usdhc2grp { 809 1.1 jmcneill fsl,pins = < 810 1.1 jmcneill MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 811 1.1 jmcneill MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 812 1.1 jmcneill MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 813 1.1 jmcneill MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 814 1.1 jmcneill MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 815 1.1 jmcneill MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 816 1.1 jmcneill /* WL12xx IRQ */ 817 1.1 jmcneill MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 818 1.1 jmcneill >; 819 1.1 jmcneill }; 820 1.1 jmcneill 821 1.1 jmcneill pinctrl_usdhc3: usdhc3grp { 822 1.1 jmcneill fsl,pins = < 823 1.1 jmcneill MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 824 1.1 jmcneill MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 825 1.1 jmcneill MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 826 1.1 jmcneill MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 827 1.1 jmcneill MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 828 1.1 jmcneill MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 829 1.1 jmcneill MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 830 1.1 jmcneill MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 831 1.1 jmcneill MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 832 1.1 jmcneill MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 833 1.1 jmcneill MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 834 1.1 jmcneill >; 835 1.1 jmcneill }; 836 1.1 jmcneill 837 1.1 jmcneill pinctrl_wifi_npd: wifinpdgrp { 838 1.1 jmcneill fsl,pins = < 839 1.1 jmcneill MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 840 1.1 jmcneill >; 841 1.1 jmcneill }; 842 1.1 jmcneill }; 843