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      1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2 /*
      3  * Copyright (c) 2014 Protonic Holland
      4  * Copyright (c) 2020 Oleksij Rempel <kernel (a] pengutronix.de>, Pengutronix
      5  */
      6 
      7 #include <dt-bindings/display/sdtv-standards.h>
      8 #include <dt-bindings/gpio/gpio.h>
      9 #include <dt-bindings/input/input.h>
     10 #include <dt-bindings/leds/common.h>
     11 #include <dt-bindings/media/tvp5150.h>
     12 #include <dt-bindings/sound/fsl-imx-audmux.h>
     13 
     14 / {
     15 	chosen {
     16 		stdout-path = &uart4;
     17 	};
     18 
     19 	backlight: backlight {
     20 		compatible = "pwm-backlight";
     21 		pinctrl-names = "default";
     22 		pinctrl-0 = <&pinctrl_backlight>;
     23 		pwms = <&pwm1 0 5000000 0>;
     24 		brightness-levels = <0 16 64 255>;
     25 		num-interpolated-steps = <16>;
     26 		default-brightness-level = <1>;
     27 		power-supply = <&reg_3v3>;
     28 		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
     29 	};
     30 
     31 	connector {
     32 		compatible = "composite-video-connector";
     33 		label = "Composite0";
     34 		sdtv-standards = <SDTV_STD_PAL_B>;
     35 
     36 		port {
     37 			comp0_out: endpoint {
     38 				remote-endpoint = <&tvp5150_comp0_in>;
     39 			};
     40 		};
     41 	};
     42 
     43 	counter-0 {
     44 		compatible = "interrupt-counter";
     45 		pinctrl-names = "default";
     46 		pinctrl-0 = <&pinctrl_counter0>;
     47 		gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
     48 	};
     49 
     50 	counter-1 {
     51 		compatible = "interrupt-counter";
     52 		pinctrl-names = "default";
     53 		pinctrl-0 = <&pinctrl_counter1>;
     54 		gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
     55 	};
     56 
     57 	counter-2 {
     58 		compatible = "interrupt-counter";
     59 		pinctrl-names = "default";
     60 		pinctrl-0 = <&pinctrl_counter2>;
     61 		gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
     62 	};
     63 
     64 	gpio-keys {
     65 		compatible = "gpio-keys";
     66 		autorepeat;
     67 
     68 		power {
     69 			label = "Power Button";
     70 			gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
     71 			linux,code = <KEY_POWER>;
     72 			wakeup-source;
     73 		};
     74 	};
     75 
     76 	leds {
     77 		compatible = "gpio-leds";
     78 		pinctrl-names = "default";
     79 		pinctrl-0 = <&pinctrl_leds>;
     80 
     81 		led-0 {
     82 			label = "LED_DI0_DEBUG_0";
     83 			function = LED_FUNCTION_HEARTBEAT;
     84 			gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
     85 			linux,default-trigger = "heartbeat";
     86 		};
     87 
     88 		led-1 {
     89 			label = "LED_DI0_DEBUG_1";
     90 			function = LED_FUNCTION_DISK;
     91 			gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
     92 			linux,default-trigger = "disk-activity";
     93 		};
     94 
     95 		led-2 {
     96 			label = "POWER_LED";
     97 			function = LED_FUNCTION_POWER;
     98 			gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
     99 			default-state = "on";
    100 		};
    101 	};
    102 
    103 	panel {
    104 		compatible = "kyo,tcg121xglp";
    105 		backlight = <&backlight>;
    106 		power-supply = <&reg_3v3>;
    107 
    108 		port {
    109 			panel_in: endpoint {
    110 				remote-endpoint = <&lvds0_out>;
    111 			};
    112 		};
    113 	};
    114 
    115 	reg_1v8: regulator-1v8 {
    116 		compatible = "regulator-fixed";
    117 		regulator-name = "1v8";
    118 		regulator-min-microvolt = <1800000>;
    119 		regulator-max-microvolt = <1800000>;
    120 	};
    121 
    122 	reg_3v3: regulator-3v3 {
    123 		compatible = "regulator-fixed";
    124 		regulator-name = "3v3";
    125 		regulator-min-microvolt = <3300000>;
    126 		regulator-max-microvolt = <3300000>;
    127 	};
    128 
    129 	reg_h1_vbus: regulator-h1-vbus {
    130 		compatible = "regulator-fixed";
    131 		regulator-name = "h1-vbus";
    132 		regulator-min-microvolt = <5000000>;
    133 		regulator-max-microvolt = <5000000>;
    134 		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
    135 		enable-active-high;
    136 	};
    137 
    138 	reg_otg_vbus: regulator-otg-vbus {
    139 		compatible = "regulator-fixed";
    140 		regulator-name = "otg-vbus";
    141 		regulator-min-microvolt = <5000000>;
    142 		regulator-max-microvolt = <5000000>;
    143 		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
    144 		enable-active-high;
    145 	};
    146 
    147 	reg_wifi: regulator-wifi {
    148 		compatible = "regulator-fixed";
    149 		pinctrl-names = "default";
    150 		pinctrl-0 = <&pinctrl_wifi_npd>;
    151 		regulator-name = "wifi";
    152 		regulator-min-microvolt = <1800000>;
    153 		regulator-max-microvolt = <1800000>;
    154 		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
    155 		enable-active-high;
    156 		startup-delay-us = <70000>;
    157 	};
    158 
    159 	sound {
    160 		compatible = "simple-audio-card";
    161 		simple-audio-card,name = "prti6q-sgtl5000";
    162 		simple-audio-card,format = "i2s";
    163 		simple-audio-card,widgets =
    164 			"Microphone", "Microphone Jack",
    165 			"Line", "Line In Jack",
    166 			"Headphone", "Headphone Jack",
    167 			"Speaker", "External Speaker";
    168 		simple-audio-card,routing =
    169 			"MIC_IN", "Microphone Jack",
    170 			"LINE_IN", "Line In Jack",
    171 			"Headphone Jack", "HP_OUT",
    172 			"External Speaker", "LINE_OUT";
    173 
    174 		simple-audio-card,cpu {
    175 			sound-dai = <&ssi1>;
    176 			system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */
    177 		};
    178 
    179 		simple-audio-card,codec {
    180 			sound-dai = <&codec>;
    181 			bitclock-master;
    182 			frame-master;
    183 		};
    184 	};
    185 };
    186 
    187 &audmux {
    188 	pinctrl-names = "default";
    189 	pinctrl-0 = <&pinctrl_audmux>;
    190 	status = "okay";
    191 
    192 	mux-ssi1 {
    193 		fsl,audmux-port = <0>;
    194 		fsl,port-config = <
    195 			IMX_AUDMUX_V2_PTCR_SYN		0
    196 			IMX_AUDMUX_V2_PTCR_TFSEL(2)	0
    197 			IMX_AUDMUX_V2_PTCR_TCSEL(2)	0
    198 			IMX_AUDMUX_V2_PTCR_TFSDIR	0
    199 			IMX_AUDMUX_V2_PTCR_TCLKDIR	IMX_AUDMUX_V2_PDCR_RXDSEL(2)
    200 		>;
    201 	};
    202 
    203 	mux-pins3 {
    204 		fsl,audmux-port = <2>;
    205 		fsl,port-config = <
    206 			IMX_AUDMUX_V2_PTCR_SYN		IMX_AUDMUX_V2_PDCR_RXDSEL(0)
    207 			0				IMX_AUDMUX_V2_PDCR_TXRXEN
    208 		>;
    209 	};
    210 };
    211 
    212 &can1 {
    213 	pinctrl-names = "default";
    214 	pinctrl-0 = <&pinctrl_can1>;
    215 	status = "okay";
    216 };
    217 
    218 &can2 {
    219 	pinctrl-names = "default";
    220 	pinctrl-0 = <&pinctrl_can2>;
    221 	status = "okay";
    222 };
    223 
    224 &clks {
    225 	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
    226 	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
    227 };
    228 
    229 &ecspi1 {
    230 	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
    231 	pinctrl-names = "default";
    232 	pinctrl-0 = <&pinctrl_ecspi1>;
    233 	status = "okay";
    234 
    235 	flash@0 {
    236 		compatible = "jedec,spi-nor";
    237 		reg = <0>;
    238 		spi-max-frequency = <20000000>;
    239 	};
    240 };
    241 
    242 &fec {
    243 	pinctrl-names = "default";
    244 	pinctrl-0 = <&pinctrl_enet>;
    245 	phy-mode = "rgmii-id";
    246 	phy-handle = <&rgmii_phy>;
    247 	status = "okay";
    248 
    249 	mdio {
    250 		#address-cells = <1>;
    251 		#size-cells = <0>;
    252 
    253 		/* Microchip KSZ9031RNX PHY */
    254 		rgmii_phy: ethernet-phy@0 {
    255 			reg = <0>;
    256 			interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
    257 			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
    258 			reset-assert-us = <10000>;
    259 			reset-deassert-us = <300>;
    260 		};
    261 	};
    262 };
    263 
    264 &gpio1 {
    265 	gpio-line-names =
    266 		"CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
    267 			"CAM2_MIRROR", "", "", "SMBALERT",
    268 		"DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3",
    269 			"SDIO_D2", "SDIO_D1", "SDIO_D0",
    270 		"SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
    271 			"SD1_DATA3", "", "",
    272 		"", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "",
    273 			"WL_IRQ", "ETH_MDC";
    274 };
    275 
    276 &gpio2 {
    277 	gpio-line-names =
    278 		"count0", "count1", "count2", "", "", "", "", "",
    279 		"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
    280 			"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
    281 		"", "", "", "", "", "", "", "ON_SWITCH",
    282 		"POWER_LED", "", "ECSPI2_SS0", "", "", "", "", "";
    283 };
    284 
    285 &gpio3 {
    286 	gpio-line-names =
    287 		"", "", "", "", "", "", "", "",
    288 		"", "", "", "", "", "", "", "",
    289 		"ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
    290 			"CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ",
    291 		"", "", "", "", "", "", "", "";
    292 };
    293 
    294 &gpio4 {
    295 	gpio-line-names =
    296 		"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
    297 		"UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
    298 			"CAN2_SR", "CAN2_TX", "CAN2_RX",
    299 		"LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "",
    300 		"", "", "", "", "BL_EN", "BL_PWM", "", "";
    301 };
    302 
    303 &gpio5 {
    304 	gpio-line-names =
    305 		"", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS",
    306 		"PCIE_RESET", "", "", "", "", "", "", "",
    307 		"", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
    308 			"I2S_BITCLK", "I2S_DOUT",
    309 		"I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
    310 			"YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
    311 };
    312 
    313 &gpio6 {
    314 	gpio-line-names =
    315 		"ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
    316 			"ITU656_D6", "ITU656_D7", "", "",
    317 		"", "", "", "", "", "", "", "",
    318 		"", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
    319 			"RGMII_TD3",
    320 		"RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
    321 			"RGMII_RD2", "RGMII_RD3", "", "";
    322 };
    323 
    324 &gpio7 {
    325 	gpio-line-names =
    326 		"EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0",
    327 			"EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3",
    328 		"EMMC_RST", "", "", "", "CAM_DETECT", "", "", "",
    329 		"", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "",
    330 		"", "", "", "", "", "", "", "";
    331 };
    332 
    333 &i2c1 {
    334 	clock-frequency = <100000>;
    335 	pinctrl-names = "default";
    336 	pinctrl-0 = <&pinctrl_i2c1>;
    337 	status = "okay";
    338 
    339 	codec: audio-codec@a {
    340 		compatible = "fsl,sgtl5000";
    341 		reg = <0xa>;
    342 		#sound-dai-cells = <0>;
    343 		clocks = <&clks 201>;
    344 		VDDA-supply = <&reg_3v3>;
    345 		VDDIO-supply = <&reg_3v3>;
    346 		VDDD-supply = <&reg_1v8>;
    347 	};
    348 
    349 	video-decoder@5c {
    350 		compatible = "ti,tvp5150";
    351 		reg = <0x5c>;
    352 		#address-cells = <1>;
    353 		#size-cells = <0>;
    354 
    355 		port@0 {
    356 			reg = <0>;
    357 
    358 			tvp5150_comp0_in: endpoint {
    359 				remote-endpoint = <&comp0_out>;
    360 			};
    361 		};
    362 
    363 		/* Output port 2 is video output pad */
    364 		port@2 {
    365 			reg = <2>;
    366 
    367 			tvp5151_to_ipu1_csi0_mux: endpoint {
    368 				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
    369 			};
    370 		};
    371 	};
    372 };
    373 
    374 &i2c3 {
    375 	clock-frequency = <100000>;
    376 	pinctrl-names = "default";
    377 	pinctrl-0 = <&pinctrl_i2c3>;
    378 	status = "okay";
    379 
    380 	adc@49 {
    381 		compatible = "ti,ads1015";
    382 		reg = <0x49>;
    383 		#address-cells = <1>;
    384 		#size-cells = <0>;
    385 
    386 		channel@4 {
    387 			reg = <4>;
    388 			ti,gain = <3>;
    389 			ti,datarate = <3>;
    390 		};
    391 
    392 		channel@5 {
    393 			reg = <5>;
    394 			ti,gain = <3>;
    395 			ti,datarate = <3>;
    396 		};
    397 
    398 		channel@6 {
    399 			reg = <6>;
    400 			ti,gain = <3>;
    401 			ti,datarate = <3>;
    402 		};
    403 
    404 		channel@7 {
    405 			reg = <7>;
    406 			ti,gain = <3>;
    407 			ti,datarate = <3>;
    408 		};
    409 	};
    410 
    411 	rtc@51 {
    412 		compatible = "nxp,pcf8563";
    413 		reg = <0x51>;
    414 	};
    415 
    416 	temperature-sensor@70 {
    417 		compatible = "ti,tmp103";
    418 		reg = <0x70>;
    419 	};
    420 };
    421 
    422 &ipu1_csi0 {
    423 	pinctrl-names = "default";
    424 	pinctrl-0 = <&pinctrl_ipu1_csi0>;
    425 	status = "okay";
    426 };
    427 
    428 &ipu1_csi0_mux_from_parallel_sensor {
    429 	remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
    430 };
    431 
    432 &ldb {
    433 	status = "okay";
    434 
    435 	lvds-channel@0 {
    436 		status = "okay";
    437 
    438 		port@4 {
    439 			reg = <4>;
    440 
    441 			lvds0_out: endpoint {
    442 				remote-endpoint = <&panel_in>;
    443 			};
    444 		};
    445 	};
    446 };
    447 
    448 &pcie {
    449 	status = "okay";
    450 };
    451 
    452 &pwm1 {
    453 	pinctrl-names = "default";
    454 	pinctrl-0 = <&pinctrl_pwm1>;
    455 	status = "okay";
    456 };
    457 
    458 &ssi1 {
    459 	#sound-dai-cells = <0>;
    460 	fsl,mode = "ac97-slave";
    461 	status = "okay";
    462 };
    463 
    464 &uart1 {
    465 	pinctrl-names = "default";
    466 	pinctrl-0 = <&pinctrl_uart1>;
    467 	status = "okay";
    468 };
    469 
    470 &uart2 {
    471 	pinctrl-names = "default";
    472 	pinctrl-0 = <&pinctrl_uart2>;
    473 	status = "okay";
    474 };
    475 
    476 &uart3 {
    477 	pinctrl-names = "default";
    478 	pinctrl-0 = <&pinctrl_uart3>;
    479 	status = "okay";
    480 };
    481 
    482 &uart4 {
    483 	pinctrl-names = "default";
    484 	pinctrl-0 = <&pinctrl_uart4>;
    485 	status = "okay";
    486 };
    487 
    488 &uart5 {
    489 	pinctrl-names = "default";
    490 	pinctrl-0 = <&pinctrl_uart5>;
    491 	status = "okay";
    492 };
    493 
    494 &usbh1 {
    495 	vbus-supply = <&reg_h1_vbus>;
    496 	pinctrl-names = "default";
    497 	phy_type = "utmi";
    498 	dr_mode = "host";
    499 	status = "okay";
    500 };
    501 
    502 &usbotg {
    503 	vbus-supply = <&reg_otg_vbus>;
    504 	pinctrl-names = "default";
    505 	pinctrl-0 = <&pinctrl_usbotg>;
    506 	phy_type = "utmi";
    507 	dr_mode = "host";
    508 	disable-over-current;
    509 	status = "okay";
    510 };
    511 
    512 &usdhc1 {
    513 	pinctrl-names = "default";
    514 	pinctrl-0 = <&pinctrl_usdhc1>;
    515 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
    516 	no-1-8-v;
    517 	disable-wp;
    518 	cap-sd-highspeed;
    519 	no-mmc;
    520 	no-sdio;
    521 	status = "okay";
    522 };
    523 
    524 &usdhc2 {
    525 	pinctrl-names = "default";
    526 	pinctrl-0 = <&pinctrl_usdhc2>;
    527 	vmmc-supply = <&reg_wifi>;
    528 	non-removable;
    529 	cap-power-off-card;
    530 	keep-power-in-suspend;
    531 	no-1-8-v;
    532 	no-mmc;
    533 	no-sd;
    534 	status = "okay";
    535 
    536 	wifi {
    537 		compatible = "ti,wl1271";
    538 		interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
    539 		ref-clock-frequency = "38400000";
    540 		tcxo-clock-frequency = "19200000";
    541 	};
    542 };
    543 
    544 &usdhc3 {
    545 	pinctrl-names = "default";
    546 	pinctrl-0 = <&pinctrl_usdhc3>;
    547 	bus-width = <8>;
    548 	no-1-8-v;
    549 	non-removable;
    550 	no-sd;
    551 	no-sdio;
    552 	status = "okay";
    553 };
    554 
    555 &iomuxc {
    556 	pinctrl-names = "default";
    557 	pinctrl-0 = <&pinctrl_hog>;
    558 
    559 	pinctrl_audmux: audmuxgrp {
    560 		fsl,pins = <
    561 			/* SGTL5000 sys_mclk */
    562 			MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1			0x030b0
    563 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD			0x130b0
    564 			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC			0x130b0
    565 			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD			0x110b0
    566 			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS			0x130b0
    567 		>;
    568 	};
    569 
    570 	pinctrl_backlight: backlightgrp {
    571 		fsl,pins = <
    572 			MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28		0x1b0b0
    573 		>;
    574 	};
    575 
    576 	pinctrl_can1: can1grp {
    577 		fsl,pins = <
    578 			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX		0x1b000
    579 			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX		0x3008
    580 			/* CAN1_SR */
    581 			MX6QDL_PAD_KEY_COL3__GPIO4_IO12			0x13008
    582 			/* CAN1_TERM */
    583 			MX6QDL_PAD_GPIO_0__GPIO1_IO00			0x1b088
    584 		>;
    585 	};
    586 
    587 	pinctrl_can2: can2grp {
    588 		fsl,pins = <
    589 			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX		0x1b000
    590 			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX		0x3008
    591 			/* CAN2_SR */
    592 			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13			0x13008
    593 		>;
    594 	};
    595 
    596 	pinctrl_counter0: counter0grp {
    597 		fsl,pins = <
    598 			MX6QDL_PAD_NANDF_D0__GPIO2_IO00			0x1b000
    599 		>;
    600 	};
    601 
    602 	pinctrl_counter1: counter1grp {
    603 		fsl,pins = <
    604 			MX6QDL_PAD_NANDF_D1__GPIO2_IO01			0x1b000
    605 		>;
    606 	};
    607 
    608 	pinctrl_counter2: counter2grp {
    609 		fsl,pins = <
    610 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02			0x1b000
    611 		>;
    612 	};
    613 
    614 	pinctrl_ecspi1: ecspi1grp {
    615 		fsl,pins = <
    616 			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x100b1
    617 			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0x100b1
    618 			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0x100b1
    619 			/* CS */
    620 			MX6QDL_PAD_EIM_D19__GPIO3_IO19			0x000b1
    621 		>;
    622 	};
    623 
    624 	pinctrl_enet: enetgrp {
    625 		fsl,pins = <
    626 			MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b030
    627 			MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b030
    628 			MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b030
    629 			MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b030
    630 			MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b030
    631 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b030
    632 			MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x10030
    633 			MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x10030
    634 			MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x10030
    635 			MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x10030
    636 			MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x10030
    637 			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x10030
    638 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x10030
    639 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x10030
    640 			MX6QDL_PAD_ENET_MDC__ENET_MDC			0x10030
    641 			/* Phy reset */
    642 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25		0x1b0b0
    643 			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28		0x1b0b1
    644 		>;
    645 	};
    646 
    647 	pinctrl_hog: hoggrp {
    648 		fsl,pins = <
    649 			/* ITU656_nRESET */
    650 			MX6QDL_PAD_GPIO_2__GPIO1_IO02			0x1b0b0
    651 			/* CAM1_MIRROR */
    652 			MX6QDL_PAD_GPIO_3__GPIO1_IO03			0x130b0
    653 			/* CAM2_MIRROR */
    654 			MX6QDL_PAD_GPIO_4__GPIO1_IO04			0x130b0
    655 			/* CAM_nDETECT */
    656 			MX6QDL_PAD_GPIO_17__GPIO7_IO12			0x1b0b0
    657 			/* nON_SWITCH */
    658 			MX6QDL_PAD_EIM_CS0__GPIO2_IO23			0x1b0b0
    659 			/* ISB_IN1 */
    660 			MX6QDL_PAD_EIM_A16__GPIO2_IO22			0x130b0
    661 			/* ISB_nIN2 */
    662 			MX6QDL_PAD_EIM_A17__GPIO2_IO21			0x1b0b0
    663 			/* WARN_LIGHT */
    664 			MX6QDL_PAD_EIM_A19__GPIO2_IO19			0x100b0
    665 			/* ON2_FB */
    666 			MX6QDL_PAD_EIM_A25__GPIO5_IO02			0x100b0
    667 			/* YACO_nIRQ */
    668 			MX6QDL_PAD_EIM_D23__GPIO3_IO23			0x1b0b0
    669 			/* YACO_BOOT0 */
    670 			MX6QDL_PAD_EIM_D30__GPIO3_IO30			0x130b0
    671 			/* YACO_nRESET */
    672 			MX6QDL_PAD_EIM_D31__GPIO3_IO31			0x1b0b0
    673 			/* FORCE_ON1 */
    674 			MX6QDL_PAD_EIM_EB2__GPIO2_IO30			0x1b0b0
    675 			/* AUDIO_nRESET */
    676 			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21		0x1f0b0
    677 			/* ITU656_nPDN */
    678 			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20		0x1b0b0
    679 
    680 			/* HW revision detect */
    681 			/* REV_ID0 */
    682 			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08			0x1b0b0
    683 			/* REV_ID1 */
    684 			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09			0x1b0b0
    685 			/* REV_ID2 */
    686 			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10			0x1b0b0
    687 			/* REV_ID3 */
    688 			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11			0x1b0b0
    689 			/* REV_ID4 */
    690 			MX6QDL_PAD_SD4_DAT4__GPIO2_IO12			0x1b0b0
    691 
    692 			/* New in HW revision 1 */
    693 			/* ON1_FB */
    694 			MX6QDL_PAD_EIM_D20__GPIO3_IO20			0x100b0
    695 			/* DIP1_FB */
    696 			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18			0x1b0b0
    697 
    698 			/* New in UT2: FIXME: ISB PWM should start off, PD */
    699 			/* ISB_LED_PWM */
    700 			MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30		0x130b0
    701 		>;
    702 	};
    703 
    704 	pinctrl_i2c1: i2c1grp {
    705 		fsl,pins = <
    706 			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001f8b1
    707 			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001f8b1
    708 		>;
    709 	};
    710 
    711 	pinctrl_i2c3: i2c3grp {
    712 		fsl,pins = <
    713 			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
    714 			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
    715 		>;
    716 	};
    717 
    718 	pinctrl_ipu1_csi0: ipu1csi0grp {
    719 		fsl,pins = <
    720 			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
    721 			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
    722 			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
    723 			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
    724 			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
    725 			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
    726 			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
    727 			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
    728 			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
    729 		>;
    730 	};
    731 
    732 	pinctrl_leds: ledsgrp {
    733 		fsl,pins = <
    734 			/* DEBUG0 */
    735 			MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16		0x1b0b0
    736 			/* DEBUG1 */
    737 			MX6QDL_PAD_DI0_PIN15__GPIO4_IO17		0x1b0b0
    738 			/* POWER_LED */
    739 			MX6QDL_PAD_EIM_CS1__GPIO2_IO24			0x1b0b0
    740 		>;
    741 	};
    742 
    743 	pinctrl_pwm1: pwm1grp {
    744 		fsl,pins = <
    745 			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT			0x1b0b0
    746 		>;
    747 	};
    748 
    749 	/* YaCO AUX Uart */
    750 	pinctrl_uart1: uart1grp {
    751 		fsl,pins = <
    752 			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA		0x1b0b1
    753 			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA		0x1b0b1
    754 		>;
    755 	};
    756 
    757 	pinctrl_uart2: uart2grp {
    758 		fsl,pins = <
    759 			MX6QDL_PAD_EIM_D26__UART2_RX_DATA		0x1b0b1
    760 			MX6QDL_PAD_EIM_D27__UART2_TX_DATA		0x1b0b1
    761 			MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B		0x1b0b1
    762 			MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B		0x1b0b1
    763 		>;
    764 	};
    765 
    766 	/* YaCO Touchscreen UART */
    767 	pinctrl_uart3: uart3grp {
    768 		fsl,pins = <
    769 			MX6QDL_PAD_EIM_D24__UART3_TX_DATA		0x1b0b1
    770 			MX6QDL_PAD_EIM_D25__UART3_RX_DATA		0x1b0b1
    771 		>;
    772 	};
    773 
    774 	pinctrl_uart4: uart4grp {
    775 		fsl,pins = <
    776 			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA		0x1b0b1
    777 			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA		0x1b0b1
    778 		>;
    779 	};
    780 
    781 	pinctrl_uart5: uart5grp {
    782 		fsl,pins = <
    783 			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA		0x1b0b1
    784 			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA		0x1b0b1
    785 		>;
    786 	};
    787 
    788 	pinctrl_usbotg: usbotggrp {
    789 		fsl,pins = <
    790 			MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x1b0b0
    791 			/* power enable, high active */
    792 			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
    793 		>;
    794 	};
    795 
    796 	pinctrl_usdhc1: usdhc1grp {
    797 		fsl,pins = <
    798 			MX6QDL_PAD_SD1_CMD__SD1_CMD			0x170f9
    799 			MX6QDL_PAD_SD1_CLK__SD1_CLK			0x100f9
    800 			MX6QDL_PAD_SD1_DAT0__SD1_DATA0			0x170f9
    801 			MX6QDL_PAD_SD1_DAT1__SD1_DATA1			0x170f9
    802 			MX6QDL_PAD_SD1_DAT2__SD1_DATA2			0x170f9
    803 			MX6QDL_PAD_SD1_DAT3__SD1_DATA3			0x170f9
    804 			MX6QDL_PAD_GPIO_1__GPIO1_IO01			0x1b0b0
    805 		>;
    806 	};
    807 
    808 	pinctrl_usdhc2: usdhc2grp {
    809 		fsl,pins = <
    810 			MX6QDL_PAD_SD2_CMD__SD2_CMD			0x170b9
    811 			MX6QDL_PAD_SD2_CLK__SD2_CLK			0x100b9
    812 			MX6QDL_PAD_SD2_DAT0__SD2_DATA0			0x170b9
    813 			MX6QDL_PAD_SD2_DAT1__SD2_DATA1			0x170b9
    814 			MX6QDL_PAD_SD2_DAT2__SD2_DATA2			0x170b9
    815 			MX6QDL_PAD_SD2_DAT3__SD2_DATA3			0x170b9
    816 			/* WL12xx IRQ */
    817 			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30		0x10880
    818 		>;
    819 	};
    820 
    821 	pinctrl_usdhc3: usdhc3grp {
    822 		fsl,pins = <
    823 			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17099
    824 			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10099
    825 			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17099
    826 			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17099
    827 			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17099
    828 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17099
    829 			MX6QDL_PAD_SD3_DAT4__SD3_DATA4			0x17099
    830 			MX6QDL_PAD_SD3_DAT5__SD3_DATA5			0x17099
    831 			MX6QDL_PAD_SD3_DAT6__SD3_DATA6			0x17099
    832 			MX6QDL_PAD_SD3_DAT7__SD3_DATA7			0x17099
    833 			MX6QDL_PAD_SD3_RST__SD3_RESET			0x1b0b1
    834 		>;
    835 	};
    836 
    837 	pinctrl_wifi_npd: wifinpdgrp {
    838 		fsl,pins = <
    839 			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26		0x1b8b0
    840 		>;
    841 	};
    842 };
    843