1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP. 5 * 6 */ 7 8 #include <dt-bindings/clock/imx6sll-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include "imx6sll-pinfunc.h" 12 13 / { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 aliases { 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 gpio3 = &gpio4; 22 gpio4 = &gpio5; 23 gpio5 = &gpio6; 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 mmc0 = &usdhc1; 28 mmc1 = &usdhc2; 29 mmc2 = &usdhc3; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 spi0 = &ecspi1; 36 spi1 = &ecspi2; 37 spi3 = &ecspi3; 38 spi4 = &ecspi4; 39 usb0 = &usbotg1; 40 usb1 = &usbotg2; 41 usbphy0 = &usbphy1; 42 usbphy1 = &usbphy2; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a9"; 51 device_type = "cpu"; 52 reg = <0>; 53 next-level-cache = <&L2>; 54 operating-points = < 55 /* kHz uV */ 56 996000 1275000 57 792000 1175000 58 396000 1075000 59 198000 975000 60 >; 61 fsl,soc-operating-points = < 62 /* ARM kHz SOC-PU uV */ 63 996000 1175000 64 792000 1175000 65 396000 1175000 66 198000 1175000 67 >; 68 clock-latency = <61036>; /* two CLK32 periods */ 69 #cooling-cells = <2>; 70 clocks = <&clks IMX6SLL_CLK_ARM>, 71 <&clks IMX6SLL_CLK_PLL2_PFD2>, 72 <&clks IMX6SLL_CLK_STEP>, 73 <&clks IMX6SLL_CLK_PLL1_SW>, 74 <&clks IMX6SLL_CLK_PLL1_SYS>; 75 clock-names = "arm", "pll2_pfd2_396m", "step", 76 "pll1_sw", "pll1_sys"; 77 nvmem-cells = <&cpu_speed_grade>; 78 nvmem-cell-names = "speed_grade"; 79 }; 80 }; 81 82 ckil: clock-ckil { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32768>; 86 clock-output-names = "ckil"; 87 }; 88 89 osc: clock-osc-24m { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 clock-output-names = "osc"; 94 }; 95 96 ipp_di0: clock-ipp-di0 { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 clock-output-names = "ipp_di0"; 101 }; 102 103 ipp_di1: clock-ipp-di1 { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <0>; 107 clock-output-names = "ipp_di1"; 108 }; 109 110 soc { 111 #address-cells = <1>; 112 #size-cells = <1>; 113 compatible = "simple-bus"; 114 interrupt-parent = <&gpc>; 115 ranges; 116 117 ocram: sram@900000 { 118 compatible = "mmio-sram"; 119 reg = <0x00900000 0x20000>; 120 }; 121 122 intc: interrupt-controller@a01000 { 123 compatible = "arm,cortex-a9-gic"; 124 #interrupt-cells = <3>; 125 interrupt-controller; 126 reg = <0x00a01000 0x1000>, 127 <0x00a00100 0x100>; 128 interrupt-parent = <&intc>; 129 }; 130 131 L2: cache-controller@a02000 { 132 compatible = "arm,pl310-cache"; 133 reg = <0x00a02000 0x1000>; 134 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 135 cache-unified; 136 cache-level = <2>; 137 arm,tag-latency = <4 2 3>; 138 arm,data-latency = <4 2 3>; 139 }; 140 141 aips1: bus@2000000 { 142 compatible = "fsl,aips-bus", "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 reg = <0x02000000 0x100000>; 146 ranges; 147 148 spba: spba-bus@2000000 { 149 compatible = "fsl,spba-bus", "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 reg = <0x02000000 0x40000>; 153 ranges; 154 155 spdif: spdif@2004000 { 156 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; 157 reg = <0x02004000 0x4000>; 158 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 159 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; 160 dma-names = "rx", "tx"; 161 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, 162 <&clks IMX6SLL_CLK_OSC>, 163 <&clks IMX6SLL_CLK_SPDIF>, 164 <&clks IMX6SLL_CLK_DUMMY>, 165 <&clks IMX6SLL_CLK_DUMMY>, 166 <&clks IMX6SLL_CLK_DUMMY>, 167 <&clks IMX6SLL_CLK_IPG>, 168 <&clks IMX6SLL_CLK_DUMMY>, 169 <&clks IMX6SLL_CLK_DUMMY>, 170 <&clks IMX6SLL_CLK_SPBA>; 171 clock-names = "core", "rxtx0", 172 "rxtx1", "rxtx2", 173 "rxtx3", "rxtx4", 174 "rxtx5", "rxtx6", 175 "rxtx7", "dma"; 176 status = "disabled"; 177 }; 178 179 ecspi1: spi@2008000 { 180 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 181 reg = <0x02008000 0x4000>; 182 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 183 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 184 dma-names = "rx", "tx"; 185 clocks = <&clks IMX6SLL_CLK_ECSPI1>, 186 <&clks IMX6SLL_CLK_ECSPI1>; 187 clock-names = "ipg", "per"; 188 status = "disabled"; 189 }; 190 191 ecspi2: spi@200c000 { 192 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 193 reg = <0x0200c000 0x4000>; 194 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 195 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 196 dma-names = "rx", "tx"; 197 clocks = <&clks IMX6SLL_CLK_ECSPI2>, 198 <&clks IMX6SLL_CLK_ECSPI2>; 199 clock-names = "ipg", "per"; 200 status = "disabled"; 201 }; 202 203 ecspi3: spi@2010000 { 204 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 205 reg = <0x02010000 0x4000>; 206 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 208 dma-names = "rx", "tx"; 209 clocks = <&clks IMX6SLL_CLK_ECSPI3>, 210 <&clks IMX6SLL_CLK_ECSPI3>; 211 clock-names = "ipg", "per"; 212 status = "disabled"; 213 }; 214 215 ecspi4: spi@2014000 { 216 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 217 reg = <0x02014000 0x4000>; 218 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 219 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 220 dma-names = "rx", "tx"; 221 clocks = <&clks IMX6SLL_CLK_ECSPI4>, 222 <&clks IMX6SLL_CLK_ECSPI4>; 223 clock-names = "ipg", "per"; 224 status = "disabled"; 225 }; 226 227 uart4: serial@2018000 { 228 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 229 "fsl,imx21-uart"; 230 reg = <0x02018000 0x4000>; 231 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 232 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 233 dma-names = "rx", "tx"; 234 clocks = <&clks IMX6SLL_CLK_UART4_IPG>, 235 <&clks IMX6SLL_CLK_UART4_SERIAL>; 236 clock-names = "ipg", "per"; 237 status = "disabled"; 238 }; 239 240 uart1: serial@2020000 { 241 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 242 "fsl,imx21-uart"; 243 reg = <0x02020000 0x4000>; 244 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 245 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 246 dma-names = "rx", "tx"; 247 clocks = <&clks IMX6SLL_CLK_UART1_IPG>, 248 <&clks IMX6SLL_CLK_UART1_SERIAL>; 249 clock-names = "ipg", "per"; 250 status = "disabled"; 251 }; 252 253 uart2: serial@2024000 { 254 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 255 "fsl,imx21-uart"; 256 reg = <0x02024000 0x4000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 259 dma-names = "rx", "tx"; 260 clocks = <&clks IMX6SLL_CLK_UART2_IPG>, 261 <&clks IMX6SLL_CLK_UART2_SERIAL>; 262 clock-names = "ipg", "per"; 263 status = "disabled"; 264 }; 265 266 ssi1: ssi@2028000 { 267 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 268 reg = <0x02028000 0x4000>; 269 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 270 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; 271 dma-names = "rx", "tx"; 272 fsl,fifo-depth = <15>; 273 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, 274 <&clks IMX6SLL_CLK_SSI1>; 275 clock-names = "ipg", "baud"; 276 status = "disabled"; 277 }; 278 279 ssi2: ssi@202c000 { 280 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 281 reg = <0x0202c000 0x4000>; 282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 283 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; 284 dma-names = "rx", "tx"; 285 fsl,fifo-depth = <15>; 286 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, 287 <&clks IMX6SLL_CLK_SSI2>; 288 clock-names = "ipg", "baud"; 289 status = "disabled"; 290 }; 291 292 ssi3: ssi@2030000 { 293 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; 294 reg = <0x02030000 0x4000>; 295 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 296 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; 297 dma-names = "rx", "tx"; 298 fsl,fifo-depth = <15>; 299 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, 300 <&clks IMX6SLL_CLK_SSI3>; 301 clock-names = "ipg", "baud"; 302 status = "disabled"; 303 }; 304 305 uart3: serial@2034000 { 306 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", 307 "fsl,imx21-uart"; 308 reg = <0x02034000 0x4000>; 309 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 310 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 311 dma-name = "rx", "tx"; 312 clocks = <&clks IMX6SLL_CLK_UART3_IPG>, 313 <&clks IMX6SLL_CLK_UART3_SERIAL>; 314 clock-names = "ipg", "per"; 315 status = "disabled"; 316 }; 317 }; 318 319 pwm1: pwm@2080000 { 320 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 321 reg = <0x02080000 0x4000>; 322 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clks IMX6SLL_CLK_PWM1>, 324 <&clks IMX6SLL_CLK_PWM1>; 325 clock-names = "ipg", "per"; 326 #pwm-cells = <3>; 327 }; 328 329 pwm2: pwm@2084000 { 330 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 331 reg = <0x02084000 0x4000>; 332 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clks IMX6SLL_CLK_PWM2>, 334 <&clks IMX6SLL_CLK_PWM2>; 335 clock-names = "ipg", "per"; 336 #pwm-cells = <3>; 337 }; 338 339 pwm3: pwm@2088000 { 340 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 341 reg = <0x02088000 0x4000>; 342 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clks IMX6SLL_CLK_PWM3>, 344 <&clks IMX6SLL_CLK_PWM3>; 345 clock-names = "ipg", "per"; 346 #pwm-cells = <3>; 347 }; 348 349 pwm4: pwm@208c000 { 350 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; 351 reg = <0x0208c000 0x4000>; 352 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clks IMX6SLL_CLK_PWM4>, 354 <&clks IMX6SLL_CLK_PWM4>; 355 clock-names = "ipg", "per"; 356 #pwm-cells = <3>; 357 }; 358 359 gpt1: timer@2098000 { 360 compatible = "fsl,imx6sl-gpt"; 361 reg = <0x02098000 0x4000>; 362 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clks IMX6SLL_CLK_GPT_BUS>, 364 <&clks IMX6SLL_CLK_GPT_SERIAL>; 365 clock-names = "ipg", "per"; 366 }; 367 368 gpio1: gpio@209c000 { 369 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 370 reg = <0x0209c000 0x4000>; 371 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clks IMX6SLL_CLK_GPIO1>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>; 379 }; 380 381 gpio2: gpio@20a0000 { 382 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 383 reg = <0x020a0000 0x4000>; 384 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clks IMX6SLL_CLK_GPIO2>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 gpio-ranges = <&iomuxc 0 50 32>; 392 }; 393 394 gpio3: gpio@20a4000 { 395 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 396 reg = <0x020a4000 0x4000>; 397 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clks IMX6SLL_CLK_GPIO3>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>, 405 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>, 406 <&iomuxc 21 6 11>; 407 }; 408 409 gpio4: gpio@20a8000 { 410 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 411 reg = <0x020a8000 0x4000>; 412 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clks IMX6SLL_CLK_GPIO4>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>, 420 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>, 421 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>, 422 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>, 423 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>, 424 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>, 425 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>, 426 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>, 427 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>; 428 }; 429 430 gpio5: gpio@20ac000 { 431 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 432 reg = <0x020ac000 0x4000>; 433 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clks IMX6SLL_CLK_GPIO5>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>, 441 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>, 442 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>, 443 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>, 444 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>, 445 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>, 446 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>, 447 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>, 448 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>, 449 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>, 450 <&iomuxc 21 137 1>; 451 }; 452 453 gpio6: gpio@20b0000 { 454 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; 455 reg = <0x020b0000 0x4000>; 456 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clks IMX6SLL_CLK_GPIO6>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 }; 464 465 kpp: keypad@20b8000 { 466 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; 467 reg = <0x020b8000 0x4000>; 468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks IMX6SLL_CLK_KPP>; 470 status = "disabled"; 471 }; 472 473 wdog1: watchdog@20bc000 { 474 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 475 reg = <0x020bc000 0x4000>; 476 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clks IMX6SLL_CLK_WDOG1>; 478 }; 479 480 wdog2: watchdog@20c0000 { 481 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; 482 reg = <0x020c0000 0x4000>; 483 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clks IMX6SLL_CLK_WDOG2>; 485 status = "disabled"; 486 }; 487 488 clks: clock-controller@20c4000 { 489 compatible = "fsl,imx6sll-ccm"; 490 reg = <0x020c4000 0x4000>; 491 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 493 #clock-cells = <1>; 494 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 495 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 496 497 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; 498 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; 499 }; 500 501 anatop: anatop@20c8000 { 502 compatible = "fsl,imx6sll-anatop", 503 "fsl,imx6q-anatop", 504 "syscon", "simple-mfd"; 505 reg = <0x020c8000 0x4000>; 506 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 reg_3p0: regulator-3p0@20c8120 { 513 compatible = "fsl,anatop-regulator"; 514 reg = <0x20c8120>; 515 regulator-name = "vdd3p0"; 516 regulator-min-microvolt = <2625000>; 517 regulator-max-microvolt = <3400000>; 518 anatop-reg-offset = <0x120>; 519 anatop-vol-bit-shift = <8>; 520 anatop-vol-bit-width = <5>; 521 anatop-min-bit-val = <0>; 522 anatop-min-voltage = <2625000>; 523 anatop-max-voltage = <3400000>; 524 anatop-enable-bit = <0>; 525 }; 526 527 tempmon: temperature-sensor { 528 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; 529 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-parent = <&gpc>; 531 fsl,tempmon = <&anatop>; 532 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 533 nvmem-cell-names = "calib", "temp_grade"; 534 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; 535 }; 536 }; 537 538 usbphy1: usb-phy@20c9000 { 539 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 540 "fsl,imx23-usbphy"; 541 reg = <0x020c9000 0x1000>; 542 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clks IMX6SLL_CLK_USBPHY1>; 544 phy-3p0-supply = <®_3p0>; 545 fsl,anatop = <&anatop>; 546 }; 547 548 usbphy2: usb-phy@20ca000 { 549 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", 550 "fsl,imx23-usbphy"; 551 reg = <0x020ca000 0x1000>; 552 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clks IMX6SLL_CLK_USBPHY2>; 554 phy-reg_3p0-supply = <®_3p0>; 555 fsl,anatop = <&anatop>; 556 }; 557 558 snvs: snvs@20cc000 { 559 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 560 reg = <0x020cc000 0x4000>; 561 562 snvs_rtc: snvs-rtc-lp { 563 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 564 regmap = <&snvs>; 565 offset = <0x34>; 566 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 570 snvs_poweroff: snvs-poweroff { 571 compatible = "syscon-poweroff"; 572 regmap = <&snvs>; 573 offset = <0x38>; 574 mask = <0x61>; 575 status = "disabled"; 576 }; 577 578 snvs_pwrkey: snvs-powerkey { 579 compatible = "fsl,sec-v4.0-pwrkey"; 580 regmap = <&snvs>; 581 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 582 linux,keycode = <KEY_POWER>; 583 wakeup-source; 584 status = "disabled"; 585 }; 586 }; 587 588 src: reset-controller@20d8000 { 589 compatible = "fsl,imx6sll-src", "fsl,imx51-src"; 590 reg = <0x020d8000 0x4000>; 591 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 593 #reset-cells = <1>; 594 }; 595 596 gpc: interrupt-controller@20dc000 { 597 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; 598 reg = <0x020dc000 0x4000>; 599 interrupt-controller; 600 #interrupt-cells = <3>; 601 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-parent = <&intc>; 603 }; 604 605 iomuxc: pinctrl@20e0000 { 606 compatible = "fsl,imx6sll-iomuxc"; 607 reg = <0x020e0000 0x4000>; 608 }; 609 610 gpr: iomuxc-gpr@20e4000 { 611 compatible = "fsl,imx6sll-iomuxc-gpr", 612 "fsl,imx6q-iomuxc-gpr", "syscon"; 613 reg = <0x020e4000 0x4000>; 614 }; 615 616 csi: csi@20e8000 { 617 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; 618 reg = <0x020e8000 0x4000>; 619 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clks IMX6SLL_CLK_DUMMY>, 621 <&clks IMX6SLL_CLK_CSI>, 622 <&clks IMX6SLL_CLK_DUMMY>; 623 clock-names = "disp-axi", "csi_mclk", "disp_dcic"; 624 status = "disabled"; 625 }; 626 627 sdma: dma-controller@20ec000 { 628 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma"; 629 reg = <0x020ec000 0x4000>; 630 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clks IMX6SLL_CLK_IPG>, 632 <&clks IMX6SLL_CLK_SDMA>; 633 clock-names = "ipg", "ahb"; 634 #dma-cells = <3>; 635 iram = <&ocram>; 636 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 637 }; 638 639 pxp: pxp@20f0000 { 640 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp"; 641 reg = <0x20f0000 0x4000>; 642 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clks IMX6SLL_CLK_PXP>; 645 clock-names = "axi"; 646 }; 647 648 lcdif: lcd-controller@20f8000 { 649 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; 650 reg = <0x020f8000 0x4000>; 651 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, 653 <&clks IMX6SLL_CLK_LCDIF_APB>, 654 <&clks IMX6SLL_CLK_DUMMY>; 655 clock-names = "pix", "axi", "disp_axi"; 656 status = "disabled"; 657 }; 658 659 dcp: crypto@20fc000 { 660 compatible = "fsl,imx28-dcp"; 661 reg = <0x020fc000 0x4000>; 662 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&clks IMX6SLL_CLK_DCP>; 666 clock-names = "dcp"; 667 }; 668 }; 669 670 aips2: bus@2100000 { 671 compatible = "fsl,aips-bus", "simple-bus"; 672 #address-cells = <1>; 673 #size-cells = <1>; 674 reg = <0x02100000 0x100000>; 675 ranges; 676 677 usbotg1: usb@2184000 { 678 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 679 "fsl,imx27-usb"; 680 reg = <0x02184000 0x200>; 681 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&clks IMX6SLL_CLK_USBOH3>; 683 fsl,usbphy = <&usbphy1>; 684 fsl,usbmisc = <&usbmisc 0>; 685 fsl,anatop = <&anatop>; 686 ahb-burst-config = <0x0>; 687 tx-burst-size-dword = <0x10>; 688 rx-burst-size-dword = <0x10>; 689 status = "disabled"; 690 }; 691 692 usbotg2: usb@2184200 { 693 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", 694 "fsl,imx27-usb"; 695 reg = <0x02184200 0x200>; 696 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clks IMX6SLL_CLK_USBOH3>; 698 fsl,usbphy = <&usbphy2>; 699 fsl,usbmisc = <&usbmisc 1>; 700 ahb-burst-config = <0x0>; 701 tx-burst-size-dword = <0x10>; 702 rx-burst-size-dword = <0x10>; 703 status = "disabled"; 704 }; 705 706 usbmisc: usbmisc@2184800 { 707 #index-cells = <1>; 708 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", 709 "fsl,imx6q-usbmisc"; 710 reg = <0x02184800 0x200>; 711 }; 712 713 usdhc1: mmc@2190000 { 714 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 715 reg = <0x02190000 0x4000>; 716 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clks IMX6SLL_CLK_USDHC1>, 718 <&clks IMX6SLL_CLK_USDHC1>, 719 <&clks IMX6SLL_CLK_USDHC1>; 720 clock-names = "ipg", "ahb", "per"; 721 bus-width = <4>; 722 fsl,tuning-step = <2>; 723 fsl,tuning-start-tap = <20>; 724 status = "disabled"; 725 }; 726 727 usdhc2: mmc@2194000 { 728 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 729 reg = <0x02194000 0x4000>; 730 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&clks IMX6SLL_CLK_USDHC2>, 732 <&clks IMX6SLL_CLK_USDHC2>, 733 <&clks IMX6SLL_CLK_USDHC2>; 734 clock-names = "ipg", "ahb", "per"; 735 bus-width = <4>; 736 fsl,tuning-step = <2>; 737 fsl,tuning-start-tap = <20>; 738 status = "disabled"; 739 }; 740 741 usdhc3: mmc@2198000 { 742 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; 743 reg = <0x02198000 0x4000>; 744 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&clks IMX6SLL_CLK_USDHC3>, 746 <&clks IMX6SLL_CLK_USDHC3>, 747 <&clks IMX6SLL_CLK_USDHC3>; 748 clock-names = "ipg", "ahb", "per"; 749 bus-width = <4>; 750 fsl,tuning-step = <2>; 751 fsl,tuning-start-tap = <20>; 752 status = "disabled"; 753 }; 754 755 i2c1: i2c@21a0000 { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 759 reg = <0x021a0000 0x4000>; 760 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clks IMX6SLL_CLK_I2C1>; 762 status = "disabled"; 763 }; 764 765 i2c2: i2c@21a4000 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 769 reg = <0x021a4000 0x4000>; 770 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&clks IMX6SLL_CLK_I2C2>; 772 status = "disabled"; 773 }; 774 775 i2c3: i2c@21a8000 { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; 779 reg = <0x021a8000 0x4000>; 780 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX6SLL_CLK_I2C3>; 782 status = "disabled"; 783 }; 784 785 mmdc: memory-controller@21b0000 { 786 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; 787 reg = <0x021b0000 0x4000>; 788 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; 789 }; 790 791 rngb: rng@21b4000 { 792 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; 793 reg = <0x021b4000 0x4000>; 794 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clks IMX6SLL_CLK_DUMMY>; 796 }; 797 798 ocotp: efuse@21bc000 { 799 #address-cells = <1>; 800 #size-cells = <1>; 801 compatible = "fsl,imx6sll-ocotp", "syscon"; 802 reg = <0x021bc000 0x4000>; 803 clocks = <&clks IMX6SLL_CLK_OCOTP>; 804 805 cpu_speed_grade: speed-grade@10 { 806 reg = <0x10 4>; 807 }; 808 809 tempmon_calib: calib@38 { 810 reg = <0x38 4>; 811 }; 812 813 tempmon_temp_grade: temp-grade@20 { 814 reg = <0x20 4>; 815 }; 816 }; 817 818 audmux: audmux@21d8000 { 819 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; 820 reg = <0x021d8000 0x4000>; 821 status = "disabled"; 822 }; 823 824 uart5: serial@21f4000 { 825 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", 826 "fsl,imx21-uart"; 827 reg = <0x021f4000 0x4000>; 828 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 829 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 830 dma-names = "rx", "tx"; 831 clocks = <&clks IMX6SLL_CLK_UART5_IPG>, 832 <&clks IMX6SLL_CLK_UART5_SERIAL>; 833 clock-names = "ipg", "per"; 834 status = "disabled"; 835 }; 836 }; 837 }; 838 }; 839
Indexes created Wed Oct 01 19:09:53 GMT 2025