1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5 / { 6 chosen { 7 stdout-path = &uart1; 8 }; 9 10 memory@80000000 { 11 device_type = "memory"; 12 reg = <0x80000000 0x20000000>; 13 }; 14 15 backlight_display: backlight-display { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000>; 18 brightness-levels = <0 4 8 16 32 64 128 255>; 19 default-brightness-level = <6>; 20 status = "okay"; 21 }; 22 23 24 reg_sd1_vmmc: regulator-sd1-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "VSD_3V3"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 reg_peri_3v3: regulator-peri-3v3 { 34 compatible = "regulator-fixed"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_peri_3v3>; 37 regulator-name = "VPERI_3V3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 41 /* 42 * If you want to want to make this dynamic please 43 * check schematics and test all affected peripherals: 44 * 45 * - sensors 46 * - ethernet phy 47 * - can 48 * - bluetooth 49 * - wm8960 audio codec 50 * - ov5640 camera 51 */ 52 regulator-always-on; 53 }; 54 55 reg_can_3v3: regulator-can-3v3 { 56 compatible = "regulator-fixed"; 57 regulator-name = "can-3v3"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 61 }; 62 63 sound-wm8960 { 64 compatible = "fsl,imx-audio-wm8960"; 65 model = "wm8960-audio"; 66 audio-cpu = <&sai2>; 67 audio-codec = <&codec>; 68 audio-asrc = <&asrc>; 69 hp-det-gpio = <&gpio5 4 0>; 70 audio-routing = 71 "Headphone Jack", "HP_L", 72 "Headphone Jack", "HP_R", 73 "Ext Spk", "SPK_LP", 74 "Ext Spk", "SPK_LN", 75 "Ext Spk", "SPK_RP", 76 "Ext Spk", "SPK_RN", 77 "LINPUT2", "Mic Jack", 78 "LINPUT3", "Mic Jack", 79 "RINPUT1", "AMIC", 80 "RINPUT2", "AMIC", 81 "Mic Jack", "MICB", 82 "AMIC", "MICB"; 83 }; 84 85 spi4 { 86 compatible = "spi-gpio"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_spi4>; 89 status = "okay"; 90 gpio-sck = <&gpio5 11 0>; 91 gpio-mosi = <&gpio5 10 0>; 92 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; 93 num-chipselects = <1>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 gpio_spi: gpio@0 { 98 compatible = "fairchild,74hc595"; 99 gpio-controller; 100 #gpio-cells = <2>; 101 reg = <0>; 102 registers-number = <1>; 103 spi-max-frequency = <100000>; 104 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 105 }; 106 }; 107 108 panel { 109 compatible = "innolux,at043tn24"; 110 backlight = <&backlight_display>; 111 112 port { 113 panel_in: endpoint { 114 remote-endpoint = <&display_out>; 115 }; 116 }; 117 }; 118 }; 119 120 &clks { 121 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 122 assigned-clock-rates = <786432000>; 123 }; 124 125 &i2c2 { 126 clock-frequency = <100000>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_i2c2>; 129 status = "okay"; 130 131 codec: wm8960@1a { 132 #sound-dai-cells = <0>; 133 compatible = "wlf,wm8960"; 134 reg = <0x1a>; 135 wlf,shared-lrclk; 136 wlf,hp-cfg = <3 2 3>; 137 wlf,gpio-cfg = <1 3>; 138 clocks = <&clks IMX6UL_CLK_SAI2>; 139 clock-names = "mclk"; 140 }; 141 142 camera@3c { 143 compatible = "ovti,ov5640"; 144 reg = <0x3c>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_camera_clock>; 147 clocks = <&clks IMX6UL_CLK_CSI>; 148 clock-names = "xclk"; 149 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; 150 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; 151 152 port { 153 ov5640_to_parallel: endpoint { 154 remote-endpoint = <¶llel_from_ov5640>; 155 bus-width = <8>; 156 data-shift = <2>; /* lines 9:2 are used */ 157 hsync-active = <0>; 158 vsync-active = <0>; 159 pclk-sample = <1>; 160 }; 161 }; 162 }; 163 }; 164 165 &csi { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_csi1>; 168 status = "okay"; 169 170 port { 171 parallel_from_ov5640: endpoint { 172 remote-endpoint = <&ov5640_to_parallel>; 173 bus-type = <5>; /* Parallel bus */ 174 }; 175 }; 176 }; 177 178 &fec1 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_enet1>; 181 phy-mode = "rmii"; 182 phy-handle = <ðphy0>; 183 phy-supply = <®_peri_3v3>; 184 status = "okay"; 185 }; 186 187 &fec2 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_enet2>; 190 phy-mode = "rmii"; 191 phy-handle = <ðphy1>; 192 phy-supply = <®_peri_3v3>; 193 status = "okay"; 194 195 mdio { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 ethphy0: ethernet-phy@2 { 200 compatible = "ethernet-phy-id0022.1560"; 201 reg = <2>; 202 micrel,led-mode = <1>; 203 clocks = <&clks IMX6UL_CLK_ENET_REF>; 204 clock-names = "rmii-ref"; 205 206 }; 207 208 ethphy1: ethernet-phy@1 { 209 compatible = "ethernet-phy-id0022.1560"; 210 reg = <1>; 211 micrel,led-mode = <1>; 212 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 213 clock-names = "rmii-ref"; 214 }; 215 }; 216 }; 217 218 &can1 { 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_flexcan1>; 221 xceiver-supply = <®_can_3v3>; 222 status = "okay"; 223 }; 224 225 &can2 { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_flexcan2>; 228 xceiver-supply = <®_can_3v3>; 229 status = "okay"; 230 }; 231 232 &gpio_spi { 233 eth0-phy-hog { 234 gpio-hog; 235 gpios = <1 GPIO_ACTIVE_HIGH>; 236 output-high; 237 line-name = "eth0-phy"; 238 }; 239 240 eth1-phy-hog { 241 gpio-hog; 242 gpios = <2 GPIO_ACTIVE_HIGH>; 243 output-high; 244 line-name = "eth1-phy"; 245 }; 246 }; 247 248 &i2c1 { 249 clock-frequency = <100000>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_i2c1>; 252 status = "okay"; 253 254 magnetometer@e { 255 compatible = "fsl,mag3110"; 256 reg = <0x0e>; 257 vdd-supply = <®_peri_3v3>; 258 vddio-supply = <®_peri_3v3>; 259 }; 260 }; 261 262 &lcdif { 263 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 264 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_lcdif_dat 267 &pinctrl_lcdif_ctrl>; 268 status = "okay"; 269 270 port { 271 display_out: endpoint { 272 remote-endpoint = <&panel_in>; 273 }; 274 }; 275 }; 276 277 &pwm1 { 278 #pwm-cells = <2>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_pwm1>; 281 status = "okay"; 282 }; 283 284 &qspi { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_qspi>; 287 status = "okay"; 288 289 flash0: n25q256a@0 { 290 #address-cells = <1>; 291 #size-cells = <1>; 292 compatible = "micron,n25q256a", "jedec,spi-nor"; 293 spi-max-frequency = <29000000>; 294 spi-rx-bus-width = <4>; 295 spi-tx-bus-width = <1>; 296 reg = <0>; 297 }; 298 }; 299 300 &sai2 { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_sai2>; 303 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 304 <&clks IMX6UL_CLK_SAI2>; 305 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 306 assigned-clock-rates = <0>, <12288000>; 307 fsl,sai-mclk-direction-output; 308 status = "okay"; 309 }; 310 311 &snvs_poweroff { 312 status = "okay"; 313 }; 314 315 &snvs_pwrkey { 316 status = "okay"; 317 }; 318 319 &tsc { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_tsc>; 322 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 323 measure-delay-time = <0xffff>; 324 pre-charge-time = <0xfff>; 325 status = "okay"; 326 }; 327 328 &uart1 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart1>; 331 status = "okay"; 332 }; 333 334 &uart2 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart2>; 337 uart-has-rtscts; 338 status = "okay"; 339 }; 340 341 &usbotg1 { 342 dr_mode = "otg"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_usb_otg1>; 345 status = "okay"; 346 }; 347 348 &usbotg2 { 349 dr_mode = "host"; 350 disable-over-current; 351 status = "okay"; 352 }; 353 354 &usbphy1 { 355 fsl,tx-d-cal = <106>; 356 }; 357 358 &usbphy2 { 359 fsl,tx-d-cal = <106>; 360 }; 361 362 &usdhc1 { 363 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 364 pinctrl-0 = <&pinctrl_usdhc1>; 365 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 366 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 367 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 368 keep-power-in-suspend; 369 wakeup-source; 370 vmmc-supply = <®_sd1_vmmc>; 371 status = "okay"; 372 }; 373 374 &usdhc2 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_usdhc2>; 377 no-1-8-v; 378 broken-cd; 379 keep-power-in-suspend; 380 wakeup-source; 381 status = "okay"; 382 }; 383 384 &wdog1 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_wdog>; 387 fsl,ext-reset-output; 388 }; 389 390 &iomuxc { 391 pinctrl-names = "default"; 392 393 pinctrl_camera_clock: cameraclockgrp { 394 fsl,pins = < 395 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 396 >; 397 }; 398 399 pinctrl_csi1: csi1grp { 400 fsl,pins = < 401 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 402 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 403 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 404 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 405 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 406 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 407 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 408 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 409 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 410 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 411 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 412 >; 413 }; 414 415 pinctrl_enet1: enet1grp { 416 fsl,pins = < 417 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 418 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 419 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 420 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 421 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 422 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 423 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 424 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 425 >; 426 }; 427 428 pinctrl_enet2: enet2grp { 429 fsl,pins = < 430 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 431 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 432 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 433 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 434 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 435 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 436 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 437 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 438 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 439 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 440 >; 441 }; 442 443 pinctrl_flexcan1: flexcan1grp{ 444 fsl,pins = < 445 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 446 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 447 >; 448 }; 449 450 pinctrl_flexcan2: flexcan2grp{ 451 fsl,pins = < 452 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 453 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 454 >; 455 }; 456 457 pinctrl_i2c1: i2c1grp { 458 fsl,pins = < 459 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 460 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 461 >; 462 }; 463 464 pinctrl_i2c2: i2c2grp { 465 fsl,pins = < 466 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 467 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 468 >; 469 }; 470 471 pinctrl_lcdif_dat: lcdifdatgrp { 472 fsl,pins = < 473 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 474 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 475 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 476 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 477 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 478 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 479 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 480 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 481 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 482 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 483 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 484 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 485 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 486 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 487 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 488 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 489 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 490 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 491 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 492 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 493 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 494 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 495 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 496 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 497 >; 498 }; 499 500 pinctrl_lcdif_ctrl: lcdifctrlgrp { 501 fsl,pins = < 502 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 503 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 504 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 505 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 506 /* used for lcd reset */ 507 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 508 >; 509 }; 510 511 pinctrl_qspi: qspigrp { 512 fsl,pins = < 513 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 514 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 515 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 516 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 517 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 518 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 519 >; 520 }; 521 522 pinctrl_sai2: sai2grp { 523 fsl,pins = < 524 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 525 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 526 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 527 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 528 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 529 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 530 >; 531 }; 532 533 pinctrl_peri_3v3: peri3v3grp { 534 fsl,pins = < 535 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 536 >; 537 }; 538 539 pinctrl_pwm1: pwm1grp { 540 fsl,pins = < 541 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 542 >; 543 }; 544 545 pinctrl_sim2: sim2grp { 546 fsl,pins = < 547 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 548 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 549 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 550 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 551 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 552 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 553 >; 554 }; 555 556 pinctrl_spi4: spi4grp { 557 fsl,pins = < 558 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 559 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 560 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 561 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 562 >; 563 }; 564 565 pinctrl_tsc: tscgrp { 566 fsl,pins = < 567 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 568 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 569 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 570 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 571 >; 572 }; 573 574 pinctrl_uart1: uart1grp { 575 fsl,pins = < 576 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 577 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 578 >; 579 }; 580 581 pinctrl_uart2: uart2grp { 582 fsl,pins = < 583 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 584 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 585 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 586 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 587 >; 588 }; 589 590 pinctrl_usb_otg1: usbotg1grp { 591 fsl,pins = < 592 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 593 >; 594 }; 595 596 pinctrl_usdhc1: usdhc1grp { 597 fsl,pins = < 598 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 599 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 600 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 601 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 602 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 603 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 604 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 605 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 606 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 607 >; 608 }; 609 610 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 611 fsl,pins = < 612 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 613 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 614 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 615 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 616 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 617 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 618 619 >; 620 }; 621 622 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 623 fsl,pins = < 624 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 625 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 626 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 627 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 628 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 629 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 630 >; 631 }; 632 633 pinctrl_usdhc2: usdhc2grp { 634 fsl,pins = < 635 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 636 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 637 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 638 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 639 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 640 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 641 >; 642 }; 643 644 pinctrl_wdog: wdoggrp { 645 fsl,pins = < 646 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 647 >; 648 }; 649 }; 650
Indexes created Thu Oct 02 10:09:58 GMT 2025