imx6ul-14x14-evk.dtsi revision 1.1.1.1.4.1
1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5 / { 6 chosen { 7 stdout-path = &uart1; 8 }; 9 10 memory@80000000 { 11 device_type = "memory"; 12 reg = <0x80000000 0x20000000>; 13 }; 14 15 backlight_display: backlight-display { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000>; 18 brightness-levels = <0 4 8 16 32 64 128 255>; 19 default-brightness-level = <6>; 20 status = "okay"; 21 }; 22 23 24 reg_sd1_vmmc: regulator-sd1-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "VSD_3V3"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 reg_can_3v3: regulator-can-3v3 { 34 compatible = "regulator-fixed"; 35 regulator-name = "can-3v3"; 36 regulator-min-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>; 38 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 39 }; 40 41 sound { 42 compatible = "simple-audio-card"; 43 simple-audio-card,name = "mx6ul-wm8960"; 44 simple-audio-card,format = "i2s"; 45 simple-audio-card,bitclock-master = <&dailink_master>; 46 simple-audio-card,frame-master = <&dailink_master>; 47 simple-audio-card,widgets = 48 "Microphone", "Mic Jack", 49 "Line", "Line In", 50 "Line", "Line Out", 51 "Speaker", "Speaker", 52 "Headphone", "Headphone Jack"; 53 simple-audio-card,routing = 54 "Headphone Jack", "HP_L", 55 "Headphone Jack", "HP_R", 56 "Speaker", "SPK_LP", 57 "Speaker", "SPK_LN", 58 "Speaker", "SPK_RP", 59 "Speaker", "SPK_RN", 60 "LINPUT1", "Mic Jack", 61 "LINPUT3", "Mic Jack", 62 "RINPUT1", "Mic Jack", 63 "RINPUT2", "Mic Jack"; 64 65 simple-audio-card,cpu { 66 sound-dai = <&sai2>; 67 }; 68 69 dailink_master: simple-audio-card,codec { 70 sound-dai = <&codec>; 71 clocks = <&clks IMX6UL_CLK_SAI2>; 72 }; 73 }; 74 75 spi4 { 76 compatible = "spi-gpio"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_spi4>; 79 status = "okay"; 80 gpio-sck = <&gpio5 11 0>; 81 gpio-mosi = <&gpio5 10 0>; 82 cs-gpios = <&gpio5 7 0>; 83 num-chipselects = <1>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 gpio_spi: gpio@0 { 88 compatible = "fairchild,74hc595"; 89 gpio-controller; 90 #gpio-cells = <2>; 91 reg = <0>; 92 registers-number = <1>; 93 spi-max-frequency = <100000>; 94 }; 95 }; 96 97 panel { 98 compatible = "innolux,at043tn24"; 99 backlight = <&backlight_display>; 100 101 port { 102 panel_in: endpoint { 103 remote-endpoint = <&display_out>; 104 }; 105 }; 106 }; 107 }; 108 109 &clks { 110 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 111 assigned-clock-rates = <786432000>; 112 }; 113 114 &i2c2 { 115 clock_frequency = <100000>; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_i2c2>; 118 status = "okay"; 119 120 codec: wm8960@1a { 121 #sound-dai-cells = <0>; 122 compatible = "wlf,wm8960"; 123 reg = <0x1a>; 124 wlf,shared-lrclk; 125 }; 126 }; 127 128 &fec1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_enet1>; 131 phy-mode = "rmii"; 132 phy-handle = <ðphy0>; 133 status = "okay"; 134 }; 135 136 &fec2 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_enet2>; 139 phy-mode = "rmii"; 140 phy-handle = <ðphy1>; 141 status = "okay"; 142 143 mdio { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 ethphy0: ethernet-phy@2 { 148 reg = <2>; 149 micrel,led-mode = <1>; 150 clocks = <&clks IMX6UL_CLK_ENET_REF>; 151 clock-names = "rmii-ref"; 152 }; 153 154 ethphy1: ethernet-phy@1 { 155 reg = <1>; 156 micrel,led-mode = <1>; 157 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 158 clock-names = "rmii-ref"; 159 }; 160 }; 161 }; 162 163 &can1 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_flexcan1>; 166 xceiver-supply = <®_can_3v3>; 167 status = "okay"; 168 }; 169 170 &can2 { 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_flexcan2>; 173 xceiver-supply = <®_can_3v3>; 174 status = "okay"; 175 }; 176 177 &i2c1 { 178 clock-frequency = <100000>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_i2c1>; 181 status = "okay"; 182 183 mag3110@e { 184 compatible = "fsl,mag3110"; 185 reg = <0x0e>; 186 }; 187 }; 188 189 &lcdif { 190 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 191 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_lcdif_dat 194 &pinctrl_lcdif_ctrl>; 195 status = "okay"; 196 197 port { 198 display_out: endpoint { 199 remote-endpoint = <&panel_in>; 200 }; 201 }; 202 }; 203 204 &pwm1 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_pwm1>; 207 status = "okay"; 208 }; 209 210 &qspi { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_qspi>; 213 status = "okay"; 214 215 flash0: n25q256a@0 { 216 #address-cells = <1>; 217 #size-cells = <1>; 218 compatible = "micron,n25q256a"; 219 spi-max-frequency = <29000000>; 220 spi-rx-bus-width = <4>; 221 spi-tx-bus-width = <4>; 222 reg = <0>; 223 }; 224 }; 225 226 &sai2 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_sai2>; 229 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 230 <&clks IMX6UL_CLK_SAI2>; 231 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 232 assigned-clock-rates = <0>, <12288000>; 233 fsl,sai-mclk-direction-output; 234 status = "okay"; 235 }; 236 237 &snvs_poweroff { 238 status = "okay"; 239 }; 240 241 &tsc { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_tsc>; 244 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 245 measure-delay-time = <0xffff>; 246 pre-charge-time = <0xfff>; 247 status = "okay"; 248 }; 249 250 &uart1 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_uart1>; 253 status = "okay"; 254 }; 255 256 &uart2 { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart2>; 259 uart-has-rtscts; 260 status = "okay"; 261 }; 262 263 &usbotg1 { 264 dr_mode = "otg"; 265 status = "okay"; 266 }; 267 268 &usbotg2 { 269 dr_mode = "host"; 270 disable-over-current; 271 status = "okay"; 272 }; 273 274 &usbphy1 { 275 fsl,tx-d-cal = <106>; 276 }; 277 278 &usbphy2 { 279 fsl,tx-d-cal = <106>; 280 }; 281 282 &usdhc1 { 283 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 284 pinctrl-0 = <&pinctrl_usdhc1>; 285 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 286 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 287 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 288 keep-power-in-suspend; 289 wakeup-source; 290 vmmc-supply = <®_sd1_vmmc>; 291 status = "okay"; 292 }; 293 294 &usdhc2 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_usdhc2>; 297 no-1-8-v; 298 keep-power-in-suspend; 299 wakeup-source; 300 status = "okay"; 301 }; 302 303 &wdog1 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_wdog>; 306 fsl,ext-reset-output; 307 }; 308 309 &iomuxc { 310 pinctrl-names = "default"; 311 312 pinctrl_csi1: csi1grp { 313 fsl,pins = < 314 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 315 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 316 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 317 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 318 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 319 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 320 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 321 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 322 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 323 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 324 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 325 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 326 >; 327 }; 328 329 pinctrl_enet1: enet1grp { 330 fsl,pins = < 331 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 332 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 333 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 334 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 335 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 336 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 337 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 338 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 339 >; 340 }; 341 342 pinctrl_enet2: enet2grp { 343 fsl,pins = < 344 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 345 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 346 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 347 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 348 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 349 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 350 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 351 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 352 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 353 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 354 >; 355 }; 356 357 pinctrl_flexcan1: flexcan1grp{ 358 fsl,pins = < 359 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 360 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 361 >; 362 }; 363 364 pinctrl_flexcan2: flexcan2grp{ 365 fsl,pins = < 366 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 367 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 368 >; 369 }; 370 371 pinctrl_i2c1: i2c1grp { 372 fsl,pins = < 373 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 374 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 375 >; 376 }; 377 378 pinctrl_i2c2: i2c2grp { 379 fsl,pins = < 380 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 381 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 382 >; 383 }; 384 385 pinctrl_lcdif_dat: lcdifdatgrp { 386 fsl,pins = < 387 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 388 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 389 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 390 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 391 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 392 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 393 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 394 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 395 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 396 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 397 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 398 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 399 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 400 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 401 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 402 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 403 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 404 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 405 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 406 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 407 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 408 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 409 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 410 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 411 >; 412 }; 413 414 pinctrl_lcdif_ctrl: lcdifctrlgrp { 415 fsl,pins = < 416 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 417 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 418 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 419 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 420 /* used for lcd reset */ 421 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 422 >; 423 }; 424 425 pinctrl_qspi: qspigrp { 426 fsl,pins = < 427 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 428 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 429 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 430 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 431 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 432 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 433 >; 434 }; 435 436 pinctrl_sai2: sai2grp { 437 fsl,pins = < 438 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 439 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 440 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 441 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 442 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 443 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 444 >; 445 }; 446 447 pinctrl_pwm1: pwm1grp { 448 fsl,pins = < 449 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 450 >; 451 }; 452 453 pinctrl_sim2: sim2grp { 454 fsl,pins = < 455 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 456 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 457 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 458 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 459 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 460 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 461 >; 462 }; 463 464 pinctrl_spi4: spi4grp { 465 fsl,pins = < 466 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 467 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 468 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 469 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 470 >; 471 }; 472 473 pinctrl_tsc: tscgrp { 474 fsl,pins = < 475 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 476 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 477 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 478 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 479 >; 480 }; 481 482 pinctrl_uart1: uart1grp { 483 fsl,pins = < 484 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 485 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 486 >; 487 }; 488 489 pinctrl_uart2: uart2grp { 490 fsl,pins = < 491 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 492 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 493 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 494 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 495 >; 496 }; 497 498 pinctrl_usdhc1: usdhc1grp { 499 fsl,pins = < 500 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 501 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 502 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 503 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 504 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 505 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 506 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 507 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 508 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 509 >; 510 }; 511 512 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 513 fsl,pins = < 514 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 515 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 516 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 517 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 518 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 519 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 520 521 >; 522 }; 523 524 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 525 fsl,pins = < 526 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 527 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 528 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 529 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 530 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 531 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 532 >; 533 }; 534 535 pinctrl_usdhc2: usdhc2grp { 536 fsl,pins = < 537 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 538 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 539 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 540 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 541 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 542 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 543 >; 544 }; 545 546 pinctrl_wdog: wdoggrp { 547 fsl,pins = < 548 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 549 >; 550 }; 551 }; 552
Indexes created Sun Oct 26 21:10:03 GMT 2025