imx6ul-14x14-evk.dtsi revision 1.1.1.1.4.2
1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5 / { 6 chosen { 7 stdout-path = &uart1; 8 }; 9 10 memory@80000000 { 11 device_type = "memory"; 12 reg = <0x80000000 0x20000000>; 13 }; 14 15 backlight_display: backlight-display { 16 compatible = "pwm-backlight"; 17 pwms = <&pwm1 0 5000000>; 18 brightness-levels = <0 4 8 16 32 64 128 255>; 19 default-brightness-level = <6>; 20 status = "okay"; 21 }; 22 23 24 reg_sd1_vmmc: regulator-sd1-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "VSD_3V3"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32 33 reg_peri_3v3: regulator-peri-3v3 { 34 compatible = "regulator-fixed"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_peri_3v3>; 37 regulator-name = "VPERI_3V3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 41 /* 42 * If you want to want to make this dynamic please 43 * check schematics and test all affected peripherals: 44 * 45 * - sensors 46 * - ethernet phy 47 * - can 48 * - bluetooth 49 * - wm8960 audio codec 50 * - ov5640 camera 51 */ 52 regulator-always-on; 53 }; 54 55 reg_can_3v3: regulator-can-3v3 { 56 compatible = "regulator-fixed"; 57 regulator-name = "can-3v3"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 61 }; 62 63 sound { 64 compatible = "simple-audio-card"; 65 simple-audio-card,name = "mx6ul-wm8960"; 66 simple-audio-card,format = "i2s"; 67 simple-audio-card,bitclock-master = <&dailink_master>; 68 simple-audio-card,frame-master = <&dailink_master>; 69 simple-audio-card,widgets = 70 "Microphone", "Mic Jack", 71 "Line", "Line In", 72 "Line", "Line Out", 73 "Speaker", "Speaker", 74 "Headphone", "Headphone Jack"; 75 simple-audio-card,routing = 76 "Headphone Jack", "HP_L", 77 "Headphone Jack", "HP_R", 78 "Speaker", "SPK_LP", 79 "Speaker", "SPK_LN", 80 "Speaker", "SPK_RP", 81 "Speaker", "SPK_RN", 82 "LINPUT1", "Mic Jack", 83 "LINPUT3", "Mic Jack", 84 "RINPUT1", "Mic Jack", 85 "RINPUT2", "Mic Jack"; 86 87 simple-audio-card,cpu { 88 sound-dai = <&sai2>; 89 }; 90 91 dailink_master: simple-audio-card,codec { 92 sound-dai = <&codec>; 93 clocks = <&clks IMX6UL_CLK_SAI2>; 94 }; 95 }; 96 97 spi4 { 98 compatible = "spi-gpio"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_spi4>; 101 status = "okay"; 102 gpio-sck = <&gpio5 11 0>; 103 gpio-mosi = <&gpio5 10 0>; 104 cs-gpios = <&gpio5 7 0>; 105 num-chipselects = <1>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 gpio_spi: gpio@0 { 110 compatible = "fairchild,74hc595"; 111 gpio-controller; 112 #gpio-cells = <2>; 113 reg = <0>; 114 registers-number = <1>; 115 spi-max-frequency = <100000>; 116 }; 117 }; 118 119 panel { 120 compatible = "innolux,at043tn24"; 121 backlight = <&backlight_display>; 122 123 port { 124 panel_in: endpoint { 125 remote-endpoint = <&display_out>; 126 }; 127 }; 128 }; 129 }; 130 131 &clks { 132 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 133 assigned-clock-rates = <786432000>; 134 }; 135 136 &i2c2 { 137 clock-frequency = <100000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c2>; 140 status = "okay"; 141 142 codec: wm8960@1a { 143 #sound-dai-cells = <0>; 144 compatible = "wlf,wm8960"; 145 reg = <0x1a>; 146 wlf,shared-lrclk; 147 }; 148 }; 149 150 &fec1 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_enet1>; 153 phy-mode = "rmii"; 154 phy-handle = <ðphy0>; 155 phy-supply = <®_peri_3v3>; 156 status = "okay"; 157 }; 158 159 &fec2 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_enet2>; 162 phy-mode = "rmii"; 163 phy-handle = <ðphy1>; 164 phy-supply = <®_peri_3v3>; 165 status = "okay"; 166 167 mdio { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 ethphy0: ethernet-phy@2 { 172 reg = <2>; 173 micrel,led-mode = <1>; 174 clocks = <&clks IMX6UL_CLK_ENET_REF>; 175 clock-names = "rmii-ref"; 176 }; 177 178 ethphy1: ethernet-phy@1 { 179 reg = <1>; 180 micrel,led-mode = <1>; 181 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 182 clock-names = "rmii-ref"; 183 }; 184 }; 185 }; 186 187 &can1 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_flexcan1>; 190 xceiver-supply = <®_can_3v3>; 191 status = "okay"; 192 }; 193 194 &can2 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_flexcan2>; 197 xceiver-supply = <®_can_3v3>; 198 status = "okay"; 199 }; 200 201 &i2c1 { 202 clock-frequency = <100000>; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_i2c1>; 205 status = "okay"; 206 207 magnetometer@e { 208 compatible = "fsl,mag3110"; 209 reg = <0x0e>; 210 vdd-supply = <®_peri_3v3>; 211 vddio-supply = <®_peri_3v3>; 212 }; 213 }; 214 215 &lcdif { 216 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 217 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_lcdif_dat 220 &pinctrl_lcdif_ctrl>; 221 status = "okay"; 222 223 port { 224 display_out: endpoint { 225 remote-endpoint = <&panel_in>; 226 }; 227 }; 228 }; 229 230 &pwm1 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_pwm1>; 233 status = "okay"; 234 }; 235 236 &qspi { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_qspi>; 239 status = "okay"; 240 241 flash0: n25q256a@0 { 242 #address-cells = <1>; 243 #size-cells = <1>; 244 compatible = "micron,n25q256a", "jedec,spi-nor"; 245 spi-max-frequency = <29000000>; 246 spi-rx-bus-width = <4>; 247 spi-tx-bus-width = <4>; 248 reg = <0>; 249 }; 250 }; 251 252 &sai2 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_sai2>; 255 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 256 <&clks IMX6UL_CLK_SAI2>; 257 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 258 assigned-clock-rates = <0>, <12288000>; 259 fsl,sai-mclk-direction-output; 260 status = "okay"; 261 }; 262 263 &snvs_poweroff { 264 status = "okay"; 265 }; 266 267 &snvs_pwrkey { 268 status = "okay"; 269 }; 270 271 &tsc { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_tsc>; 274 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 275 measure-delay-time = <0xffff>; 276 pre-charge-time = <0xfff>; 277 status = "okay"; 278 }; 279 280 &uart1 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_uart1>; 283 status = "okay"; 284 }; 285 286 &uart2 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_uart2>; 289 uart-has-rtscts; 290 status = "okay"; 291 }; 292 293 &usbotg1 { 294 dr_mode = "otg"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_usb_otg1>; 297 status = "okay"; 298 }; 299 300 &usbotg2 { 301 dr_mode = "host"; 302 disable-over-current; 303 status = "okay"; 304 }; 305 306 &usbphy1 { 307 fsl,tx-d-cal = <106>; 308 }; 309 310 &usbphy2 { 311 fsl,tx-d-cal = <106>; 312 }; 313 314 &usdhc1 { 315 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 316 pinctrl-0 = <&pinctrl_usdhc1>; 317 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 318 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 319 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 320 keep-power-in-suspend; 321 wakeup-source; 322 vmmc-supply = <®_sd1_vmmc>; 323 status = "okay"; 324 }; 325 326 &usdhc2 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&pinctrl_usdhc2>; 329 no-1-8-v; 330 keep-power-in-suspend; 331 wakeup-source; 332 status = "okay"; 333 }; 334 335 &wdog1 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_wdog>; 338 fsl,ext-reset-output; 339 }; 340 341 &iomuxc { 342 pinctrl-names = "default"; 343 344 pinctrl_csi1: csi1grp { 345 fsl,pins = < 346 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 347 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 348 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 349 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 350 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 351 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 352 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 353 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 354 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 355 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 356 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 357 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 358 >; 359 }; 360 361 pinctrl_enet1: enet1grp { 362 fsl,pins = < 363 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 364 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 365 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 366 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 367 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 368 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 369 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 370 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 371 >; 372 }; 373 374 pinctrl_enet2: enet2grp { 375 fsl,pins = < 376 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 377 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 378 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 379 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 380 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 381 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 382 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 383 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 384 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 385 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 386 >; 387 }; 388 389 pinctrl_flexcan1: flexcan1grp{ 390 fsl,pins = < 391 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 392 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 393 >; 394 }; 395 396 pinctrl_flexcan2: flexcan2grp{ 397 fsl,pins = < 398 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 399 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 400 >; 401 }; 402 403 pinctrl_i2c1: i2c1grp { 404 fsl,pins = < 405 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 406 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 407 >; 408 }; 409 410 pinctrl_i2c2: i2c2grp { 411 fsl,pins = < 412 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 413 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 414 >; 415 }; 416 417 pinctrl_lcdif_dat: lcdifdatgrp { 418 fsl,pins = < 419 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 420 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 421 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 422 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 423 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 424 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 425 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 426 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 427 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 428 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 429 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 430 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 431 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 432 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 433 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 434 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 435 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 436 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 437 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 438 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 439 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 440 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 441 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 442 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 443 >; 444 }; 445 446 pinctrl_lcdif_ctrl: lcdifctrlgrp { 447 fsl,pins = < 448 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 449 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 450 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 451 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 452 /* used for lcd reset */ 453 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 454 >; 455 }; 456 457 pinctrl_qspi: qspigrp { 458 fsl,pins = < 459 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 460 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 461 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 462 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 463 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 464 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 465 >; 466 }; 467 468 pinctrl_sai2: sai2grp { 469 fsl,pins = < 470 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 471 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 472 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 473 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 474 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 475 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 476 >; 477 }; 478 479 pinctrl_peri_3v3: peri3v3grp { 480 fsl,pins = < 481 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 482 >; 483 }; 484 485 pinctrl_pwm1: pwm1grp { 486 fsl,pins = < 487 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 488 >; 489 }; 490 491 pinctrl_sim2: sim2grp { 492 fsl,pins = < 493 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 494 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 495 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 496 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 497 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 498 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 499 >; 500 }; 501 502 pinctrl_spi4: spi4grp { 503 fsl,pins = < 504 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 505 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 506 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 507 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 508 >; 509 }; 510 511 pinctrl_tsc: tscgrp { 512 fsl,pins = < 513 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 514 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 515 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 516 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 517 >; 518 }; 519 520 pinctrl_uart1: uart1grp { 521 fsl,pins = < 522 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 523 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 524 >; 525 }; 526 527 pinctrl_uart2: uart2grp { 528 fsl,pins = < 529 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 530 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 531 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 532 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 533 >; 534 }; 535 536 pinctrl_usb_otg1: usbotg1grp { 537 fsl,pins = < 538 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 539 >; 540 }; 541 542 pinctrl_usdhc1: usdhc1grp { 543 fsl,pins = < 544 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 545 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 546 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 547 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 548 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 549 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 550 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 551 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 552 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 553 >; 554 }; 555 556 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 557 fsl,pins = < 558 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 559 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 560 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 561 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 562 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 563 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 564 565 >; 566 }; 567 568 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 569 fsl,pins = < 570 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 571 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 572 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 573 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 574 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 575 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 576 >; 577 }; 578 579 pinctrl_usdhc2: usdhc2grp { 580 fsl,pins = < 581 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 582 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 583 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 584 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 585 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 586 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 587 >; 588 }; 589 590 pinctrl_wdog: wdoggrp { 591 fsl,pins = < 592 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 593 >; 594 }; 595 }; 596
Indexes created Wed Oct 29 18:09:52 GMT 2025