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      1 // SPDX-License-Identifier: GPL-2.0
      2 /*
      3  * Copyright (C) 2017 exceet electronics GmbH
      4  * Copyright (C) 2018 Kontron Electronics GmbH
      5  * Copyright (c) 2019 Krzysztof Kozlowski <krzk (a] kernel.org>
      6  */
      7 
      8 #include <dt-bindings/gpio/gpio.h>
      9 
     10 / {
     11 	chosen {
     12 		stdout-path = &uart4;
     13 	};
     14 };
     15 
     16 &ecspi2 {
     17 	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
     18 	pinctrl-names = "default";
     19 	pinctrl-0 = <&pinctrl_ecspi2>;
     20 	status = "okay";
     21 
     22 	spi-flash@0 {
     23 		compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
     24 		spi-max-frequency = <50000000>;
     25 		reg = <0>;
     26 	};
     27 };
     28 
     29 &fec1 {
     30 	pinctrl-names = "default";
     31 	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
     32 	phy-mode = "rmii";
     33 	phy-handle = <&ethphy1>;
     34 	status = "okay";
     35 
     36 	mdio {
     37 		#address-cells = <1>;
     38 		#size-cells = <0>;
     39 
     40 		ethphy1: ethernet-phy@1 {
     41 			reg = <1>;
     42 			micrel,led-mode = <0>;
     43 			clocks = <&clks IMX6UL_CLK_ENET_REF>;
     44 			clock-names = "rmii-ref";
     45 		};
     46 	};
     47 };
     48 
     49 &fec2 {
     50 	phy-mode = "rmii";
     51 	status = "disabled";
     52 };
     53 
     54 &qspi {
     55 	pinctrl-names = "default";
     56 	pinctrl-0 = <&pinctrl_qspi>;
     57 	status = "okay";
     58 };
     59 
     60 &wdog1 {
     61 	pinctrl-names = "default";
     62 	pinctrl-0 = <&pinctrl_wdog>;
     63 	fsl,ext-reset-output;
     64 	status = "okay";
     65 };
     66 
     67 &iomuxc {
     68 	pinctrl-names = "default";
     69 	pinctrl-0 = <&pinctrl_reset_out>;
     70 
     71 	pinctrl_ecspi2: ecspi2grp {
     72 		fsl,pins = <
     73 			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO      0x100b1
     74 			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI      0x100b1
     75 			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK      0x100b1
     76 			MX6UL_PAD_CSI_DATA01__GPIO4_IO22       0x100b1
     77 		>;
     78 	};
     79 
     80 	pinctrl_enet1: enet1grp {
     81 		fsl,pins = <
     82 			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
     83 			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
     84 			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
     85 			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
     86 			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
     87 			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
     88 			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
     89 			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b009
     90 		>;
     91 	};
     92 
     93 	pinctrl_enet1_mdio: enet1mdiogrp {
     94 		fsl,pins = <
     95 			MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
     96 			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
     97 		>;
     98 	};
     99 
    100 	pinctrl_qspi: qspigrp {
    101 		fsl,pins = <
    102 			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
    103 			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
    104 			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
    105 			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
    106 			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
    107 			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
    108 		>;
    109 	};
    110 
    111 	pinctrl_reset_out: rstoutgrp {
    112 		fsl,pins = <
    113 			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
    114 		>;
    115 	};
    116 
    117 	pinctrl_wdog: wdoggrp {
    118 		fsl,pins = <
    119 			MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x18b0
    120 		>;
    121 	};
    122 };
    123