1 // SPDX-License-Identifier: GPL-2.0 OR X11 2 /* 3 * Copyright 2016 Boundary Devices, Inc. 4 */ 5 6 /dts-v1/; 7 8 #include "imx7d.dtsi" 9 10 / { 11 model = "Boundary Devices i.MX7 Nitrogen7 Board"; 12 compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x40000000>; 17 }; 18 19 backlight-j9 { 20 compatible = "gpio-backlight"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_backlight_j9>; 23 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 24 default-on; 25 }; 26 27 backlight_lcd: backlight-j20 { 28 compatible = "pwm-backlight"; 29 pwms = <&pwm1 0 5000000 0>; 30 brightness-levels = <0 4 8 16 32 64 128 255>; 31 default-brightness-level = <6>; 32 status = "okay"; 33 }; 34 35 panel-lcd { 36 compatible = "okaya,rs800480t-7x0gp"; 37 backlight = <&backlight_lcd>; 38 39 port { 40 panel_in: endpoint { 41 remote-endpoint = <&lcdif_out>; 42 }; 43 }; 44 }; 45 46 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 47 compatible = "regulator-fixed"; 48 regulator-name = "usb_otg1_vbus"; 49 regulator-min-microvolt = <5000000>; 50 regulator-max-microvolt = <5000000>; 51 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 56 compatible = "regulator-fixed"; 57 regulator-name = "usb_otg2_vbus"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; 61 enable-active-high; 62 }; 63 64 reg_can2_3v3: regulator-can2-3v3 { 65 compatible = "regulator-fixed"; 66 regulator-name = "can2-3v3"; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 70 }; 71 72 reg_vref_1v8: regulator-vref-1v8 { 73 compatible = "regulator-fixed"; 74 regulator-name = "vref-1v8"; 75 regulator-min-microvolt = <1800000>; 76 regulator-max-microvolt = <1800000>; 77 }; 78 79 reg_vref_3v3: regulator-vref-3v3 { 80 compatible = "regulator-fixed"; 81 regulator-name = "vref-3v3"; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 }; 85 86 reg_wlan: regulator-wlan { 87 compatible = "regulator-fixed"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 regulator-name = "reg_wlan"; 91 startup-delay-us = <70000>; 92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 }; 95 96 usdhc2_pwrseq: usdhc2_pwrseq { 97 compatible = "mmc-pwrseq-simple"; 98 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; 99 clock-names = "ext_clock"; 100 }; 101 }; 102 103 &adc1 { 104 vref-supply = <®_vref_1v8>; 105 status = "okay"; 106 }; 107 108 &adc2 { 109 vref-supply = <®_vref_1v8>; 110 status = "okay"; 111 }; 112 113 &clks { 114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, 115 <&clks IMX7D_CLKO2_ROOT_DIV>; 116 assigned-clock-parents = <&clks IMX7D_CKIL>; 117 assigned-clock-rates = <0>, <32768>; 118 }; 119 120 &cpu0 { 121 cpu-supply = <&sw1a_reg>; 122 }; 123 124 &cpu1 { 125 cpu-supply = <&sw1a_reg>; 126 }; 127 128 &fec1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_enet1>; 131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 132 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 134 assigned-clock-rates = <0>, <100000000>; 135 phy-mode = "rgmii"; 136 phy-handle = <ðphy0>; 137 fsl,magic-packet; 138 status = "okay"; 139 140 mdio { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 ethphy0: ethernet-phy@4 { 145 reg = <4>; 146 }; 147 }; 148 }; 149 150 &flexcan2 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_flexcan2>; 153 xceiver-supply = <®_can2_3v3>; 154 status = "okay"; 155 }; 156 157 &i2c1 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_i2c1>; 160 status = "okay"; 161 162 pmic: pmic@8 { 163 compatible = "fsl,pfuze3000"; 164 reg = <0x08>; 165 166 regulators { 167 sw1a_reg: sw1a { 168 regulator-min-microvolt = <700000>; 169 regulator-max-microvolt = <1475000>; 170 regulator-boot-on; 171 regulator-always-on; 172 regulator-ramp-delay = <6250>; 173 }; 174 175 /* use sw1c_reg to align with pfuze100/pfuze200 */ 176 sw1c_reg: sw1b { 177 regulator-min-microvolt = <700000>; 178 regulator-max-microvolt = <1475000>; 179 regulator-boot-on; 180 regulator-always-on; 181 regulator-ramp-delay = <6250>; 182 }; 183 184 sw2_reg: sw2 { 185 regulator-min-microvolt = <1500000>; 186 regulator-max-microvolt = <1850000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 sw3a_reg: sw3 { 192 regulator-min-microvolt = <900000>; 193 regulator-max-microvolt = <1650000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 swbst_reg: swbst { 199 regulator-min-microvolt = <5000000>; 200 regulator-max-microvolt = <5150000>; 201 }; 202 203 snvs_reg: vsnvs { 204 regulator-min-microvolt = <1000000>; 205 regulator-max-microvolt = <3000000>; 206 regulator-boot-on; 207 regulator-always-on; 208 }; 209 210 vref_reg: vrefddr { 211 regulator-boot-on; 212 regulator-always-on; 213 }; 214 215 vgen1_reg: vldo1 { 216 regulator-min-microvolt = <1800000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-always-on; 219 }; 220 221 vgen2_reg: vldo2 { 222 regulator-min-microvolt = <800000>; 223 regulator-max-microvolt = <1550000>; 224 regulator-always-on; 225 }; 226 227 vgen3_reg: vccsd { 228 regulator-min-microvolt = <2850000>; 229 regulator-max-microvolt = <3300000>; 230 regulator-always-on; 231 }; 232 233 vgen4_reg: v33 { 234 regulator-min-microvolt = <2850000>; 235 regulator-max-microvolt = <3300000>; 236 regulator-always-on; 237 }; 238 239 vgen5_reg: vldo3 { 240 regulator-min-microvolt = <1800000>; 241 regulator-max-microvolt = <3300000>; 242 regulator-always-on; 243 }; 244 245 vgen6_reg: vldo4 { 246 regulator-min-microvolt = <1800000>; 247 regulator-max-microvolt = <3300000>; 248 regulator-always-on; 249 }; 250 }; 251 }; 252 }; 253 254 &i2c2 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_i2c2>; 257 status = "okay"; 258 259 rtc@68 { 260 compatible = "microcrystal,rv4162"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_i2c2_rv4162>; 263 reg = <0x68>; 264 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>; 265 }; 266 }; 267 268 &i2c3 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_i2c3>; 271 status = "okay"; 272 273 touch@48 { 274 compatible = "ti,tsc2004"; 275 reg = <0x48>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_i2c3_tsc2004>; 278 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; 279 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; 280 }; 281 }; 282 283 &i2c4 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_i2c4>; 286 status = "okay"; 287 288 codec: wm8960@1a { 289 compatible = "wlf,wm8960"; 290 reg = <0x1a>; 291 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 292 clock-names = "mclk"; 293 wlf,shared-lrclk; 294 }; 295 }; 296 297 &lcdif { 298 status = "okay"; 299 300 port { 301 lcdif_out: endpoint { 302 remote-endpoint = <&panel_in>; 303 }; 304 }; 305 }; 306 307 &pwm1 { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_pwm1>; 310 status = "okay"; 311 }; 312 313 &pwm2 { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_pwm2>; 316 status = "okay"; 317 }; 318 319 &uart1 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_uart1>; 322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 324 status = "okay"; 325 }; 326 327 &uart2 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_uart2>; 330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; 331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 332 status = "okay"; 333 }; 334 335 &uart3 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart3>; 338 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; 339 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 340 status = "okay"; 341 }; 342 343 &uart6 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_uart6>; 346 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 347 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 348 uart-has-rtscts; 349 status = "okay"; 350 }; 351 352 &usbotg1 { 353 vbus-supply = <®_usb_otg1_vbus>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_usbotg1>; 356 status = "okay"; 357 }; 358 359 &usbotg2 { 360 vbus-supply = <®_usb_otg2_vbus>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_usbotg2>; 363 dr_mode = "host"; 364 status = "okay"; 365 }; 366 367 &usdhc1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_usdhc1>; 370 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 371 vmmc-supply = <&vgen3_reg>; 372 bus-width = <4>; 373 fsl,tuning-step = <2>; 374 wakeup-source; 375 keep-power-in-suspend; 376 status = "okay"; 377 }; 378 379 &usdhc2 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_usdhc2>; 384 bus-width = <4>; 385 non-removable; 386 vmmc-supply = <®_wlan>; 387 mmc-pwrseq = <&usdhc2_pwrseq>; 388 cap-power-off-card; 389 keep-power-in-suspend; 390 status = "okay"; 391 392 wlcore: wlcore@2 { 393 compatible = "ti,wl1271"; 394 reg = <2>; 395 interrupt-parent = <&gpio4>; 396 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 397 ref-clock-frequency = <38400000>; 398 }; 399 }; 400 401 &usdhc3 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_usdhc3>; 404 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 405 assigned-clock-rates = <400000000>; 406 bus-width = <8>; 407 fsl,tuning-step = <2>; 408 non-removable; 409 status = "okay"; 410 }; 411 412 &wdog1 { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_wdog1>; 415 status = "okay"; 416 }; 417 418 &iomuxc { 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>; 421 422 pinctrl_hog_1: hoggrp { 423 fsl,pins = < 424 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d 425 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d 426 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d 427 >; 428 }; 429 430 pinctrl_enet1: enet1grp { 431 fsl,pins = < 432 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 433 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 434 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3 435 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 436 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 437 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 438 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 439 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 440 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 441 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71 442 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11 443 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11 444 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11 445 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71 446 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11 447 MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75 448 >; 449 }; 450 451 pinctrl_flexcan2: flexcan2grp { 452 fsl,pins = < 453 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d 454 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d 455 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d 456 >; 457 }; 458 459 pinctrl_i2c1: i2c1grp { 460 fsl,pins = < 461 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 462 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 463 >; 464 }; 465 466 pinctrl_i2c2: i2c2grp { 467 fsl,pins = < 468 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 469 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 470 >; 471 }; 472 473 pinctrl_i2c2_rv4162: i2c2-rv4162grp { 474 fsl,pins = < 475 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d 476 >; 477 }; 478 479 pinctrl_i2c3: i2c3grp { 480 fsl,pins = < 481 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 482 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 483 >; 484 }; 485 486 pinctrl_i2c3_tsc2004: i2c3tsc2004grp { 487 fsl,pins = < 488 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 489 MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d 490 >; 491 }; 492 493 pinctrl_i2c4: i2c4grp { 494 fsl,pins = < 495 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f 496 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f 497 >; 498 }; 499 500 pinctrl_j2: j2grp { 501 fsl,pins = < 502 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d 503 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d 504 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d 505 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d 506 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d 507 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d 508 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d 509 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d 510 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d 511 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d 512 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d 513 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d 514 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d 515 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d 516 MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d 517 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d 518 MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d 519 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d 520 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d 521 MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d 522 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d 523 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d 524 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d 525 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d 526 MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d 527 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d 528 MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d 529 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d 530 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d 531 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d 532 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d 533 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d 534 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d 535 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d 536 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d 537 >; 538 }; 539 540 pinctrl_lcdif_dat: lcdifdatgrp { 541 fsl,pins = < 542 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 543 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 544 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 545 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 546 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 547 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 548 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 549 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 550 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 551 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 552 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 553 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 554 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 555 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 556 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 557 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 558 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 559 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 560 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 561 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 562 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 563 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 564 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 565 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 566 >; 567 }; 568 569 pinctrl_lcdif_ctrl: lcdifctrlgrp { 570 fsl,pins = < 571 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 572 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 573 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 574 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 575 >; 576 }; 577 578 pinctrl_pwm2: pwm2grp { 579 fsl,pins = < 580 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d 581 >; 582 }; 583 584 pinctrl_uart1: uart1grp { 585 fsl,pins = < 586 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 587 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 588 >; 589 }; 590 591 pinctrl_uart2: uart2grp { 592 fsl,pins = < 593 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 594 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 595 >; 596 }; 597 598 pinctrl_uart3: uart3grp { 599 fsl,pins = < 600 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 601 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 602 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d 603 >; 604 }; 605 606 pinctrl_uart6: uart6grp { 607 fsl,pins = < 608 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 609 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 610 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 611 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 612 >; 613 }; 614 615 pinctrl_usbotg2: usbotg2grp { 616 fsl,pins = < 617 MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d 618 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 619 >; 620 }; 621 622 pinctrl_usdhc1: usdhc1grp { 623 fsl,pins = < 624 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 625 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 626 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 627 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 628 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 629 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 630 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75 631 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75 632 >; 633 }; 634 635 pinctrl_usdhc2: usdhc2grp { 636 fsl,pins = < 637 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 638 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 639 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 640 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 641 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 642 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 643 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59 644 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 645 >; 646 }; 647 648 pinctrl_usdhc3: usdhc3grp { 649 fsl,pins = < 650 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 651 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 652 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 653 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 654 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 655 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 656 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 657 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 658 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 659 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 660 >; 661 }; 662 }; 663 664 &iomuxc_lpsr { 665 pinctrl-names = "default"; 666 pinctrl-0 = <&pinctrl_hog_2>; 667 668 pinctrl_hog_2: hoggrp { 669 fsl,pins = < 670 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d 671 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d 672 >; 673 }; 674 675 pinctrl_backlight_j9: backlightj9grp { 676 fsl,pins = < 677 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d 678 >; 679 }; 680 681 pinctrl_pwm1: pwm1grp { 682 fsl,pins = < 683 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d 684 >; 685 }; 686 687 pinctrl_usbotg1: usbotg1grp { 688 fsl,pins = < 689 MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d 690 MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 691 >; 692 }; 693 694 pinctrl_wdog1: wdog1grp { 695 fsl,pins = < 696 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75 697 >; 698 }; 699 }; 700
Indexes created Mon Oct 26 00:26:21 UTC 2026