r8a7794.dtsi revision 1.1.1.3
1 /* 2 * Device Tree Source for the r8a7794 SoC 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Ulrich Hecht 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 #include <dt-bindings/clock/r8a7794-clock.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/interrupt-controller/irq.h> 15 #include <dt-bindings/power/r8a7794-sysc.h> 16 17 / { 18 compatible = "renesas,r8a7794"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 spi0 = &qspi; 33 vin0 = &vin0; 34 vin1 = &vin1; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0>; 45 clock-frequency = <1000000000>; 46 clocks = <&z2_clk>; 47 power-domains = <&sysc R8A7794_PD_CA7_CPU0>; 48 next-level-cache = <&L2_CA7>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <1>; 55 clock-frequency = <1000000000>; 56 power-domains = <&sysc R8A7794_PD_CA7_CPU1>; 57 next-level-cache = <&L2_CA7>; 58 }; 59 60 L2_CA7: cache-controller-0 { 61 compatible = "cache"; 62 power-domains = <&sysc R8A7794_PD_CA7_SCU>; 63 cache-unified; 64 cache-level = <2>; 65 }; 66 }; 67 68 gic: interrupt-controller@f1001000 { 69 compatible = "arm,gic-400"; 70 #interrupt-cells = <3>; 71 #address-cells = <0>; 72 interrupt-controller; 73 reg = <0 0xf1001000 0 0x1000>, 74 <0 0xf1002000 0 0x2000>, 75 <0 0xf1004000 0 0x2000>, 76 <0 0xf1006000 0 0x2000>; 77 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 78 clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; 79 clock-names = "clk"; 80 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 81 }; 82 83 gpio0: gpio@e6050000 { 84 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 85 reg = <0 0xe6050000 0 0x50>; 86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 87 #gpio-cells = <2>; 88 gpio-controller; 89 gpio-ranges = <&pfc 0 0 32>; 90 #interrupt-cells = <2>; 91 interrupt-controller; 92 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; 93 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 94 }; 95 96 gpio1: gpio@e6051000 { 97 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 98 reg = <0 0xe6051000 0 0x50>; 99 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 100 #gpio-cells = <2>; 101 gpio-controller; 102 gpio-ranges = <&pfc 0 32 26>; 103 #interrupt-cells = <2>; 104 interrupt-controller; 105 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; 106 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 107 }; 108 109 gpio2: gpio@e6052000 { 110 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 111 reg = <0 0xe6052000 0 0x50>; 112 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 113 #gpio-cells = <2>; 114 gpio-controller; 115 gpio-ranges = <&pfc 0 64 32>; 116 #interrupt-cells = <2>; 117 interrupt-controller; 118 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; 119 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 120 }; 121 122 gpio3: gpio@e6053000 { 123 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 124 reg = <0 0xe6053000 0 0x50>; 125 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 126 #gpio-cells = <2>; 127 gpio-controller; 128 gpio-ranges = <&pfc 0 96 32>; 129 #interrupt-cells = <2>; 130 interrupt-controller; 131 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; 132 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 133 }; 134 135 gpio4: gpio@e6054000 { 136 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 137 reg = <0 0xe6054000 0 0x50>; 138 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 139 #gpio-cells = <2>; 140 gpio-controller; 141 gpio-ranges = <&pfc 0 128 32>; 142 #interrupt-cells = <2>; 143 interrupt-controller; 144 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; 145 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 146 }; 147 148 gpio5: gpio@e6055000 { 149 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 150 reg = <0 0xe6055000 0 0x50>; 151 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 160 28>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; 158 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 159 }; 160 161 gpio6: gpio@e6055400 { 162 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 163 reg = <0 0xe6055400 0 0x50>; 164 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 165 #gpio-cells = <2>; 166 gpio-controller; 167 gpio-ranges = <&pfc 0 192 26>; 168 #interrupt-cells = <2>; 169 interrupt-controller; 170 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; 171 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 172 }; 173 174 cmt0: timer@ffca0000 { 175 compatible = "renesas,cmt-48-gen2"; 176 reg = <0 0xffca0000 0 0x1004>; 177 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&mstp1_clks R8A7794_CLK_CMT0>; 180 clock-names = "fck"; 181 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 182 183 renesas,channels-mask = <0x60>; 184 185 status = "disabled"; 186 }; 187 188 cmt1: timer@e6130000 { 189 compatible = "renesas,cmt-48-gen2"; 190 reg = <0 0xe6130000 0 0x1004>; 191 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&mstp3_clks R8A7794_CLK_CMT1>; 200 clock-names = "fck"; 201 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 202 203 renesas,channels-mask = <0xff>; 204 205 status = "disabled"; 206 }; 207 208 timer { 209 compatible = "arm,armv7-timer"; 210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 214 }; 215 216 irqc0: interrupt-controller@e61c0000 { 217 compatible = "renesas,irqc-r8a7794", "renesas,irqc"; 218 #interrupt-cells = <2>; 219 interrupt-controller; 220 reg = <0 0xe61c0000 0 0x200>; 221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&mstp4_clks R8A7794_CLK_IRQC>; 232 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 233 }; 234 235 pfc: pin-controller@e6060000 { 236 compatible = "renesas,pfc-r8a7794"; 237 reg = <0 0xe6060000 0 0x11c>; 238 }; 239 240 dmac0: dma-controller@e6700000 { 241 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 242 reg = <0 0xe6700000 0 0x20000>; 243 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 248 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 249 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 250 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 251 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 252 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 256 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 257 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 258 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-names = "error", 260 "ch0", "ch1", "ch2", "ch3", 261 "ch4", "ch5", "ch6", "ch7", 262 "ch8", "ch9", "ch10", "ch11", 263 "ch12", "ch13", "ch14"; 264 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; 265 clock-names = "fck"; 266 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 267 #dma-cells = <1>; 268 dma-channels = <15>; 269 }; 270 271 dmac1: dma-controller@e6720000 { 272 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 273 reg = <0 0xe6720000 0 0x20000>; 274 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 275 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 287 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "error", 291 "ch0", "ch1", "ch2", "ch3", 292 "ch4", "ch5", "ch6", "ch7", 293 "ch8", "ch9", "ch10", "ch11", 294 "ch12", "ch13", "ch14"; 295 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; 296 clock-names = "fck"; 297 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 298 #dma-cells = <1>; 299 dma-channels = <15>; 300 }; 301 302 audma0: dma-controller@ec700000 { 303 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 304 reg = <0 0xec700000 0 0x10000>; 305 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-names = "error", 320 "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", 321 "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", 322 "ch12"; 323 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; 324 clock-names = "fck"; 325 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 326 #dma-cells = <1>; 327 dma-channels = <13>; 328 }; 329 330 scifa0: serial@e6c40000 { 331 compatible = "renesas,scifa-r8a7794", 332 "renesas,rcar-gen2-scifa", "renesas,scifa"; 333 reg = <0 0xe6c40000 0 64>; 334 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; 336 clock-names = "fck"; 337 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 338 <&dmac1 0x21>, <&dmac1 0x22>; 339 dma-names = "tx", "rx", "tx", "rx"; 340 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 341 status = "disabled"; 342 }; 343 344 scifa1: serial@e6c50000 { 345 compatible = "renesas,scifa-r8a7794", 346 "renesas,rcar-gen2-scifa", "renesas,scifa"; 347 reg = <0 0xe6c50000 0 64>; 348 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; 350 clock-names = "fck"; 351 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 352 <&dmac1 0x25>, <&dmac1 0x26>; 353 dma-names = "tx", "rx", "tx", "rx"; 354 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 355 status = "disabled"; 356 }; 357 358 scifa2: serial@e6c60000 { 359 compatible = "renesas,scifa-r8a7794", 360 "renesas,rcar-gen2-scifa", "renesas,scifa"; 361 reg = <0 0xe6c60000 0 64>; 362 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; 364 clock-names = "fck"; 365 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 366 <&dmac1 0x27>, <&dmac1 0x28>; 367 dma-names = "tx", "rx", "tx", "rx"; 368 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 369 status = "disabled"; 370 }; 371 372 scifa3: serial@e6c70000 { 373 compatible = "renesas,scifa-r8a7794", 374 "renesas,rcar-gen2-scifa", "renesas,scifa"; 375 reg = <0 0xe6c70000 0 64>; 376 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; 378 clock-names = "fck"; 379 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 380 <&dmac1 0x1b>, <&dmac1 0x1c>; 381 dma-names = "tx", "rx", "tx", "rx"; 382 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 383 status = "disabled"; 384 }; 385 386 scifa4: serial@e6c78000 { 387 compatible = "renesas,scifa-r8a7794", 388 "renesas,rcar-gen2-scifa", "renesas,scifa"; 389 reg = <0 0xe6c78000 0 64>; 390 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; 392 clock-names = "fck"; 393 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 394 <&dmac1 0x1f>, <&dmac1 0x20>; 395 dma-names = "tx", "rx", "tx", "rx"; 396 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 397 status = "disabled"; 398 }; 399 400 scifa5: serial@e6c80000 { 401 compatible = "renesas,scifa-r8a7794", 402 "renesas,rcar-gen2-scifa", "renesas,scifa"; 403 reg = <0 0xe6c80000 0 64>; 404 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; 406 clock-names = "fck"; 407 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 408 <&dmac1 0x23>, <&dmac1 0x24>; 409 dma-names = "tx", "rx", "tx", "rx"; 410 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 411 status = "disabled"; 412 }; 413 414 scifb0: serial@e6c20000 { 415 compatible = "renesas,scifb-r8a7794", 416 "renesas,rcar-gen2-scifb", "renesas,scifb"; 417 reg = <0 0xe6c20000 0 0x100>; 418 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; 420 clock-names = "fck"; 421 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 422 <&dmac1 0x3d>, <&dmac1 0x3e>; 423 dma-names = "tx", "rx", "tx", "rx"; 424 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 425 status = "disabled"; 426 }; 427 428 scifb1: serial@e6c30000 { 429 compatible = "renesas,scifb-r8a7794", 430 "renesas,rcar-gen2-scifb", "renesas,scifb"; 431 reg = <0 0xe6c30000 0 0x100>; 432 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; 434 clock-names = "fck"; 435 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 436 <&dmac1 0x19>, <&dmac1 0x1a>; 437 dma-names = "tx", "rx", "tx", "rx"; 438 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 439 status = "disabled"; 440 }; 441 442 scifb2: serial@e6ce0000 { 443 compatible = "renesas,scifb-r8a7794", 444 "renesas,rcar-gen2-scifb", "renesas,scifb"; 445 reg = <0 0xe6ce0000 0 0x100>; 446 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; 448 clock-names = "fck"; 449 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 450 <&dmac1 0x1d>, <&dmac1 0x1e>; 451 dma-names = "tx", "rx", "tx", "rx"; 452 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 453 status = "disabled"; 454 }; 455 456 scif0: serial@e6e60000 { 457 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 458 "renesas,scif"; 459 reg = <0 0xe6e60000 0 64>; 460 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, 462 <&scif_clk>; 463 clock-names = "fck", "brg_int", "scif_clk"; 464 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 465 <&dmac1 0x29>, <&dmac1 0x2a>; 466 dma-names = "tx", "rx", "tx", "rx"; 467 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 468 status = "disabled"; 469 }; 470 471 scif1: serial@e6e68000 { 472 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 473 "renesas,scif"; 474 reg = <0 0xe6e68000 0 64>; 475 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, 477 <&scif_clk>; 478 clock-names = "fck", "brg_int", "scif_clk"; 479 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 480 <&dmac1 0x2d>, <&dmac1 0x2e>; 481 dma-names = "tx", "rx", "tx", "rx"; 482 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 483 status = "disabled"; 484 }; 485 486 scif2: serial@e6e58000 { 487 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 488 "renesas,scif"; 489 reg = <0 0xe6e58000 0 64>; 490 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, 492 <&scif_clk>; 493 clock-names = "fck", "brg_int", "scif_clk"; 494 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 495 <&dmac1 0x2b>, <&dmac1 0x2c>; 496 dma-names = "tx", "rx", "tx", "rx"; 497 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 498 status = "disabled"; 499 }; 500 501 scif3: serial@e6ea8000 { 502 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 503 "renesas,scif"; 504 reg = <0 0xe6ea8000 0 64>; 505 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, 507 <&scif_clk>; 508 clock-names = "fck", "brg_int", "scif_clk"; 509 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 510 <&dmac1 0x2f>, <&dmac1 0x30>; 511 dma-names = "tx", "rx", "tx", "rx"; 512 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 513 status = "disabled"; 514 }; 515 516 scif4: serial@e6ee0000 { 517 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 518 "renesas,scif"; 519 reg = <0 0xe6ee0000 0 64>; 520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, 522 <&scif_clk>; 523 clock-names = "fck", "brg_int", "scif_clk"; 524 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 525 <&dmac1 0xfb>, <&dmac1 0xfc>; 526 dma-names = "tx", "rx", "tx", "rx"; 527 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 528 status = "disabled"; 529 }; 530 531 scif5: serial@e6ee8000 { 532 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 533 "renesas,scif"; 534 reg = <0 0xe6ee8000 0 64>; 535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, 537 <&scif_clk>; 538 clock-names = "fck", "brg_int", "scif_clk"; 539 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 540 <&dmac1 0xfd>, <&dmac1 0xfe>; 541 dma-names = "tx", "rx", "tx", "rx"; 542 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 543 status = "disabled"; 544 }; 545 546 hscif0: serial@e62c0000 { 547 compatible = "renesas,hscif-r8a7794", 548 "renesas,rcar-gen2-hscif", "renesas,hscif"; 549 reg = <0 0xe62c0000 0 96>; 550 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, 552 <&scif_clk>; 553 clock-names = "fck", "brg_int", "scif_clk"; 554 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 555 <&dmac1 0x39>, <&dmac1 0x3a>; 556 dma-names = "tx", "rx", "tx", "rx"; 557 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 558 status = "disabled"; 559 }; 560 561 hscif1: serial@e62c8000 { 562 compatible = "renesas,hscif-r8a7794", 563 "renesas,rcar-gen2-hscif", "renesas,hscif"; 564 reg = <0 0xe62c8000 0 96>; 565 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, 567 <&scif_clk>; 568 clock-names = "fck", "brg_int", "scif_clk"; 569 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 570 <&dmac1 0x4d>, <&dmac1 0x4e>; 571 dma-names = "tx", "rx", "tx", "rx"; 572 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 573 status = "disabled"; 574 }; 575 576 hscif2: serial@e62d0000 { 577 compatible = "renesas,hscif-r8a7794", 578 "renesas,rcar-gen2-hscif", "renesas,hscif"; 579 reg = <0 0xe62d0000 0 96>; 580 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, 582 <&scif_clk>; 583 clock-names = "fck", "brg_int", "scif_clk"; 584 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 585 <&dmac1 0x3b>, <&dmac1 0x3c>; 586 dma-names = "tx", "rx", "tx", "rx"; 587 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 588 status = "disabled"; 589 }; 590 591 icram0: sram@e63a0000 { 592 compatible = "mmio-sram"; 593 reg = <0 0xe63a0000 0 0x12000>; 594 }; 595 596 icram1: sram@e63c0000 { 597 compatible = "mmio-sram"; 598 reg = <0 0xe63c0000 0 0x1000>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0 0 0xe63c0000 0x1000>; 602 603 smp-sram@0 { 604 compatible = "renesas,smp-sram"; 605 reg = <0 0x10>; 606 }; 607 }; 608 609 ether: ethernet@ee700000 { 610 compatible = "renesas,ether-r8a7794"; 611 reg = <0 0xee700000 0 0x400>; 612 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&mstp8_clks R8A7794_CLK_ETHER>; 614 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 615 phy-mode = "rmii"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 avb: ethernet@e6800000 { 622 compatible = "renesas,etheravb-r8a7794", 623 "renesas,etheravb-rcar-gen2"; 624 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 625 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; 627 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 /* The memory map in the User's Manual maps the cores to bus numbers */ 634 i2c0: i2c@e6508000 { 635 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 636 reg = <0 0xe6508000 0 0x40>; 637 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&mstp9_clks R8A7794_CLK_I2C0>; 639 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 i2c-scl-internal-delay-ns = <6>; 643 status = "disabled"; 644 }; 645 646 i2c1: i2c@e6518000 { 647 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 648 reg = <0 0xe6518000 0 0x40>; 649 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&mstp9_clks R8A7794_CLK_I2C1>; 651 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 i2c-scl-internal-delay-ns = <6>; 655 status = "disabled"; 656 }; 657 658 i2c2: i2c@e6530000 { 659 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 660 reg = <0 0xe6530000 0 0x40>; 661 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&mstp9_clks R8A7794_CLK_I2C2>; 663 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 i2c-scl-internal-delay-ns = <6>; 667 status = "disabled"; 668 }; 669 670 i2c3: i2c@e6540000 { 671 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 672 reg = <0 0xe6540000 0 0x40>; 673 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&mstp9_clks R8A7794_CLK_I2C3>; 675 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 i2c-scl-internal-delay-ns = <6>; 679 status = "disabled"; 680 }; 681 682 i2c4: i2c@e6520000 { 683 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 684 reg = <0 0xe6520000 0 0x40>; 685 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&mstp9_clks R8A7794_CLK_I2C4>; 687 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 i2c-scl-internal-delay-ns = <6>; 691 status = "disabled"; 692 }; 693 694 i2c5: i2c@e6528000 { 695 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 696 reg = <0 0xe6528000 0 0x40>; 697 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&mstp9_clks R8A7794_CLK_I2C5>; 699 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 i2c-scl-internal-delay-ns = <6>; 703 status = "disabled"; 704 }; 705 706 i2c6: i2c@e6500000 { 707 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", 708 "renesas,rmobile-iic"; 709 reg = <0 0xe6500000 0 0x425>; 710 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&mstp3_clks R8A7794_CLK_IIC0>; 712 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 713 <&dmac1 0x61>, <&dmac1 0x62>; 714 dma-names = "tx", "rx", "tx", "rx"; 715 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 i2c7: i2c@e6510000 { 722 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", 723 "renesas,rmobile-iic"; 724 reg = <0 0xe6510000 0 0x425>; 725 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&mstp3_clks R8A7794_CLK_IIC1>; 727 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 728 <&dmac1 0x65>, <&dmac1 0x66>; 729 dma-names = "tx", "rx", "tx", "rx"; 730 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 mmcif0: mmc@ee200000 { 737 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; 738 reg = <0 0xee200000 0 0x80>; 739 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; 741 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 742 <&dmac1 0xd1>, <&dmac1 0xd2>; 743 dma-names = "tx", "rx", "tx", "rx"; 744 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 745 reg-io-width = <4>; 746 status = "disabled"; 747 }; 748 749 sdhi0: sd@ee100000 { 750 compatible = "renesas,sdhi-r8a7794"; 751 reg = <0 0xee100000 0 0x328>; 752 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; 754 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 755 <&dmac1 0xcd>, <&dmac1 0xce>; 756 dma-names = "tx", "rx", "tx", "rx"; 757 max-frequency = <195000000>; 758 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 759 status = "disabled"; 760 }; 761 762 sdhi1: sd@ee140000 { 763 compatible = "renesas,sdhi-r8a7794"; 764 reg = <0 0xee140000 0 0x100>; 765 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; 767 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 768 <&dmac1 0xc1>, <&dmac1 0xc2>; 769 dma-names = "tx", "rx", "tx", "rx"; 770 max-frequency = <97500000>; 771 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 772 status = "disabled"; 773 }; 774 775 sdhi2: sd@ee160000 { 776 compatible = "renesas,sdhi-r8a7794"; 777 reg = <0 0xee160000 0 0x100>; 778 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; 780 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 781 <&dmac1 0xd3>, <&dmac1 0xd4>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 max-frequency = <97500000>; 784 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 785 status = "disabled"; 786 }; 787 788 qspi: spi@e6b10000 { 789 compatible = "renesas,qspi-r8a7794", "renesas,qspi"; 790 reg = <0 0xe6b10000 0 0x2c>; 791 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; 793 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 794 <&dmac1 0x17>, <&dmac1 0x18>; 795 dma-names = "tx", "rx", "tx", "rx"; 796 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 797 num-cs = <1>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 status = "disabled"; 801 }; 802 803 vin0: video@e6ef0000 { 804 compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; 805 reg = <0 0xe6ef0000 0 0x1000>; 806 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&mstp8_clks R8A7794_CLK_VIN0>; 808 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 809 status = "disabled"; 810 }; 811 812 vin1: video@e6ef1000 { 813 compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; 814 reg = <0 0xe6ef1000 0 0x1000>; 815 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&mstp8_clks R8A7794_CLK_VIN1>; 817 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 818 status = "disabled"; 819 }; 820 821 pci0: pci@ee090000 { 822 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; 823 device_type = "pci"; 824 reg = <0 0xee090000 0 0xc00>, 825 <0 0xee080000 0 0x1100>; 826 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&mstp7_clks R8A7794_CLK_EHCI>; 828 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 829 status = "disabled"; 830 831 bus-range = <0 0>; 832 #address-cells = <3>; 833 #size-cells = <2>; 834 #interrupt-cells = <1>; 835 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 836 interrupt-map-mask = <0xff00 0 0 0x7>; 837 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 838 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 839 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 840 841 usb@1,0 { 842 reg = <0x800 0 0 0 0>; 843 phys = <&usb0 0>; 844 phy-names = "usb"; 845 }; 846 847 usb@2,0 { 848 reg = <0x1000 0 0 0 0>; 849 phys = <&usb0 0>; 850 phy-names = "usb"; 851 }; 852 }; 853 854 pci1: pci@ee0d0000 { 855 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; 856 device_type = "pci"; 857 reg = <0 0xee0d0000 0 0xc00>, 858 <0 0xee0c0000 0 0x1100>; 859 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&mstp7_clks R8A7794_CLK_EHCI>; 861 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 862 status = "disabled"; 863 864 bus-range = <1 1>; 865 #address-cells = <3>; 866 #size-cells = <2>; 867 #interrupt-cells = <1>; 868 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 869 interrupt-map-mask = <0xff00 0 0 0x7>; 870 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 871 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 872 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 873 874 usb@1,0 { 875 reg = <0x10800 0 0 0 0>; 876 phys = <&usb2 0>; 877 phy-names = "usb"; 878 }; 879 880 usb@2,0 { 881 reg = <0x11000 0 0 0 0>; 882 phys = <&usb2 0>; 883 phy-names = "usb"; 884 }; 885 }; 886 887 hsusb: usb@e6590000 { 888 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; 889 reg = <0 0xe6590000 0 0x100>; 890 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; 892 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 893 renesas,buswait = <4>; 894 phys = <&usb0 1>; 895 phy-names = "usb"; 896 status = "disabled"; 897 }; 898 899 usbphy: usb-phy@e6590100 { 900 compatible = "renesas,usb-phy-r8a7794", 901 "renesas,rcar-gen2-usb-phy"; 902 reg = <0 0xe6590100 0 0x100>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; 906 clock-names = "usbhs"; 907 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 908 status = "disabled"; 909 910 usb0: usb-channel@0 { 911 reg = <0>; 912 #phy-cells = <1>; 913 }; 914 usb2: usb-channel@2 { 915 reg = <2>; 916 #phy-cells = <1>; 917 }; 918 }; 919 920 vsp1@fe928000 { 921 compatible = "renesas,vsp1"; 922 reg = <0 0xfe928000 0 0x8000>; 923 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; 925 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 926 }; 927 928 vsp1@fe930000 { 929 compatible = "renesas,vsp1"; 930 reg = <0 0xfe930000 0 0x8000>; 931 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; 933 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 934 }; 935 936 du: display@feb00000 { 937 compatible = "renesas,du-r8a7794"; 938 reg = <0 0xfeb00000 0 0x40000>; 939 reg-names = "du"; 940 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&mstp7_clks R8A7794_CLK_DU0>, 943 <&mstp7_clks R8A7794_CLK_DU1>; 944 clock-names = "du.0", "du.1"; 945 status = "disabled"; 946 947 ports { 948 #address-cells = <1>; 949 #size-cells = <0>; 950 951 port@0 { 952 reg = <0>; 953 du_out_rgb0: endpoint { 954 }; 955 }; 956 port@1 { 957 reg = <1>; 958 du_out_rgb1: endpoint { 959 }; 960 }; 961 }; 962 }; 963 964 can0: can@e6e80000 { 965 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; 966 reg = <0 0xe6e80000 0 0x1000>; 967 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, 969 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; 970 clock-names = "clkp1", "clkp2", "can_clk"; 971 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 972 status = "disabled"; 973 }; 974 975 can1: can@e6e88000 { 976 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; 977 reg = <0 0xe6e88000 0 0x1000>; 978 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, 980 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; 981 clock-names = "clkp1", "clkp2", "can_clk"; 982 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 983 status = "disabled"; 984 }; 985 986 clocks { 987 #address-cells = <2>; 988 #size-cells = <2>; 989 ranges; 990 991 /* External root clock */ 992 extal_clk: extal { 993 compatible = "fixed-clock"; 994 #clock-cells = <0>; 995 /* This value must be overriden by the board. */ 996 clock-frequency = <0>; 997 }; 998 999 /* External USB clock - can be overridden by the board */ 1000 usb_extal_clk: usb_extal { 1001 compatible = "fixed-clock"; 1002 #clock-cells = <0>; 1003 clock-frequency = <48000000>; 1004 }; 1005 1006 /* External CAN clock */ 1007 can_clk: can { 1008 compatible = "fixed-clock"; 1009 #clock-cells = <0>; 1010 /* This value must be overridden by the board. */ 1011 clock-frequency = <0>; 1012 }; 1013 1014 /* External SCIF clock */ 1015 scif_clk: scif { 1016 compatible = "fixed-clock"; 1017 #clock-cells = <0>; 1018 /* This value must be overridden by the board. */ 1019 clock-frequency = <0>; 1020 }; 1021 1022 /* 1023 * The external audio clocks are configured as 0 Hz fixed 1024 * frequency clocks by default. Boards that provide audio 1025 * clocks should override them. 1026 */ 1027 audio_clka: audio_clka { 1028 compatible = "fixed-clock"; 1029 #clock-cells = <0>; 1030 clock-frequency = <0>; 1031 }; 1032 audio_clkb: audio_clkb { 1033 compatible = "fixed-clock"; 1034 #clock-cells = <0>; 1035 clock-frequency = <0>; 1036 }; 1037 audio_clkc: audio_clkc { 1038 compatible = "fixed-clock"; 1039 #clock-cells = <0>; 1040 clock-frequency = <0>; 1041 }; 1042 1043 /* Special CPG clocks */ 1044 cpg_clocks: cpg_clocks@e6150000 { 1045 compatible = "renesas,r8a7794-cpg-clocks", 1046 "renesas,rcar-gen2-cpg-clocks"; 1047 reg = <0 0xe6150000 0 0x1000>; 1048 clocks = <&extal_clk &usb_extal_clk>; 1049 #clock-cells = <1>; 1050 clock-output-names = "main", "pll0", "pll1", "pll3", 1051 "lb", "qspi", "sdh", "sd0", "rcan"; 1052 #power-domain-cells = <0>; 1053 }; 1054 /* Variable factor clocks */ 1055 sd2_clk: sd2@e6150078 { 1056 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 1057 reg = <0 0xe6150078 0 4>; 1058 clocks = <&pll1_div2_clk>; 1059 #clock-cells = <0>; 1060 }; 1061 sd3_clk: sd3@e615026c { 1062 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 1063 reg = <0 0xe615026c 0 4>; 1064 clocks = <&pll1_div2_clk>; 1065 #clock-cells = <0>; 1066 }; 1067 mmc0_clk: mmc0@e6150240 { 1068 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 1069 reg = <0 0xe6150240 0 4>; 1070 clocks = <&pll1_div2_clk>; 1071 #clock-cells = <0>; 1072 }; 1073 1074 /* Fixed factor clocks */ 1075 pll1_div2_clk: pll1_div2 { 1076 compatible = "fixed-factor-clock"; 1077 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1078 #clock-cells = <0>; 1079 clock-div = <2>; 1080 clock-mult = <1>; 1081 }; 1082 z2_clk: z2 { 1083 compatible = "fixed-factor-clock"; 1084 clocks = <&cpg_clocks R8A7794_CLK_PLL0>; 1085 #clock-cells = <0>; 1086 clock-div = <1>; 1087 clock-mult = <1>; 1088 }; 1089 zg_clk: zg { 1090 compatible = "fixed-factor-clock"; 1091 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1092 #clock-cells = <0>; 1093 clock-div = <6>; 1094 clock-mult = <1>; 1095 }; 1096 zx_clk: zx { 1097 compatible = "fixed-factor-clock"; 1098 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1099 #clock-cells = <0>; 1100 clock-div = <3>; 1101 clock-mult = <1>; 1102 }; 1103 zs_clk: zs { 1104 compatible = "fixed-factor-clock"; 1105 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1106 #clock-cells = <0>; 1107 clock-div = <6>; 1108 clock-mult = <1>; 1109 }; 1110 hp_clk: hp { 1111 compatible = "fixed-factor-clock"; 1112 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1113 #clock-cells = <0>; 1114 clock-div = <12>; 1115 clock-mult = <1>; 1116 }; 1117 i_clk: i { 1118 compatible = "fixed-factor-clock"; 1119 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1120 #clock-cells = <0>; 1121 clock-div = <2>; 1122 clock-mult = <1>; 1123 }; 1124 b_clk: b { 1125 compatible = "fixed-factor-clock"; 1126 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1127 #clock-cells = <0>; 1128 clock-div = <12>; 1129 clock-mult = <1>; 1130 }; 1131 p_clk: p { 1132 compatible = "fixed-factor-clock"; 1133 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1134 #clock-cells = <0>; 1135 clock-div = <24>; 1136 clock-mult = <1>; 1137 }; 1138 cl_clk: cl { 1139 compatible = "fixed-factor-clock"; 1140 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1141 #clock-cells = <0>; 1142 clock-div = <48>; 1143 clock-mult = <1>; 1144 }; 1145 m2_clk: m2 { 1146 compatible = "fixed-factor-clock"; 1147 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1148 #clock-cells = <0>; 1149 clock-div = <8>; 1150 clock-mult = <1>; 1151 }; 1152 rclk_clk: rclk { 1153 compatible = "fixed-factor-clock"; 1154 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1155 #clock-cells = <0>; 1156 clock-div = <(48 * 1024)>; 1157 clock-mult = <1>; 1158 }; 1159 oscclk_clk: oscclk { 1160 compatible = "fixed-factor-clock"; 1161 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1162 #clock-cells = <0>; 1163 clock-div = <(12 * 1024)>; 1164 clock-mult = <1>; 1165 }; 1166 zb3_clk: zb3 { 1167 compatible = "fixed-factor-clock"; 1168 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 1169 #clock-cells = <0>; 1170 clock-div = <4>; 1171 clock-mult = <1>; 1172 }; 1173 zb3d2_clk: zb3d2 { 1174 compatible = "fixed-factor-clock"; 1175 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 1176 #clock-cells = <0>; 1177 clock-div = <8>; 1178 clock-mult = <1>; 1179 }; 1180 ddr_clk: ddr { 1181 compatible = "fixed-factor-clock"; 1182 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 1183 #clock-cells = <0>; 1184 clock-div = <8>; 1185 clock-mult = <1>; 1186 }; 1187 mp_clk: mp { 1188 compatible = "fixed-factor-clock"; 1189 clocks = <&pll1_div2_clk>; 1190 #clock-cells = <0>; 1191 clock-div = <15>; 1192 clock-mult = <1>; 1193 }; 1194 cp_clk: cp { 1195 compatible = "fixed-factor-clock"; 1196 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 1197 #clock-cells = <0>; 1198 clock-div = <48>; 1199 clock-mult = <1>; 1200 }; 1201 1202 acp_clk: acp { 1203 compatible = "fixed-factor-clock"; 1204 clocks = <&extal_clk>; 1205 #clock-cells = <0>; 1206 clock-div = <2>; 1207 clock-mult = <1>; 1208 }; 1209 1210 /* Gate clocks */ 1211 mstp0_clks: mstp0_clks@e6150130 { 1212 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1213 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1214 clocks = <&mp_clk>; 1215 #clock-cells = <1>; 1216 clock-indices = <R8A7794_CLK_MSIOF0>; 1217 clock-output-names = "msiof0"; 1218 }; 1219 mstp1_clks: mstp1_clks@e6150134 { 1220 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1221 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1222 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, 1223 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 1224 <&zs_clk>, <&zs_clk>; 1225 #clock-cells = <1>; 1226 clock-indices = < 1227 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 1228 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 1229 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 1230 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S 1231 >; 1232 clock-output-names = 1233 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", 1234 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; 1235 }; 1236 mstp2_clks: mstp2_clks@e6150138 { 1237 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1238 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 1239 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 1240 <&mp_clk>, <&mp_clk>, <&mp_clk>, 1241 <&zs_clk>, <&zs_clk>; 1242 #clock-cells = <1>; 1243 clock-indices = < 1244 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 1245 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 1246 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 1247 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 1248 >; 1249 clock-output-names = 1250 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 1251 "scifb1", "msiof1", "scifb2", 1252 "sys-dmac1", "sys-dmac0"; 1253 }; 1254 mstp3_clks: mstp3_clks@e615013c { 1255 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1256 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1257 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, 1258 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, 1259 <&hp_clk>, <&hp_clk>; 1260 #clock-cells = <1>; 1261 clock-indices = < 1262 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 1263 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 1264 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 1265 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 1266 >; 1267 clock-output-names = 1268 "sdhi2", "sdhi1", "sdhi0", 1269 "mmcif0", "i2c6", "i2c7", 1270 "cmt1", "usbdmac0", "usbdmac1"; 1271 }; 1272 mstp4_clks: mstp4_clks@e6150140 { 1273 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1274 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 1275 clocks = <&cp_clk>, <&zs_clk>; 1276 #clock-cells = <1>; 1277 clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>; 1278 clock-output-names = "irqc", "intc-sys"; 1279 }; 1280 mstp5_clks: mstp5_clks@e6150144 { 1281 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1282 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1283 clocks = <&hp_clk>, <&p_clk>; 1284 #clock-cells = <1>; 1285 clock-indices = <R8A7794_CLK_AUDIO_DMAC0 1286 R8A7794_CLK_PWM>; 1287 clock-output-names = "audmac0", "pwm"; 1288 }; 1289 mstp7_clks: mstp7_clks@e615014c { 1290 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1291 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 1292 clocks = <&mp_clk>, <&hp_clk>, 1293 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 1294 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1295 <&zx_clk>, <&zx_clk>; 1296 #clock-cells = <1>; 1297 clock-indices = < 1298 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB 1299 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 1300 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 1301 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 1302 R8A7794_CLK_SCIF0 1303 R8A7794_CLK_DU1 R8A7794_CLK_DU0 1304 >; 1305 clock-output-names = 1306 "ehci", "hsusb", 1307 "hscif2", "scif5", "scif4", "hscif1", "hscif0", 1308 "scif3", "scif2", "scif1", "scif0", 1309 "du1", "du0"; 1310 }; 1311 mstp8_clks: mstp8_clks@e6150990 { 1312 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1313 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1314 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; 1315 #clock-cells = <1>; 1316 clock-indices = < 1317 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 1318 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER 1319 >; 1320 clock-output-names = 1321 "vin1", "vin0", "etheravb", "ether"; 1322 }; 1323 mstp9_clks: mstp9_clks@e6150994 { 1324 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1325 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1326 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1327 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, 1328 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, 1329 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1330 <&hp_clk>, <&hp_clk>; 1331 #clock-cells = <1>; 1332 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 1333 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 1334 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 1335 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 1336 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD 1337 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 1338 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 1339 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; 1340 clock-output-names = 1341 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", 1342 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", 1343 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; 1344 }; 1345 mstp10_clks: mstp10_clks@e6150998 { 1346 compatible = "renesas,r8a7794-mstp-clocks", 1347 "renesas,cpg-mstp-clocks"; 1348 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; 1349 clocks = <&p_clk>, 1350 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1351 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1352 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1353 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1354 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1355 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1356 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1357 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1358 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1359 <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1360 <&p_clk>, 1361 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1362 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1363 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1364 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1365 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1366 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1367 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1368 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1369 <&mstp10_clks R8A7794_CLK_SCU_ALL>, 1370 <&mstp10_clks R8A7794_CLK_SCU_ALL>; 1371 #clock-cells = <1>; 1372 clock-indices = <R8A7794_CLK_SSI_ALL 1373 R8A7794_CLK_SSI9 R8A7794_CLK_SSI8 1374 R8A7794_CLK_SSI7 R8A7794_CLK_SSI6 1375 R8A7794_CLK_SSI5 R8A7794_CLK_SSI4 1376 R8A7794_CLK_SSI3 R8A7794_CLK_SSI2 1377 R8A7794_CLK_SSI1 R8A7794_CLK_SSI0 1378 R8A7794_CLK_SCU_ALL 1379 R8A7794_CLK_SCU_DVC1 1380 R8A7794_CLK_SCU_DVC0 1381 R8A7794_CLK_SCU_CTU1_MIX1 1382 R8A7794_CLK_SCU_CTU0_MIX0 1383 R8A7794_CLK_SCU_SRC6 1384 R8A7794_CLK_SCU_SRC5 1385 R8A7794_CLK_SCU_SRC4 1386 R8A7794_CLK_SCU_SRC3 1387 R8A7794_CLK_SCU_SRC2 1388 R8A7794_CLK_SCU_SRC1>; 1389 clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", 1390 "ssi6", "ssi5", "ssi4", "ssi3", 1391 "ssi2", "ssi1", "ssi0", 1392 "scu-all", "scu-dvc1", "scu-dvc0", 1393 "scu-ctu1-mix1", "scu-ctu0-mix0", 1394 "scu-src6", "scu-src5", "scu-src4", 1395 "scu-src3", "scu-src2", "scu-src1"; 1396 }; 1397 mstp11_clks: mstp11_clks@e615099c { 1398 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 1399 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1400 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1401 #clock-cells = <1>; 1402 clock-indices = < 1403 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 1404 >; 1405 clock-output-names = "scifa3", "scifa4", "scifa5"; 1406 }; 1407 }; 1408 1409 rst: reset-controller@e6160000 { 1410 compatible = "renesas,r8a7794-rst"; 1411 reg = <0 0xe6160000 0 0x0100>; 1412 }; 1413 1414 prr: chipid@ff000044 { 1415 compatible = "renesas,prr"; 1416 reg = <0 0xff000044 0 4>; 1417 }; 1418 1419 sysc: system-controller@e6180000 { 1420 compatible = "renesas,r8a7794-sysc"; 1421 reg = <0 0xe6180000 0 0x0200>; 1422 #power-domain-cells = <1>; 1423 }; 1424 1425 ipmmu_sy0: mmu@e6280000 { 1426 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1427 reg = <0 0xe6280000 0 0x1000>; 1428 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1430 #iommu-cells = <1>; 1431 status = "disabled"; 1432 }; 1433 1434 ipmmu_sy1: mmu@e6290000 { 1435 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1436 reg = <0 0xe6290000 0 0x1000>; 1437 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1438 #iommu-cells = <1>; 1439 status = "disabled"; 1440 }; 1441 1442 ipmmu_ds: mmu@e6740000 { 1443 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1444 reg = <0 0xe6740000 0 0x1000>; 1445 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1447 #iommu-cells = <1>; 1448 status = "disabled"; 1449 }; 1450 1451 ipmmu_mp: mmu@ec680000 { 1452 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1453 reg = <0 0xec680000 0 0x1000>; 1454 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1455 #iommu-cells = <1>; 1456 status = "disabled"; 1457 }; 1458 1459 ipmmu_mx: mmu@fe951000 { 1460 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1461 reg = <0 0xfe951000 0 0x1000>; 1462 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1464 #iommu-cells = <1>; 1465 status = "disabled"; 1466 }; 1467 1468 ipmmu_gp: mmu@e62a0000 { 1469 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1470 reg = <0 0xe62a0000 0 0x1000>; 1471 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1473 #iommu-cells = <1>; 1474 status = "disabled"; 1475 }; 1476 1477 rcar_sound: sound@ec500000 { 1478 /* 1479 * #sound-dai-cells is required 1480 * 1481 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1482 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1483 */ 1484 compatible = "renesas,rcar_sound-r8a7794", 1485 "renesas,rcar_sound-gen2"; 1486 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1487 <0 0xec5a0000 0 0x100>, /* ADG */ 1488 <0 0xec540000 0 0x1000>, /* SSIU */ 1489 <0 0xec541000 0 0x280>, /* SSI */ 1490 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ 1491 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1492 1493 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, 1494 <&mstp10_clks R8A7794_CLK_SSI9>, 1495 <&mstp10_clks R8A7794_CLK_SSI8>, 1496 <&mstp10_clks R8A7794_CLK_SSI7>, 1497 <&mstp10_clks R8A7794_CLK_SSI6>, 1498 <&mstp10_clks R8A7794_CLK_SSI5>, 1499 <&mstp10_clks R8A7794_CLK_SSI4>, 1500 <&mstp10_clks R8A7794_CLK_SSI3>, 1501 <&mstp10_clks R8A7794_CLK_SSI2>, 1502 <&mstp10_clks R8A7794_CLK_SSI1>, 1503 <&mstp10_clks R8A7794_CLK_SSI0>, 1504 <&mstp10_clks R8A7794_CLK_SCU_SRC6>, 1505 <&mstp10_clks R8A7794_CLK_SCU_SRC5>, 1506 <&mstp10_clks R8A7794_CLK_SCU_SRC4>, 1507 <&mstp10_clks R8A7794_CLK_SCU_SRC3>, 1508 <&mstp10_clks R8A7794_CLK_SCU_SRC2>, 1509 <&mstp10_clks R8A7794_CLK_SCU_SRC1>, 1510 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, 1511 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, 1512 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, 1513 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, 1514 <&mstp10_clks R8A7794_CLK_SCU_DVC0>, 1515 <&mstp10_clks R8A7794_CLK_SCU_DVC1>, 1516 <&audio_clka>, <&audio_clkb>, <&audio_clkc>, 1517 <&m2_clk>; 1518 clock-names = "ssi-all", 1519 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1520 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1521 "src.6", "src.5", "src.4", "src.3", "src.2", 1522 "src.1", 1523 "ctu.0", "ctu.1", 1524 "mix.0", "mix.1", 1525 "dvc.0", "dvc.1", 1526 "clk_a", "clk_b", "clk_c", "clk_i"; 1527 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 1528 1529 status = "disabled"; 1530 1531 rcar_sound,dvc { 1532 dvc0: dvc-0 { 1533 dmas = <&audma0 0xbc>; 1534 dma-names = "tx"; 1535 }; 1536 dvc1: dvc-1 { 1537 dmas = <&audma0 0xbe>; 1538 dma-names = "tx"; 1539 }; 1540 }; 1541 1542 rcar_sound,mix { 1543 mix0: mix-0 { }; 1544 mix1: mix-1 { }; 1545 }; 1546 1547 rcar_sound,ctu { 1548 ctu00: ctu-0 { }; 1549 ctu01: ctu-1 { }; 1550 ctu02: ctu-2 { }; 1551 ctu03: ctu-3 { }; 1552 ctu10: ctu-4 { }; 1553 ctu11: ctu-5 { }; 1554 ctu12: ctu-6 { }; 1555 ctu13: ctu-7 { }; 1556 }; 1557 1558 rcar_sound,src { 1559 src-0 { 1560 status = "disabled"; 1561 }; 1562 src1: src-1 { 1563 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1564 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1565 dma-names = "rx", "tx"; 1566 }; 1567 src2: src-2 { 1568 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1569 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1570 dma-names = "rx", "tx"; 1571 }; 1572 src3: src-3 { 1573 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1574 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1575 dma-names = "rx", "tx"; 1576 }; 1577 src4: src-4 { 1578 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1579 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1580 dma-names = "rx", "tx"; 1581 }; 1582 src5: src-5 { 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1584 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1585 dma-names = "rx", "tx"; 1586 }; 1587 src6: src-6 { 1588 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1589 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1590 dma-names = "rx", "tx"; 1591 }; 1592 }; 1593 1594 rcar_sound,ssi { 1595 ssi0: ssi-0 { 1596 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1597 dmas = <&audma0 0x01>, <&audma0 0x02>, 1598 <&audma0 0x15>, <&audma0 0x16>; 1599 dma-names = "rx", "tx", "rxu", "txu"; 1600 }; 1601 ssi1: ssi-1 { 1602 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1603 dmas = <&audma0 0x03>, <&audma0 0x04>, 1604 <&audma0 0x49>, <&audma0 0x4a>; 1605 dma-names = "rx", "tx", "rxu", "txu"; 1606 }; 1607 ssi2: ssi-2 { 1608 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1609 dmas = <&audma0 0x05>, <&audma0 0x06>, 1610 <&audma0 0x63>, <&audma0 0x64>; 1611 dma-names = "rx", "tx", "rxu", "txu"; 1612 }; 1613 ssi3: ssi-3 { 1614 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1615 dmas = <&audma0 0x07>, <&audma0 0x08>, 1616 <&audma0 0x6f>, <&audma0 0x70>; 1617 dma-names = "rx", "tx", "rxu", "txu"; 1618 }; 1619 ssi4: ssi-4 { 1620 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1621 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1622 <&audma0 0x71>, <&audma0 0x72>; 1623 dma-names = "rx", "tx", "rxu", "txu"; 1624 }; 1625 ssi5: ssi-5 { 1626 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1627 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1628 <&audma0 0x73>, <&audma0 0x74>; 1629 dma-names = "rx", "tx", "rxu", "txu"; 1630 }; 1631 ssi6: ssi-6 { 1632 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1633 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1634 <&audma0 0x75>, <&audma0 0x76>; 1635 dma-names = "rx", "tx", "rxu", "txu"; 1636 }; 1637 ssi7: ssi-7 { 1638 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1639 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1640 <&audma0 0x79>, <&audma0 0x7a>; 1641 dma-names = "rx", "tx", "rxu", "txu"; 1642 }; 1643 ssi8: ssi-8 { 1644 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1645 dmas = <&audma0 0x11>, <&audma0 0x12>, 1646 <&audma0 0x7b>, <&audma0 0x7c>; 1647 dma-names = "rx", "tx", "rxu", "txu"; 1648 }; 1649 ssi9: ssi-9 { 1650 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1651 dmas = <&audma0 0x13>, <&audma0 0x14>, 1652 <&audma0 0x7d>, <&audma0 0x7e>; 1653 dma-names = "rx", "tx", "rxu", "txu"; 1654 }; 1655 }; 1656 }; 1657 }; 1658
Indexes created Wed Oct 29 06:09:47 GMT 2025