r8a7794.dtsi revision 1.1.1.4
1 /* 2 * Device Tree Source for the r8a7794 SoC 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Ulrich Hecht 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 #include <dt-bindings/clock/r8a7794-cpg-mssr.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/interrupt-controller/irq.h> 15 #include <dt-bindings/power/r8a7794-sysc.h> 16 17 / { 18 compatible = "renesas,r8a7794"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 spi0 = &qspi; 33 vin0 = &vin0; 34 vin1 = &vin1; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a7"; 44 reg = <0>; 45 clock-frequency = <1000000000>; 46 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; 47 power-domains = <&sysc R8A7794_PD_CA7_CPU0>; 48 next-level-cache = <&L2_CA7>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <1>; 55 clock-frequency = <1000000000>; 56 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; 57 power-domains = <&sysc R8A7794_PD_CA7_CPU1>; 58 next-level-cache = <&L2_CA7>; 59 }; 60 61 L2_CA7: cache-controller-0 { 62 compatible = "cache"; 63 power-domains = <&sysc R8A7794_PD_CA7_SCU>; 64 cache-unified; 65 cache-level = <2>; 66 }; 67 }; 68 69 gic: interrupt-controller@f1001000 { 70 compatible = "arm,gic-400"; 71 #interrupt-cells = <3>; 72 #address-cells = <0>; 73 interrupt-controller; 74 reg = <0 0xf1001000 0 0x1000>, 75 <0 0xf1002000 0 0x2000>, 76 <0 0xf1004000 0 0x2000>, 77 <0 0xf1006000 0 0x2000>; 78 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 79 clocks = <&cpg CPG_MOD 408>; 80 clock-names = "clk"; 81 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 82 resets = <&cpg 408>; 83 }; 84 85 gpio0: gpio@e6050000 { 86 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 87 reg = <0 0xe6050000 0 0x50>; 88 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 89 #gpio-cells = <2>; 90 gpio-controller; 91 gpio-ranges = <&pfc 0 0 32>; 92 #interrupt-cells = <2>; 93 interrupt-controller; 94 clocks = <&cpg CPG_MOD 912>; 95 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 96 resets = <&cpg 912>; 97 }; 98 99 gpio1: gpio@e6051000 { 100 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 101 reg = <0 0xe6051000 0 0x50>; 102 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 103 #gpio-cells = <2>; 104 gpio-controller; 105 gpio-ranges = <&pfc 0 32 26>; 106 #interrupt-cells = <2>; 107 interrupt-controller; 108 clocks = <&cpg CPG_MOD 911>; 109 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 110 resets = <&cpg 911>; 111 }; 112 113 gpio2: gpio@e6052000 { 114 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 115 reg = <0 0xe6052000 0 0x50>; 116 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 117 #gpio-cells = <2>; 118 gpio-controller; 119 gpio-ranges = <&pfc 0 64 32>; 120 #interrupt-cells = <2>; 121 interrupt-controller; 122 clocks = <&cpg CPG_MOD 910>; 123 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 124 resets = <&cpg 910>; 125 }; 126 127 gpio3: gpio@e6053000 { 128 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 129 reg = <0 0xe6053000 0 0x50>; 130 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 131 #gpio-cells = <2>; 132 gpio-controller; 133 gpio-ranges = <&pfc 0 96 32>; 134 #interrupt-cells = <2>; 135 interrupt-controller; 136 clocks = <&cpg CPG_MOD 909>; 137 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 138 resets = <&cpg 909>; 139 }; 140 141 gpio4: gpio@e6054000 { 142 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 143 reg = <0 0xe6054000 0 0x50>; 144 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 145 #gpio-cells = <2>; 146 gpio-controller; 147 gpio-ranges = <&pfc 0 128 32>; 148 #interrupt-cells = <2>; 149 interrupt-controller; 150 clocks = <&cpg CPG_MOD 908>; 151 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 152 resets = <&cpg 908>; 153 }; 154 155 gpio5: gpio@e6055000 { 156 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 157 reg = <0 0xe6055000 0 0x50>; 158 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 159 #gpio-cells = <2>; 160 gpio-controller; 161 gpio-ranges = <&pfc 0 160 28>; 162 #interrupt-cells = <2>; 163 interrupt-controller; 164 clocks = <&cpg CPG_MOD 907>; 165 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 166 resets = <&cpg 907>; 167 }; 168 169 gpio6: gpio@e6055400 { 170 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; 171 reg = <0 0xe6055400 0 0x50>; 172 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 173 #gpio-cells = <2>; 174 gpio-controller; 175 gpio-ranges = <&pfc 0 192 26>; 176 #interrupt-cells = <2>; 177 interrupt-controller; 178 clocks = <&cpg CPG_MOD 905>; 179 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 180 resets = <&cpg 905>; 181 }; 182 183 cmt0: timer@ffca0000 { 184 compatible = "renesas,cmt-48-gen2"; 185 reg = <0 0xffca0000 0 0x1004>; 186 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&cpg CPG_MOD 124>; 189 clock-names = "fck"; 190 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 191 resets = <&cpg 124>; 192 193 renesas,channels-mask = <0x60>; 194 195 status = "disabled"; 196 }; 197 198 cmt1: timer@e6130000 { 199 compatible = "renesas,cmt-48-gen2"; 200 reg = <0 0xe6130000 0 0x1004>; 201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&cpg CPG_MOD 329>; 210 clock-names = "fck"; 211 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 212 resets = <&cpg 329>; 213 214 renesas,channels-mask = <0xff>; 215 216 status = "disabled"; 217 }; 218 219 timer { 220 compatible = "arm,armv7-timer"; 221 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 222 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 224 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 225 }; 226 227 irqc0: interrupt-controller@e61c0000 { 228 compatible = "renesas,irqc-r8a7794", "renesas,irqc"; 229 #interrupt-cells = <2>; 230 interrupt-controller; 231 reg = <0 0xe61c0000 0 0x200>; 232 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cpg CPG_MOD 407>; 243 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 244 resets = <&cpg 407>; 245 }; 246 247 pfc: pin-controller@e6060000 { 248 compatible = "renesas,pfc-r8a7794"; 249 reg = <0 0xe6060000 0 0x11c>; 250 }; 251 252 dmac0: dma-controller@e6700000 { 253 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 254 reg = <0 0xe6700000 0 0x20000>; 255 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 256 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 257 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 258 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 259 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 260 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 261 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 262 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 263 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 264 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 265 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 266 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 267 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 268 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 269 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 270 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-names = "error", 272 "ch0", "ch1", "ch2", "ch3", 273 "ch4", "ch5", "ch6", "ch7", 274 "ch8", "ch9", "ch10", "ch11", 275 "ch12", "ch13", "ch14"; 276 clocks = <&cpg CPG_MOD 219>; 277 clock-names = "fck"; 278 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 279 resets = <&cpg 219>; 280 #dma-cells = <1>; 281 dma-channels = <15>; 282 }; 283 284 dmac1: dma-controller@e6720000 { 285 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 286 reg = <0 0xe6720000 0 0x20000>; 287 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 290 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 291 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 292 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 295 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 303 interrupt-names = "error", 304 "ch0", "ch1", "ch2", "ch3", 305 "ch4", "ch5", "ch6", "ch7", 306 "ch8", "ch9", "ch10", "ch11", 307 "ch12", "ch13", "ch14"; 308 clocks = <&cpg CPG_MOD 218>; 309 clock-names = "fck"; 310 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 311 resets = <&cpg 218>; 312 #dma-cells = <1>; 313 dma-channels = <15>; 314 }; 315 316 audma0: dma-controller@ec700000 { 317 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; 318 reg = <0 0xec700000 0 0x10000>; 319 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 321 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 322 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 323 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 324 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 325 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 326 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 333 interrupt-names = "error", 334 "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", 335 "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", 336 "ch12"; 337 clocks = <&cpg CPG_MOD 502>; 338 clock-names = "fck"; 339 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 340 resets = <&cpg 502>; 341 #dma-cells = <1>; 342 dma-channels = <13>; 343 }; 344 345 scifa0: serial@e6c40000 { 346 compatible = "renesas,scifa-r8a7794", 347 "renesas,rcar-gen2-scifa", "renesas,scifa"; 348 reg = <0 0xe6c40000 0 64>; 349 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&cpg CPG_MOD 204>; 351 clock-names = "fck"; 352 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 353 <&dmac1 0x21>, <&dmac1 0x22>; 354 dma-names = "tx", "rx", "tx", "rx"; 355 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 356 resets = <&cpg 204>; 357 status = "disabled"; 358 }; 359 360 scifa1: serial@e6c50000 { 361 compatible = "renesas,scifa-r8a7794", 362 "renesas,rcar-gen2-scifa", "renesas,scifa"; 363 reg = <0 0xe6c50000 0 64>; 364 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cpg CPG_MOD 203>; 366 clock-names = "fck"; 367 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 368 <&dmac1 0x25>, <&dmac1 0x26>; 369 dma-names = "tx", "rx", "tx", "rx"; 370 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 371 resets = <&cpg 203>; 372 status = "disabled"; 373 }; 374 375 scifa2: serial@e6c60000 { 376 compatible = "renesas,scifa-r8a7794", 377 "renesas,rcar-gen2-scifa", "renesas,scifa"; 378 reg = <0 0xe6c60000 0 64>; 379 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&cpg CPG_MOD 202>; 381 clock-names = "fck"; 382 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 383 <&dmac1 0x27>, <&dmac1 0x28>; 384 dma-names = "tx", "rx", "tx", "rx"; 385 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 386 resets = <&cpg 202>; 387 status = "disabled"; 388 }; 389 390 scifa3: serial@e6c70000 { 391 compatible = "renesas,scifa-r8a7794", 392 "renesas,rcar-gen2-scifa", "renesas,scifa"; 393 reg = <0 0xe6c70000 0 64>; 394 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cpg CPG_MOD 1106>; 396 clock-names = "fck"; 397 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 398 <&dmac1 0x1b>, <&dmac1 0x1c>; 399 dma-names = "tx", "rx", "tx", "rx"; 400 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 401 resets = <&cpg 1106>; 402 status = "disabled"; 403 }; 404 405 scifa4: serial@e6c78000 { 406 compatible = "renesas,scifa-r8a7794", 407 "renesas,rcar-gen2-scifa", "renesas,scifa"; 408 reg = <0 0xe6c78000 0 64>; 409 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 1107>; 411 clock-names = "fck"; 412 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 413 <&dmac1 0x1f>, <&dmac1 0x20>; 414 dma-names = "tx", "rx", "tx", "rx"; 415 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 416 resets = <&cpg 1107>; 417 status = "disabled"; 418 }; 419 420 scifa5: serial@e6c80000 { 421 compatible = "renesas,scifa-r8a7794", 422 "renesas,rcar-gen2-scifa", "renesas,scifa"; 423 reg = <0 0xe6c80000 0 64>; 424 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 1108>; 426 clock-names = "fck"; 427 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 428 <&dmac1 0x23>, <&dmac1 0x24>; 429 dma-names = "tx", "rx", "tx", "rx"; 430 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 431 resets = <&cpg 1108>; 432 status = "disabled"; 433 }; 434 435 scifb0: serial@e6c20000 { 436 compatible = "renesas,scifb-r8a7794", 437 "renesas,rcar-gen2-scifb", "renesas,scifb"; 438 reg = <0 0xe6c20000 0 0x100>; 439 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cpg CPG_MOD 206>; 441 clock-names = "fck"; 442 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 443 <&dmac1 0x3d>, <&dmac1 0x3e>; 444 dma-names = "tx", "rx", "tx", "rx"; 445 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 446 resets = <&cpg 206>; 447 status = "disabled"; 448 }; 449 450 scifb1: serial@e6c30000 { 451 compatible = "renesas,scifb-r8a7794", 452 "renesas,rcar-gen2-scifb", "renesas,scifb"; 453 reg = <0 0xe6c30000 0 0x100>; 454 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cpg CPG_MOD 207>; 456 clock-names = "fck"; 457 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 458 <&dmac1 0x19>, <&dmac1 0x1a>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 461 resets = <&cpg 207>; 462 status = "disabled"; 463 }; 464 465 scifb2: serial@e6ce0000 { 466 compatible = "renesas,scifb-r8a7794", 467 "renesas,rcar-gen2-scifb", "renesas,scifb"; 468 reg = <0 0xe6ce0000 0 0x100>; 469 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 216>; 471 clock-names = "fck"; 472 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 473 <&dmac1 0x1d>, <&dmac1 0x1e>; 474 dma-names = "tx", "rx", "tx", "rx"; 475 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 476 resets = <&cpg 216>; 477 status = "disabled"; 478 }; 479 480 scif0: serial@e6e60000 { 481 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 482 "renesas,scif"; 483 reg = <0 0xe6e60000 0 64>; 484 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 486 <&scif_clk>; 487 clock-names = "fck", "brg_int", "scif_clk"; 488 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 489 <&dmac1 0x29>, <&dmac1 0x2a>; 490 dma-names = "tx", "rx", "tx", "rx"; 491 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 492 resets = <&cpg 721>; 493 status = "disabled"; 494 }; 495 496 scif1: serial@e6e68000 { 497 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 498 "renesas,scif"; 499 reg = <0 0xe6e68000 0 64>; 500 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 502 <&scif_clk>; 503 clock-names = "fck", "brg_int", "scif_clk"; 504 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 505 <&dmac1 0x2d>, <&dmac1 0x2e>; 506 dma-names = "tx", "rx", "tx", "rx"; 507 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 508 resets = <&cpg 720>; 509 status = "disabled"; 510 }; 511 512 scif2: serial@e6e58000 { 513 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 514 "renesas,scif"; 515 reg = <0 0xe6e58000 0 64>; 516 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 518 <&scif_clk>; 519 clock-names = "fck", "brg_int", "scif_clk"; 520 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 521 <&dmac1 0x2b>, <&dmac1 0x2c>; 522 dma-names = "tx", "rx", "tx", "rx"; 523 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 524 resets = <&cpg 719>; 525 status = "disabled"; 526 }; 527 528 scif3: serial@e6ea8000 { 529 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 530 "renesas,scif"; 531 reg = <0 0xe6ea8000 0 64>; 532 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 534 <&scif_clk>; 535 clock-names = "fck", "brg_int", "scif_clk"; 536 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 537 <&dmac1 0x2f>, <&dmac1 0x30>; 538 dma-names = "tx", "rx", "tx", "rx"; 539 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 540 resets = <&cpg 718>; 541 status = "disabled"; 542 }; 543 544 scif4: serial@e6ee0000 { 545 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 546 "renesas,scif"; 547 reg = <0 0xe6ee0000 0 64>; 548 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 550 <&scif_clk>; 551 clock-names = "fck", "brg_int", "scif_clk"; 552 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 553 <&dmac1 0xfb>, <&dmac1 0xfc>; 554 dma-names = "tx", "rx", "tx", "rx"; 555 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 556 resets = <&cpg 715>; 557 status = "disabled"; 558 }; 559 560 scif5: serial@e6ee8000 { 561 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif", 562 "renesas,scif"; 563 reg = <0 0xe6ee8000 0 64>; 564 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 566 <&scif_clk>; 567 clock-names = "fck", "brg_int", "scif_clk"; 568 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 569 <&dmac1 0xfd>, <&dmac1 0xfe>; 570 dma-names = "tx", "rx", "tx", "rx"; 571 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 572 resets = <&cpg 714>; 573 status = "disabled"; 574 }; 575 576 hscif0: serial@e62c0000 { 577 compatible = "renesas,hscif-r8a7794", 578 "renesas,rcar-gen2-hscif", "renesas,hscif"; 579 reg = <0 0xe62c0000 0 96>; 580 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 582 <&scif_clk>; 583 clock-names = "fck", "brg_int", "scif_clk"; 584 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 585 <&dmac1 0x39>, <&dmac1 0x3a>; 586 dma-names = "tx", "rx", "tx", "rx"; 587 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 588 resets = <&cpg 717>; 589 status = "disabled"; 590 }; 591 592 hscif1: serial@e62c8000 { 593 compatible = "renesas,hscif-r8a7794", 594 "renesas,rcar-gen2-hscif", "renesas,hscif"; 595 reg = <0 0xe62c8000 0 96>; 596 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 598 <&scif_clk>; 599 clock-names = "fck", "brg_int", "scif_clk"; 600 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 601 <&dmac1 0x4d>, <&dmac1 0x4e>; 602 dma-names = "tx", "rx", "tx", "rx"; 603 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 604 resets = <&cpg 716>; 605 status = "disabled"; 606 }; 607 608 hscif2: serial@e62d0000 { 609 compatible = "renesas,hscif-r8a7794", 610 "renesas,rcar-gen2-hscif", "renesas,hscif"; 611 reg = <0 0xe62d0000 0 96>; 612 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, 614 <&scif_clk>; 615 clock-names = "fck", "brg_int", "scif_clk"; 616 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 617 <&dmac1 0x3b>, <&dmac1 0x3c>; 618 dma-names = "tx", "rx", "tx", "rx"; 619 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 620 resets = <&cpg 713>; 621 status = "disabled"; 622 }; 623 624 icram0: sram@e63a0000 { 625 compatible = "mmio-sram"; 626 reg = <0 0xe63a0000 0 0x12000>; 627 }; 628 629 icram1: sram@e63c0000 { 630 compatible = "mmio-sram"; 631 reg = <0 0xe63c0000 0 0x1000>; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges = <0 0 0xe63c0000 0x1000>; 635 636 smp-sram@0 { 637 compatible = "renesas,smp-sram"; 638 reg = <0 0x10>; 639 }; 640 }; 641 642 ether: ethernet@ee700000 { 643 compatible = "renesas,ether-r8a7794"; 644 reg = <0 0xee700000 0 0x400>; 645 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cpg CPG_MOD 813>; 647 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 648 resets = <&cpg 813>; 649 phy-mode = "rmii"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 status = "disabled"; 653 }; 654 655 avb: ethernet@e6800000 { 656 compatible = "renesas,etheravb-r8a7794", 657 "renesas,etheravb-rcar-gen2"; 658 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 659 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cpg CPG_MOD 812>; 661 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 662 resets = <&cpg 812>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 /* The memory map in the User's Manual maps the cores to bus numbers */ 669 i2c0: i2c@e6508000 { 670 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 671 reg = <0 0xe6508000 0 0x40>; 672 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cpg CPG_MOD 931>; 674 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 675 resets = <&cpg 931>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 i2c-scl-internal-delay-ns = <6>; 679 status = "disabled"; 680 }; 681 682 i2c1: i2c@e6518000 { 683 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 684 reg = <0 0xe6518000 0 0x40>; 685 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cpg CPG_MOD 930>; 687 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 688 resets = <&cpg 930>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 i2c-scl-internal-delay-ns = <6>; 692 status = "disabled"; 693 }; 694 695 i2c2: i2c@e6530000 { 696 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 697 reg = <0 0xe6530000 0 0x40>; 698 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cpg CPG_MOD 929>; 700 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 701 resets = <&cpg 929>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 i2c-scl-internal-delay-ns = <6>; 705 status = "disabled"; 706 }; 707 708 i2c3: i2c@e6540000 { 709 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 710 reg = <0 0xe6540000 0 0x40>; 711 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&cpg CPG_MOD 928>; 713 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 714 resets = <&cpg 928>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 i2c-scl-internal-delay-ns = <6>; 718 status = "disabled"; 719 }; 720 721 i2c4: i2c@e6520000 { 722 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 723 reg = <0 0xe6520000 0 0x40>; 724 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cpg CPG_MOD 927>; 726 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 727 resets = <&cpg 927>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 i2c-scl-internal-delay-ns = <6>; 731 status = "disabled"; 732 }; 733 734 i2c5: i2c@e6528000 { 735 compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; 736 reg = <0 0xe6528000 0 0x40>; 737 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 925>; 739 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 740 resets = <&cpg 925>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 i2c-scl-internal-delay-ns = <6>; 744 status = "disabled"; 745 }; 746 747 i2c6: i2c@e6500000 { 748 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", 749 "renesas,rmobile-iic"; 750 reg = <0 0xe6500000 0 0x425>; 751 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 318>; 753 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 754 <&dmac1 0x61>, <&dmac1 0x62>; 755 dma-names = "tx", "rx", "tx", "rx"; 756 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 757 resets = <&cpg 318>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c7: i2c@e6510000 { 764 compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic", 765 "renesas,rmobile-iic"; 766 reg = <0 0xe6510000 0 0x425>; 767 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD 323>; 769 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 770 <&dmac1 0x65>, <&dmac1 0x66>; 771 dma-names = "tx", "rx", "tx", "rx"; 772 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 773 resets = <&cpg 323>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 mmcif0: mmc@ee200000 { 780 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; 781 reg = <0 0xee200000 0 0x80>; 782 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&cpg CPG_MOD 315>; 784 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 785 <&dmac1 0xd1>, <&dmac1 0xd2>; 786 dma-names = "tx", "rx", "tx", "rx"; 787 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 788 resets = <&cpg 315>; 789 reg-io-width = <4>; 790 status = "disabled"; 791 }; 792 793 sdhi0: sd@ee100000 { 794 compatible = "renesas,sdhi-r8a7794"; 795 reg = <0 0xee100000 0 0x328>; 796 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 314>; 798 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 799 <&dmac1 0xcd>, <&dmac1 0xce>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 max-frequency = <195000000>; 802 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 803 resets = <&cpg 314>; 804 status = "disabled"; 805 }; 806 807 sdhi1: sd@ee140000 { 808 compatible = "renesas,sdhi-r8a7794"; 809 reg = <0 0xee140000 0 0x100>; 810 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 312>; 812 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 813 <&dmac1 0xc1>, <&dmac1 0xc2>; 814 dma-names = "tx", "rx", "tx", "rx"; 815 max-frequency = <97500000>; 816 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 817 resets = <&cpg 312>; 818 status = "disabled"; 819 }; 820 821 sdhi2: sd@ee160000 { 822 compatible = "renesas,sdhi-r8a7794"; 823 reg = <0 0xee160000 0 0x100>; 824 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&cpg CPG_MOD 311>; 826 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 827 <&dmac1 0xd3>, <&dmac1 0xd4>; 828 dma-names = "tx", "rx", "tx", "rx"; 829 max-frequency = <97500000>; 830 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 831 resets = <&cpg 311>; 832 status = "disabled"; 833 }; 834 835 qspi: spi@e6b10000 { 836 compatible = "renesas,qspi-r8a7794", "renesas,qspi"; 837 reg = <0 0xe6b10000 0 0x2c>; 838 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cpg CPG_MOD 917>; 840 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 841 <&dmac1 0x17>, <&dmac1 0x18>; 842 dma-names = "tx", "rx", "tx", "rx"; 843 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 844 resets = <&cpg 917>; 845 num-cs = <1>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 status = "disabled"; 849 }; 850 851 vin0: video@e6ef0000 { 852 compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; 853 reg = <0 0xe6ef0000 0 0x1000>; 854 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 811>; 856 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 857 resets = <&cpg 811>; 858 status = "disabled"; 859 }; 860 861 vin1: video@e6ef1000 { 862 compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; 863 reg = <0 0xe6ef1000 0 0x1000>; 864 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cpg CPG_MOD 810>; 866 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 867 resets = <&cpg 810>; 868 status = "disabled"; 869 }; 870 871 pci0: pci@ee090000 { 872 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; 873 device_type = "pci"; 874 reg = <0 0xee090000 0 0xc00>, 875 <0 0xee080000 0 0x1100>; 876 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cpg CPG_MOD 703>; 878 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 879 resets = <&cpg 703>; 880 status = "disabled"; 881 882 bus-range = <0 0>; 883 #address-cells = <3>; 884 #size-cells = <2>; 885 #interrupt-cells = <1>; 886 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 887 interrupt-map-mask = <0xff00 0 0 0x7>; 888 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 889 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 890 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 891 892 usb@1,0 { 893 reg = <0x800 0 0 0 0>; 894 phys = <&usb0 0>; 895 phy-names = "usb"; 896 }; 897 898 usb@2,0 { 899 reg = <0x1000 0 0 0 0>; 900 phys = <&usb0 0>; 901 phy-names = "usb"; 902 }; 903 }; 904 905 pci1: pci@ee0d0000 { 906 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2"; 907 device_type = "pci"; 908 reg = <0 0xee0d0000 0 0xc00>, 909 <0 0xee0c0000 0 0x1100>; 910 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cpg CPG_MOD 703>; 912 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 913 resets = <&cpg 703>; 914 status = "disabled"; 915 916 bus-range = <1 1>; 917 #address-cells = <3>; 918 #size-cells = <2>; 919 #interrupt-cells = <1>; 920 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 921 interrupt-map-mask = <0xff00 0 0 0x7>; 922 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 923 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 924 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 925 926 usb@1,0 { 927 reg = <0x10800 0 0 0 0>; 928 phys = <&usb2 0>; 929 phy-names = "usb"; 930 }; 931 932 usb@2,0 { 933 reg = <0x11000 0 0 0 0>; 934 phys = <&usb2 0>; 935 phy-names = "usb"; 936 }; 937 }; 938 939 hsusb: usb@e6590000 { 940 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; 941 reg = <0 0xe6590000 0 0x100>; 942 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&cpg CPG_MOD 704>; 944 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 945 resets = <&cpg 704>; 946 renesas,buswait = <4>; 947 phys = <&usb0 1>; 948 phy-names = "usb"; 949 status = "disabled"; 950 }; 951 952 usbphy: usb-phy@e6590100 { 953 compatible = "renesas,usb-phy-r8a7794", 954 "renesas,rcar-gen2-usb-phy"; 955 reg = <0 0xe6590100 0 0x100>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 clocks = <&cpg CPG_MOD 704>; 959 clock-names = "usbhs"; 960 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 961 resets = <&cpg 704>; 962 status = "disabled"; 963 964 usb0: usb-channel@0 { 965 reg = <0>; 966 #phy-cells = <1>; 967 }; 968 usb2: usb-channel@2 { 969 reg = <2>; 970 #phy-cells = <1>; 971 }; 972 }; 973 974 vsp@fe928000 { 975 compatible = "renesas,vsp1"; 976 reg = <0 0xfe928000 0 0x8000>; 977 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&cpg CPG_MOD 131>; 979 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 980 resets = <&cpg 131>; 981 }; 982 983 vsp@fe930000 { 984 compatible = "renesas,vsp1"; 985 reg = <0 0xfe930000 0 0x8000>; 986 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cpg CPG_MOD 128>; 988 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 989 resets = <&cpg 128>; 990 }; 991 992 du: display@feb00000 { 993 compatible = "renesas,du-r8a7794"; 994 reg = <0 0xfeb00000 0 0x40000>; 995 reg-names = "du"; 996 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 999 clock-names = "du.0", "du.1"; 1000 status = "disabled"; 1001 1002 ports { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 1006 port@0 { 1007 reg = <0>; 1008 du_out_rgb0: endpoint { 1009 }; 1010 }; 1011 port@1 { 1012 reg = <1>; 1013 du_out_rgb1: endpoint { 1014 }; 1015 }; 1016 }; 1017 }; 1018 1019 can0: can@e6e80000 { 1020 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; 1021 reg = <0 0xe6e80000 0 0x1000>; 1022 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, 1024 <&can_clk>; 1025 clock-names = "clkp1", "clkp2", "can_clk"; 1026 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 1027 resets = <&cpg 916>; 1028 status = "disabled"; 1029 }; 1030 1031 can1: can@e6e88000 { 1032 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; 1033 reg = <0 0xe6e88000 0 0x1000>; 1034 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, 1036 <&can_clk>; 1037 clock-names = "clkp1", "clkp2", "can_clk"; 1038 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 1039 resets = <&cpg 915>; 1040 status = "disabled"; 1041 }; 1042 1043 /* External root clock */ 1044 extal_clk: extal { 1045 compatible = "fixed-clock"; 1046 #clock-cells = <0>; 1047 /* This value must be overridden by the board. */ 1048 clock-frequency = <0>; 1049 }; 1050 1051 /* External USB clock - can be overridden by the board */ 1052 usb_extal_clk: usb_extal { 1053 compatible = "fixed-clock"; 1054 #clock-cells = <0>; 1055 clock-frequency = <48000000>; 1056 }; 1057 1058 /* External CAN clock */ 1059 can_clk: can { 1060 compatible = "fixed-clock"; 1061 #clock-cells = <0>; 1062 /* This value must be overridden by the board. */ 1063 clock-frequency = <0>; 1064 }; 1065 1066 /* External SCIF clock */ 1067 scif_clk: scif { 1068 compatible = "fixed-clock"; 1069 #clock-cells = <0>; 1070 /* This value must be overridden by the board. */ 1071 clock-frequency = <0>; 1072 }; 1073 1074 /* 1075 * The external audio clocks are configured as 0 Hz fixed 1076 * frequency clocks by default. Boards that provide audio 1077 * clocks should override them. 1078 */ 1079 audio_clka: audio_clka { 1080 compatible = "fixed-clock"; 1081 #clock-cells = <0>; 1082 clock-frequency = <0>; 1083 }; 1084 audio_clkb: audio_clkb { 1085 compatible = "fixed-clock"; 1086 #clock-cells = <0>; 1087 clock-frequency = <0>; 1088 }; 1089 audio_clkc: audio_clkc { 1090 compatible = "fixed-clock"; 1091 #clock-cells = <0>; 1092 clock-frequency = <0>; 1093 }; 1094 1095 cpg: clock-controller@e6150000 { 1096 compatible = "renesas,r8a7794-cpg-mssr"; 1097 reg = <0 0xe6150000 0 0x1000>; 1098 clocks = <&extal_clk>, <&usb_extal_clk>; 1099 clock-names = "extal", "usb_extal"; 1100 #clock-cells = <2>; 1101 #power-domain-cells = <0>; 1102 }; 1103 1104 rst: reset-controller@e6160000 { 1105 compatible = "renesas,r8a7794-rst"; 1106 reg = <0 0xe6160000 0 0x0100>; 1107 }; 1108 1109 prr: chipid@ff000044 { 1110 compatible = "renesas,prr"; 1111 reg = <0 0xff000044 0 4>; 1112 }; 1113 1114 sysc: system-controller@e6180000 { 1115 compatible = "renesas,r8a7794-sysc"; 1116 reg = <0 0xe6180000 0 0x0200>; 1117 #power-domain-cells = <1>; 1118 }; 1119 1120 ipmmu_sy0: mmu@e6280000 { 1121 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1122 reg = <0 0xe6280000 0 0x1000>; 1123 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1125 #iommu-cells = <1>; 1126 status = "disabled"; 1127 }; 1128 1129 ipmmu_sy1: mmu@e6290000 { 1130 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1131 reg = <0 0xe6290000 0 0x1000>; 1132 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1133 #iommu-cells = <1>; 1134 status = "disabled"; 1135 }; 1136 1137 ipmmu_ds: mmu@e6740000 { 1138 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1139 reg = <0 0xe6740000 0 0x1000>; 1140 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1142 #iommu-cells = <1>; 1143 status = "disabled"; 1144 }; 1145 1146 ipmmu_mp: mmu@ec680000 { 1147 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1148 reg = <0 0xec680000 0 0x1000>; 1149 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1150 #iommu-cells = <1>; 1151 status = "disabled"; 1152 }; 1153 1154 ipmmu_mx: mmu@fe951000 { 1155 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1156 reg = <0 0xfe951000 0 0x1000>; 1157 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1159 #iommu-cells = <1>; 1160 status = "disabled"; 1161 }; 1162 1163 ipmmu_gp: mmu@e62a0000 { 1164 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1165 reg = <0 0xe62a0000 0 0x1000>; 1166 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1168 #iommu-cells = <1>; 1169 status = "disabled"; 1170 }; 1171 1172 rcar_sound: sound@ec500000 { 1173 /* 1174 * #sound-dai-cells is required 1175 * 1176 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1177 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1178 */ 1179 compatible = "renesas,rcar_sound-r8a7794", 1180 "renesas,rcar_sound-gen2"; 1181 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1182 <0 0xec5a0000 0 0x100>, /* ADG */ 1183 <0 0xec540000 0 0x1000>, /* SSIU */ 1184 <0 0xec541000 0 0x280>, /* SSI */ 1185 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ 1186 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1187 1188 clocks = <&cpg CPG_MOD 1005>, 1189 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1190 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1191 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1192 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1193 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1194 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, 1195 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, 1196 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, 1197 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1198 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1199 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1200 <&audio_clka>, <&audio_clkb>, <&audio_clkc>, 1201 <&cpg CPG_CORE R8A7794_CLK_M2>; 1202 clock-names = "ssi-all", 1203 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1204 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1205 "src.6", "src.5", "src.4", "src.3", "src.2", 1206 "src.1", 1207 "ctu.0", "ctu.1", 1208 "mix.0", "mix.1", 1209 "dvc.0", "dvc.1", 1210 "clk_a", "clk_b", "clk_c", "clk_i"; 1211 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; 1212 resets = <&cpg 1005>, 1213 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, 1214 <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, 1215 <&cpg 1014>, <&cpg 1015>; 1216 reset-names = "ssi-all", 1217 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1218 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; 1219 1220 status = "disabled"; 1221 1222 rcar_sound,dvc { 1223 dvc0: dvc-0 { 1224 dmas = <&audma0 0xbc>; 1225 dma-names = "tx"; 1226 }; 1227 dvc1: dvc-1 { 1228 dmas = <&audma0 0xbe>; 1229 dma-names = "tx"; 1230 }; 1231 }; 1232 1233 rcar_sound,mix { 1234 mix0: mix-0 { }; 1235 mix1: mix-1 { }; 1236 }; 1237 1238 rcar_sound,ctu { 1239 ctu00: ctu-0 { }; 1240 ctu01: ctu-1 { }; 1241 ctu02: ctu-2 { }; 1242 ctu03: ctu-3 { }; 1243 ctu10: ctu-4 { }; 1244 ctu11: ctu-5 { }; 1245 ctu12: ctu-6 { }; 1246 ctu13: ctu-7 { }; 1247 }; 1248 1249 rcar_sound,src { 1250 src-0 { 1251 status = "disabled"; 1252 }; 1253 src1: src-1 { 1254 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1255 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1256 dma-names = "rx", "tx"; 1257 }; 1258 src2: src-2 { 1259 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1260 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1261 dma-names = "rx", "tx"; 1262 }; 1263 src3: src-3 { 1264 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1265 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1266 dma-names = "rx", "tx"; 1267 }; 1268 src4: src-4 { 1269 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1270 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1271 dma-names = "rx", "tx"; 1272 }; 1273 src5: src-5 { 1274 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1275 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1276 dma-names = "rx", "tx"; 1277 }; 1278 src6: src-6 { 1279 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1280 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1281 dma-names = "rx", "tx"; 1282 }; 1283 }; 1284 1285 rcar_sound,ssi { 1286 ssi0: ssi-0 { 1287 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1288 dmas = <&audma0 0x01>, <&audma0 0x02>, 1289 <&audma0 0x15>, <&audma0 0x16>; 1290 dma-names = "rx", "tx", "rxu", "txu"; 1291 }; 1292 ssi1: ssi-1 { 1293 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1294 dmas = <&audma0 0x03>, <&audma0 0x04>, 1295 <&audma0 0x49>, <&audma0 0x4a>; 1296 dma-names = "rx", "tx", "rxu", "txu"; 1297 }; 1298 ssi2: ssi-2 { 1299 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1300 dmas = <&audma0 0x05>, <&audma0 0x06>, 1301 <&audma0 0x63>, <&audma0 0x64>; 1302 dma-names = "rx", "tx", "rxu", "txu"; 1303 }; 1304 ssi3: ssi-3 { 1305 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1306 dmas = <&audma0 0x07>, <&audma0 0x08>, 1307 <&audma0 0x6f>, <&audma0 0x70>; 1308 dma-names = "rx", "tx", "rxu", "txu"; 1309 }; 1310 ssi4: ssi-4 { 1311 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1312 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1313 <&audma0 0x71>, <&audma0 0x72>; 1314 dma-names = "rx", "tx", "rxu", "txu"; 1315 }; 1316 ssi5: ssi-5 { 1317 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1318 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1319 <&audma0 0x73>, <&audma0 0x74>; 1320 dma-names = "rx", "tx", "rxu", "txu"; 1321 }; 1322 ssi6: ssi-6 { 1323 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1324 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1325 <&audma0 0x75>, <&audma0 0x76>; 1326 dma-names = "rx", "tx", "rxu", "txu"; 1327 }; 1328 ssi7: ssi-7 { 1329 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1330 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1331 <&audma0 0x79>, <&audma0 0x7a>; 1332 dma-names = "rx", "tx", "rxu", "txu"; 1333 }; 1334 ssi8: ssi-8 { 1335 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1336 dmas = <&audma0 0x11>, <&audma0 0x12>, 1337 <&audma0 0x7b>, <&audma0 0x7c>; 1338 dma-names = "rx", "tx", "rxu", "txu"; 1339 }; 1340 ssi9: ssi-9 { 1341 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&audma0 0x13>, <&audma0 0x14>, 1343 <&audma0 0x7d>, <&audma0 0x7e>; 1344 dma-names = "rx", "tx", "rxu", "txu"; 1345 }; 1346 }; 1347 }; 1348 }; 1349
Indexes created Mon Oct 27 04:09:48 GMT 2025