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      1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2 /*
      3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
      4  * Author: Alexandre Torgue <alexandre.torgue (a] foss.st.com> for STMicroelectronics.
      5  */
      6 
      7 /dts-v1/;
      8 
      9 #include "stm32mp157c-ev1.dts"
     10 #include "stm32mp15-scmi.dtsi"
     11 
     12 / {
     13 	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
     14 	compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
     15 
     16 	reserved-memory {
     17 		optee@fe000000 {
     18 			reg = <0xfe000000 0x2000000>;
     19 			no-map;
     20 		};
     21 	};
     22 };
     23 
     24 &cpu0 {
     25 	clocks = <&scmi_clk CK_SCMI_MPU>;
     26 };
     27 
     28 &cpu1 {
     29 	clocks = <&scmi_clk CK_SCMI_MPU>;
     30 };
     31 
     32 &cryp1 {
     33 	clocks = <&scmi_clk CK_SCMI_CRYP1>;
     34 	resets = <&scmi_reset RST_SCMI_CRYP1>;
     35 };
     36 
     37 &dsi {
     38 	phy-dsi-supply = <&scmi_reg18>;
     39 	clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
     40 };
     41 
     42 &gpioz {
     43 	clocks = <&scmi_clk CK_SCMI_GPIOZ>;
     44 };
     45 
     46 &hash1 {
     47 	clocks = <&scmi_clk CK_SCMI_HASH1>;
     48 	resets = <&scmi_reset RST_SCMI_HASH1>;
     49 };
     50 
     51 &i2c4 {
     52 	clocks = <&scmi_clk CK_SCMI_I2C4>;
     53 	resets = <&scmi_reset RST_SCMI_I2C4>;
     54 };
     55 
     56 &iwdg2 {
     57 	clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
     58 };
     59 
     60 &m_can1 {
     61 	clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
     62 };
     63 
     64 &mdma1 {
     65 	resets = <&scmi_reset RST_SCMI_MDMA>;
     66 };
     67 
     68 &m4_rproc {
     69 	/delete-property/ st,syscfg-holdboot;
     70 	resets = <&scmi_reset RST_SCMI_MCU>,
     71 		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
     72 	reset-names = "mcu_rst", "hold_boot";
     73 };
     74 
     75 &optee {
     76 	interrupt-parent = <&intc>;
     77 	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
     78 };
     79 
     80 &rcc {
     81 	compatible = "st,stm32mp1-rcc-secure", "syscon";
     82 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
     83 	clocks = <&scmi_clk CK_SCMI_HSE>,
     84 		 <&scmi_clk CK_SCMI_HSI>,
     85 		 <&scmi_clk CK_SCMI_CSI>,
     86 		 <&scmi_clk CK_SCMI_LSE>,
     87 		 <&scmi_clk CK_SCMI_LSI>;
     88 };
     89 
     90 &rng1 {
     91 	clocks = <&scmi_clk CK_SCMI_RNG1>;
     92 	resets = <&scmi_reset RST_SCMI_RNG1>;
     93 };
     94 
     95 &rtc {
     96 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
     97 };
     98