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      1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2 /*
      3  * Copyright (C) Protonic Holland
      4  * Author: David Jander <david (a] protonic.nl>
      5  */
      6 
      7 #include "stm32mp15xc.dtsi"
      8 #include "stm32mp15-pinctrl.dtsi"
      9 #include "stm32mp15xxaa-pinctrl.dtsi"
     10 #include <dt-bindings/gpio/gpio.h>
     11 #include <dt-bindings/input/input.h>
     12 
     13 / {
     14 	chosen {
     15 		stdout-path = "serial0:1500000n8";
     16 	};
     17 
     18 	aliases {
     19 		serial0 = &uart4;
     20 		ethernet0 = &ethernet0;
     21 		spi1 = &spi1;
     22 		spi2 = &spi2;
     23 		spi3 = &spi3;
     24 		spi4 = &spi4;
     25 		spi5 = &spi5;
     26 		spi6 = &spi6;
     27 	};
     28 
     29 	memory@c0000000 {
     30 		device_type = "memory";
     31 		reg = <0xC0000000 0x10000000>;
     32 	};
     33 
     34 	reserved-memory {
     35 		#address-cells = <1>;
     36 		#size-cells = <1>;
     37 		ranges;
     38 
     39 		mcuram2: mcuram2@10000000 {
     40 			compatible = "shared-dma-pool";
     41 			reg = <0x10000000 0x40000>;
     42 			no-map;
     43 		};
     44 
     45 		vdev0vring0: vdev0vring0@10040000 {
     46 			compatible = "shared-dma-pool";
     47 			reg = <0x10040000 0x1000>;
     48 			no-map;
     49 		};
     50 
     51 		vdev0vring1: vdev0vring1@10041000 {
     52 			compatible = "shared-dma-pool";
     53 			reg = <0x10041000 0x1000>;
     54 			no-map;
     55 		};
     56 
     57 		vdev0buffer: vdev0buffer@10042000 {
     58 			compatible = "shared-dma-pool";
     59 			reg = <0x10042000 0x4000>;
     60 			no-map;
     61 		};
     62 
     63 		mcuram: mcuram@30000000 {
     64 			compatible = "shared-dma-pool";
     65 			reg = <0x30000000 0x40000>;
     66 			no-map;
     67 		};
     68 
     69 		retram: retram@38000000 {
     70 			compatible = "shared-dma-pool";
     71 			reg = <0x38000000 0x10000>;
     72 			no-map;
     73 		};
     74 	};
     75 
     76 	v3v3: regulator-v3v3 {
     77 		compatible = "regulator-fixed";
     78 		regulator-name = "v3v3";
     79 		regulator-min-microvolt = <3300000>;
     80 		regulator-max-microvolt = <3300000>;
     81 	};
     82 
     83 	v5v: regulator-v5v {
     84 		compatible = "regulator-fixed";
     85 		regulator-name = "v5v";
     86 		regulator-min-microvolt = <5000000>;
     87 		regulator-max-microvolt = <5000000>;
     88 		regulator-always-on;
     89 	};
     90 };
     91 
     92 &adc {
     93 	/* ANA0, ANA1 are dedicated pins and don't need pinctrl. */
     94 	pinctrl-0 = <&adc12_pins_mecsbc>;
     95 	pinctrl-names = "default";
     96 	vdd-supply = <&v3v3>;
     97 	vdda-supply = <&v3v3>;
     98 	vref-supply = <&vrefbuf>;
     99 	status = "okay";
    100 };
    101 
    102 &adc1 {
    103 	status = "okay";
    104 
    105 	channel@2 {
    106 		reg = <2>;
    107 		st,min-sample-time-ns = <20000>;
    108 		label = "ain0";
    109 	};
    110 
    111 	channel@6 {
    112 		reg = <6>;
    113 		st,min-sample-time-ns = <20000>;
    114 		label = "ain1";
    115 	};
    116 
    117 	channel@10 {
    118 		reg = <10>;
    119 		st,min-sample-time-ns = <200000>;
    120 		label = "phint0_ain";
    121 	};
    122 
    123 	channel@16 {
    124 		reg = <16>;
    125 		st,min-sample-time-ns = <20000>;
    126 		label = "lsin";
    127 	};
    128 
    129 	channel@19 {
    130 		reg = <19>;
    131 		st,min-sample-time-ns = <20000>;
    132 		label = "hpdcm1_i1";
    133 	};
    134 };
    135 
    136 &adc2 {
    137 	status = "okay";
    138 
    139 	channel@2 {
    140 		reg = <2>;
    141 		st,min-sample-time-ns = <20000>;
    142 		label = "ain2";
    143 	};
    144 
    145 	channel@6 {
    146 		reg = <6>;
    147 		st,min-sample-time-ns = <20000>;
    148 		label = "ain3";
    149 	};
    150 };
    151 
    152 &ethernet0 {
    153 	status = "okay";
    154 	pinctrl-0 = <&ethernet0_rgmii_pins_x>;
    155 	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_x>;
    156 	pinctrl-names = "default", "sleep";
    157 	phy-mode = "rgmii-id";
    158 	max-speed = <1000>;
    159 	phy-handle = <&phy0>;
    160 	st,eth-clk-sel;
    161 
    162 	mdio {
    163 		#address-cells = <1>;
    164 		#size-cells = <0>;
    165 		compatible = "snps,dwmac-mdio";
    166 		phy0: ethernet-phy@8 {
    167 			reg = <8>;
    168 			interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
    169 			reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>;
    170 			reset-assert-us = <10>;
    171 			reset-deassert-us = <35>;
    172 		};
    173 	};
    174 };
    175 
    176 &i2c2 {
    177 	pinctrl-names = "default";
    178 	pinctrl-0 = <&i2c2_pins_a>;
    179 	pinctrl-1 = <&i2c2_sleep_pins_a>;
    180 	status = "okay";
    181 
    182 	gpio0: gpio@20 {
    183 		compatible = "ti,tca6416";
    184 		reg = <0x20>;
    185 		gpio-controller;
    186 		#gpio-cells = <2>;
    187 	};
    188 
    189 	gpio1: gpio@21 {
    190 		compatible = "ti,tca6416";
    191 		reg = <0x21>;
    192 		gpio-controller;
    193 		#gpio-cells = <2>;
    194 	};
    195 };
    196 
    197 &qspi {
    198 	pinctrl-names = "default", "sleep";
    199 	pinctrl-0 = <&qspi_clk_pins_a
    200 		     &qspi_bk1_pins_a
    201 		     &qspi_cs1_pins_a>;
    202 	pinctrl-1 = <&qspi_clk_sleep_pins_a
    203 		     &qspi_bk1_sleep_pins_a
    204 		     &qspi_cs1_sleep_pins_a>;
    205 	status = "okay";
    206 
    207 	flash@0 {
    208 		compatible = "jedec,spi-nor";
    209 		reg = <0>;
    210 		spi-rx-bus-width = <4>;
    211 		spi-max-frequency = <104000000>;
    212 		#address-cells = <1>;
    213 		#size-cells = <1>;
    214 	};
    215 };
    216 
    217 &{qspi_bk1_pins_a/pins} {
    218 	pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
    219 		 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
    220 		 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
    221 		 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
    222 	/delete-property/ bias-disable;
    223 	bias-pull-up;
    224 };
    225 
    226 &timers1 {
    227 	/delete-property/dmas;
    228 	/delete-property/dma-names;
    229 	status = "okay";
    230 
    231 	hpdcm0_pwm: pwm {
    232 		pinctrl-names = "default", "sleep";
    233 		pinctrl-0 = <&pwm1_pins_mecio1>;
    234 		pinctrl-1 = <&pwm1_sleep_pins_mecio1>;
    235 		status = "okay";
    236 	};
    237 };
    238 
    239 &timers8 {
    240 	/delete-property/dmas;
    241 	/delete-property/dma-names;
    242 	status = "okay";
    243 
    244 	hpdcm1_pwm: pwm {
    245 		pinctrl-names = "default", "sleep";
    246 		pinctrl-0 = <&pwm8_pins_mecio1>;
    247 		pinctrl-1 = <&pwm8_sleep_pins_mecio1>;
    248 		status = "okay";
    249 	};
    250 };
    251 
    252 &uart4 {
    253 	pinctrl-names = "default", "sleep", "idle";
    254 	pinctrl-0 = <&uart4_pins_a>;
    255 	pinctrl-1 = <&uart4_sleep_pins_a>;
    256 	pinctrl-2 = <&uart4_idle_pins_a>;
    257 	/delete-property/dmas;
    258 	/delete-property/dma-names;
    259 	status = "okay";
    260 };
    261 
    262 &{uart4_pins_a/pins1} {
    263 	pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
    264 };
    265 
    266 &{uart4_pins_a/pins2} {
    267 	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
    268 	/delete-property/ bias-disable;
    269 	bias-pull-up;
    270 };
    271 
    272 &usbotg_hs {
    273 	dr_mode = "host";
    274 	pinctrl-0 = <&usbotg_hs_pins_a>;
    275 	pinctrl-names = "default";
    276 	phys = <&usbphyc_port1 0>;
    277 	phy-names = "usb2-phy";
    278 	vbus-supply = <&v5v>;
    279 	status = "okay";
    280 };
    281 
    282 &usbphyc {
    283 	status = "okay";
    284 };
    285 
    286 &usbphyc_port0 {
    287 	phy-supply = <&v3v3>;
    288 };
    289 
    290 &usbphyc_port1 {
    291 	phy-supply = <&v3v3>;
    292 };
    293 
    294 &vrefbuf {
    295 	regulator-min-microvolt = <2500000>;
    296 	regulator-max-microvolt = <2500000>;
    297 	vdda-supply = <&v3v3>;
    298 	status = "okay";
    299 };
    300 
    301 &pinctrl {
    302 	adc12_pins_mecsbc: adc12-ain-mecsbc-0 {
    303 		pins {
    304 			pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
    305 				 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1_INP6 */
    306 				 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2_INP2 */
    307 				 <STM32_PINMUX('F', 14, ANALOG)>, /* ADC2_INP6 */
    308 				 <STM32_PINMUX('A', 0, ANALOG)>, /* ADC1_INP16 */
    309 				 <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
    310 				 <STM32_PINMUX('A', 4, ANALOG)>, /* ADC1_INP18 */
    311 				 <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP19 */
    312 				 <STM32_PINMUX('A', 6, ANALOG)>, /* ADC1_INP3 */
    313 				 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
    314 				 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
    315 				 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
    316 				 <STM32_PINMUX('C', 3, ANALOG)>; /* ADC1_INP13 */
    317 		};
    318 	};
    319 
    320 	pinctrl_hog_d_mecsbc: hog-d-0 {
    321 		pins {
    322 			pinmux = <STM32_PINMUX('D', 12, GPIO)>; /* STP_RESETn */
    323 			bias-pull-up;
    324 			drive-push-pull;
    325 			slew-rate = <0>;
    326 		};
    327 	};
    328 
    329 	pwm1_pins_mecio1: pwm1-mecio1-0 {
    330 		pins {
    331 			pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
    332 				 <STM32_PINMUX('A', 8, AF1)>; /* TIM1_CH2 */
    333 			bias-pull-down;
    334 			drive-push-pull;
    335 			slew-rate = <0>;
    336 		};
    337 	};
    338 
    339 	pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 {
    340 		pins {
    341 			pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* TIM1_CH1 */
    342 				 <STM32_PINMUX('A', 8, ANALOG)>; /* TIM1_CH2 */
    343 		};
    344 	};
    345 
    346 	pwm8_pins_mecio1: pwm8-mecio1-0 {
    347 		pins {
    348 			pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
    349 				 <STM32_PINMUX('I', 6, AF3)>; /* TIM8_CH2 */
    350 			bias-pull-down;
    351 			drive-push-pull;
    352 			slew-rate = <0>;
    353 		};
    354 	};
    355 
    356 	pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 {
    357 		pins {
    358 			pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
    359 				 <STM32_PINMUX('I', 6, ANALOG)>; /* TIM8_CH2 */
    360 		};
    361 	};
    362 
    363 	ethernet0_rgmii_pins_x: rgmii-0 {
    364 		pins1 {
    365 			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
    366 				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
    367 				 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
    368 				 <STM32_PINMUX('B', 13, AF11)>, /* ETH_RGMII_TXD1 */
    369 				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
    370 				 <STM32_PINMUX('B', 8, AF11)>, /* ETH_RGMII_TXD3 */
    371 				 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
    372 				 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
    373 			bias-disable;
    374 			drive-push-pull;
    375 			slew-rate = <3>;
    376 		};
    377 		pins2 {
    378 			pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
    379 			bias-disable;
    380 			drive-push-pull;
    381 			slew-rate = <0>;
    382 		};
    383 		pins3 {
    384 			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
    385 				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
    386 				 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
    387 				 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
    388 				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
    389 				 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
    390 			bias-disable;
    391 		};
    392 	};
    393 
    394 	ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {
    395 		pins1 {
    396 			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
    397 				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
    398 				 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
    399 				 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH_RGMII_TXD1 */
    400 				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
    401 				 <STM32_PINMUX('B', 8, ANALOG)>, /* ETH_RGMII_TXD3 */
    402 				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
    403 				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
    404 				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
    405 				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
    406 				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
    407 				 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
    408 				 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
    409 				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
    410 				 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
    411 		};
    412 	};
    413 };
    414