1 /* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32 (at) gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 #include "armv7-m.dtsi" 44 #include <dt-bindings/clock/stm32fx-clock.h> 45 #include <dt-bindings/mfd/stm32f7-rcc.h> 46 47 / { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 clocks { 52 clk_hse: clk-hse { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57 58 clk-lse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <32768>; 62 }; 63 64 clk-lsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <32000>; 68 }; 69 70 clk_i2s_ckin: clk-i2s-ckin { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <48000000>; 74 }; 75 }; 76 77 soc { 78 timer2: timer@40000000 { 79 compatible = "st,stm32-timer"; 80 reg = <0x40000000 0x400>; 81 interrupts = <28>; 82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 83 status = "disabled"; 84 }; 85 86 timers2: timers@40000000 { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 compatible = "st,stm32-timers"; 90 reg = <0x40000000 0x400>; 91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 92 clock-names = "int"; 93 status = "disabled"; 94 95 pwm { 96 compatible = "st,stm32-pwm"; 97 #pwm-cells = <3>; 98 status = "disabled"; 99 }; 100 101 timer@1 { 102 compatible = "st,stm32-timer-trigger"; 103 reg = <1>; 104 status = "disabled"; 105 }; 106 }; 107 108 timer3: timer@40000400 { 109 compatible = "st,stm32-timer"; 110 reg = <0x40000400 0x400>; 111 interrupts = <29>; 112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 113 status = "disabled"; 114 }; 115 116 timers3: timers@40000400 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "st,stm32-timers"; 120 reg = <0x40000400 0x400>; 121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 122 clock-names = "int"; 123 status = "disabled"; 124 125 pwm { 126 compatible = "st,stm32-pwm"; 127 #pwm-cells = <3>; 128 status = "disabled"; 129 }; 130 131 timer@2 { 132 compatible = "st,stm32-timer-trigger"; 133 reg = <2>; 134 status = "disabled"; 135 }; 136 }; 137 138 timer4: timer@40000800 { 139 compatible = "st,stm32-timer"; 140 reg = <0x40000800 0x400>; 141 interrupts = <30>; 142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 143 status = "disabled"; 144 }; 145 146 timers4: timers@40000800 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "st,stm32-timers"; 150 reg = <0x40000800 0x400>; 151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 152 clock-names = "int"; 153 status = "disabled"; 154 155 pwm { 156 compatible = "st,stm32-pwm"; 157 #pwm-cells = <3>; 158 status = "disabled"; 159 }; 160 161 timer@3 { 162 compatible = "st,stm32-timer-trigger"; 163 reg = <3>; 164 status = "disabled"; 165 }; 166 }; 167 168 timer5: timer@40000c00 { 169 compatible = "st,stm32-timer"; 170 reg = <0x40000c00 0x400>; 171 interrupts = <50>; 172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 173 }; 174 175 timers5: timers@40000c00 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "st,stm32-timers"; 179 reg = <0x40000C00 0x400>; 180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 181 clock-names = "int"; 182 status = "disabled"; 183 184 pwm { 185 compatible = "st,stm32-pwm"; 186 #pwm-cells = <3>; 187 status = "disabled"; 188 }; 189 190 timer@4 { 191 compatible = "st,stm32-timer-trigger"; 192 reg = <4>; 193 status = "disabled"; 194 }; 195 }; 196 197 timer6: timer@40001000 { 198 compatible = "st,stm32-timer"; 199 reg = <0x40001000 0x400>; 200 interrupts = <54>; 201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 202 status = "disabled"; 203 }; 204 205 timers6: timers@40001000 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "st,stm32-timers"; 209 reg = <0x40001000 0x400>; 210 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 211 clock-names = "int"; 212 status = "disabled"; 213 214 timer@5 { 215 compatible = "st,stm32-timer-trigger"; 216 reg = <5>; 217 status = "disabled"; 218 }; 219 }; 220 221 timer7: timer@40001400 { 222 compatible = "st,stm32-timer"; 223 reg = <0x40001400 0x400>; 224 interrupts = <55>; 225 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 226 status = "disabled"; 227 }; 228 229 timers7: timers@40001400 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "st,stm32-timers"; 233 reg = <0x40001400 0x400>; 234 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 235 clock-names = "int"; 236 status = "disabled"; 237 238 timer@6 { 239 compatible = "st,stm32-timer-trigger"; 240 reg = <6>; 241 status = "disabled"; 242 }; 243 }; 244 245 timers12: timers@40001800 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "st,stm32-timers"; 249 reg = <0x40001800 0x400>; 250 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 251 clock-names = "int"; 252 status = "disabled"; 253 254 pwm { 255 compatible = "st,stm32-pwm"; 256 #pwm-cells = <3>; 257 status = "disabled"; 258 }; 259 260 timer@11 { 261 compatible = "st,stm32-timer-trigger"; 262 reg = <11>; 263 status = "disabled"; 264 }; 265 }; 266 267 timers13: timers@40001c00 { 268 compatible = "st,stm32-timers"; 269 reg = <0x40001C00 0x400>; 270 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 271 clock-names = "int"; 272 status = "disabled"; 273 274 pwm { 275 compatible = "st,stm32-pwm"; 276 #pwm-cells = <3>; 277 status = "disabled"; 278 }; 279 }; 280 281 timers14: timers@40002000 { 282 compatible = "st,stm32-timers"; 283 reg = <0x40002000 0x400>; 284 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 285 clock-names = "int"; 286 status = "disabled"; 287 288 pwm { 289 compatible = "st,stm32-pwm"; 290 #pwm-cells = <3>; 291 status = "disabled"; 292 }; 293 }; 294 295 rtc: rtc@40002800 { 296 compatible = "st,stm32-rtc"; 297 reg = <0x40002800 0x400>; 298 clocks = <&rcc 1 CLK_RTC>; 299 assigned-clocks = <&rcc 1 CLK_RTC>; 300 assigned-clock-parents = <&rcc 1 CLK_LSE>; 301 interrupt-parent = <&exti>; 302 interrupts = <17 1>; 303 st,syscfg = <&pwrcfg 0x00 0x100>; 304 status = "disabled"; 305 }; 306 307 usart2: serial@40004400 { 308 compatible = "st,stm32f7-uart"; 309 reg = <0x40004400 0x400>; 310 interrupts = <38>; 311 clocks = <&rcc 1 CLK_USART2>; 312 status = "disabled"; 313 }; 314 315 usart3: serial@40004800 { 316 compatible = "st,stm32f7-uart"; 317 reg = <0x40004800 0x400>; 318 interrupts = <39>; 319 clocks = <&rcc 1 CLK_USART3>; 320 status = "disabled"; 321 }; 322 323 usart4: serial@40004c00 { 324 compatible = "st,stm32f7-uart"; 325 reg = <0x40004c00 0x400>; 326 interrupts = <52>; 327 clocks = <&rcc 1 CLK_UART4>; 328 status = "disabled"; 329 }; 330 331 usart5: serial@40005000 { 332 compatible = "st,stm32f7-uart"; 333 reg = <0x40005000 0x400>; 334 interrupts = <53>; 335 clocks = <&rcc 1 CLK_UART5>; 336 status = "disabled"; 337 }; 338 339 i2c1: i2c@40005400 { 340 compatible = "st,stm32f7-i2c"; 341 reg = <0x40005400 0x400>; 342 interrupts = <31>, 343 <32>; 344 resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 345 clocks = <&rcc 1 CLK_I2C1>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 i2c2: i2c@40005800 { 352 compatible = "st,stm32f7-i2c"; 353 reg = <0x40005800 0x400>; 354 interrupts = <33>, 355 <34>; 356 resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 357 clocks = <&rcc 1 CLK_I2C2>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 i2c3: i2c@40005c00 { 364 compatible = "st,stm32f7-i2c"; 365 reg = <0x40005c00 0x400>; 366 interrupts = <72>, 367 <73>; 368 resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 369 clocks = <&rcc 1 CLK_I2C3>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2c4: i2c@40006000 { 376 compatible = "st,stm32f7-i2c"; 377 reg = <0x40006000 0x400>; 378 interrupts = <95>, 379 <96>; 380 resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 381 clocks = <&rcc 1 CLK_I2C4>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 387 cec: cec@40006c00 { 388 compatible = "st,stm32-cec"; 389 reg = <0x40006C00 0x400>; 390 interrupts = <94>; 391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 392 clock-names = "cec", "hdmi-cec"; 393 status = "disabled"; 394 }; 395 396 usart7: serial@40007800 { 397 compatible = "st,stm32f7-uart"; 398 reg = <0x40007800 0x400>; 399 interrupts = <82>; 400 clocks = <&rcc 1 CLK_UART7>; 401 status = "disabled"; 402 }; 403 404 usart8: serial@40007c00 { 405 compatible = "st,stm32f7-uart"; 406 reg = <0x40007c00 0x400>; 407 interrupts = <83>; 408 clocks = <&rcc 1 CLK_UART8>; 409 status = "disabled"; 410 }; 411 412 timers1: timers@40010000 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 compatible = "st,stm32-timers"; 416 reg = <0x40010000 0x400>; 417 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 418 clock-names = "int"; 419 status = "disabled"; 420 421 pwm { 422 compatible = "st,stm32-pwm"; 423 #pwm-cells = <3>; 424 status = "disabled"; 425 }; 426 427 timer@0 { 428 compatible = "st,stm32-timer-trigger"; 429 reg = <0>; 430 status = "disabled"; 431 }; 432 }; 433 434 timers8: timers@40010400 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 compatible = "st,stm32-timers"; 438 reg = <0x40010400 0x400>; 439 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 440 clock-names = "int"; 441 status = "disabled"; 442 443 pwm { 444 compatible = "st,stm32-pwm"; 445 #pwm-cells = <3>; 446 status = "disabled"; 447 }; 448 449 timer@7 { 450 compatible = "st,stm32-timer-trigger"; 451 reg = <7>; 452 status = "disabled"; 453 }; 454 }; 455 456 usart1: serial@40011000 { 457 compatible = "st,stm32f7-uart"; 458 reg = <0x40011000 0x400>; 459 interrupts = <37>; 460 clocks = <&rcc 1 CLK_USART1>; 461 status = "disabled"; 462 }; 463 464 usart6: serial@40011400 { 465 compatible = "st,stm32f7-uart"; 466 reg = <0x40011400 0x400>; 467 interrupts = <71>; 468 clocks = <&rcc 1 CLK_USART6>; 469 status = "disabled"; 470 }; 471 472 sdio2: mmc@40011c00 { 473 compatible = "arm,pl180", "arm,primecell"; 474 arm,primecell-periphid = <0x00880180>; 475 reg = <0x40011c00 0x400>; 476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 477 clock-names = "apb_pclk"; 478 interrupts = <103>; 479 max-frequency = <48000000>; 480 status = "disabled"; 481 }; 482 483 sdio1: mmc@40012c00 { 484 compatible = "arm,pl180", "arm,primecell"; 485 arm,primecell-periphid = <0x00880180>; 486 reg = <0x40012c00 0x400>; 487 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 488 clock-names = "apb_pclk"; 489 interrupts = <49>; 490 max-frequency = <48000000>; 491 status = "disabled"; 492 }; 493 494 syscfg: syscon@40013800 { 495 compatible = "st,stm32-syscfg", "syscon"; 496 reg = <0x40013800 0x400>; 497 }; 498 499 exti: interrupt-controller@40013c00 { 500 compatible = "st,stm32-exti"; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 reg = <0x40013C00 0x400>; 504 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 505 }; 506 507 timers9: timers@40014000 { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 compatible = "st,stm32-timers"; 511 reg = <0x40014000 0x400>; 512 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 513 clock-names = "int"; 514 status = "disabled"; 515 516 pwm { 517 compatible = "st,stm32-pwm"; 518 #pwm-cells = <3>; 519 status = "disabled"; 520 }; 521 522 timer@8 { 523 compatible = "st,stm32-timer-trigger"; 524 reg = <8>; 525 status = "disabled"; 526 }; 527 }; 528 529 timers10: timers@40014400 { 530 compatible = "st,stm32-timers"; 531 reg = <0x40014400 0x400>; 532 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 533 clock-names = "int"; 534 status = "disabled"; 535 536 pwm { 537 compatible = "st,stm32-pwm"; 538 #pwm-cells = <3>; 539 status = "disabled"; 540 }; 541 }; 542 543 timers11: timers@40014800 { 544 compatible = "st,stm32-timers"; 545 reg = <0x40014800 0x400>; 546 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 547 clock-names = "int"; 548 status = "disabled"; 549 550 pwm { 551 compatible = "st,stm32-pwm"; 552 #pwm-cells = <3>; 553 status = "disabled"; 554 }; 555 }; 556 557 pwrcfg: power-config@40007000 { 558 compatible = "st,stm32-power-config", "syscon"; 559 reg = <0x40007000 0x400>; 560 }; 561 562 crc: crc@40023000 { 563 compatible = "st,stm32f7-crc"; 564 reg = <0x40023000 0x400>; 565 clocks = <&rcc 0 12>; 566 status = "disabled"; 567 }; 568 569 rcc: rcc@40023800 { 570 #reset-cells = <1>; 571 #clock-cells = <2>; 572 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 573 reg = <0x40023800 0x400>; 574 clocks = <&clk_hse>, <&clk_i2s_ckin>; 575 st,syscfg = <&pwrcfg>; 576 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 577 assigned-clock-rates = <1000000>; 578 }; 579 580 dma1: dma-controller@40026000 { 581 compatible = "st,stm32-dma"; 582 reg = <0x40026000 0x400>; 583 interrupts = <11>, 584 <12>, 585 <13>, 586 <14>, 587 <15>, 588 <16>, 589 <17>, 590 <47>; 591 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 592 #dma-cells = <4>; 593 status = "disabled"; 594 }; 595 596 dma2: dma-controller@40026400 { 597 compatible = "st,stm32-dma"; 598 reg = <0x40026400 0x400>; 599 interrupts = <56>, 600 <57>, 601 <58>, 602 <59>, 603 <60>, 604 <68>, 605 <69>, 606 <70>; 607 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 608 #dma-cells = <4>; 609 st,mem2mem; 610 status = "disabled"; 611 }; 612 613 usbotg_hs: usb@40040000 { 614 compatible = "st,stm32f7-hsotg"; 615 reg = <0x40040000 0x40000>; 616 interrupts = <77>; 617 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 618 clock-names = "otg"; 619 g-rx-fifo-size = <256>; 620 g-np-tx-fifo-size = <32>; 621 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 622 status = "disabled"; 623 }; 624 625 usbotg_fs: usb@50000000 { 626 compatible = "st,stm32f4x9-fsotg"; 627 reg = <0x50000000 0x40000>; 628 interrupts = <67>; 629 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 630 clock-names = "otg"; 631 status = "disabled"; 632 }; 633 }; 634 }; 635 636 &systick { 637 clocks = <&rcc 1 0>; 638 status = "okay"; 639 }; 640
Indexes created Thu Sep 25 16:09:42 GMT 2025