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      1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2 /*
      3  * Device Tree file for Freescale LS2080a RDB Board.
      4  *
      5  * Copyright 2016 Freescale Semiconductor, Inc.
      6  * Copyright 2017 NXP
      7  *
      8  * Abhimanyu Saini <abhimanyu.saini (a] nxp.com>
      9  * Bhupesh Sharma <bhupesh.sharma (a] freescale.com>
     10  *
     11  */
     12 
     13 /dts-v1/;
     14 
     15 #include "fsl-ls2080a.dtsi"
     16 #include "fsl-ls208xa-rdb.dtsi"
     17 #include <dt-bindings/interrupt-controller/arm-gic.h>
     18 
     19 / {
     20 	model = "Freescale Layerscape 2080a RDB Board";
     21 	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
     22 
     23 	chosen {
     24 		stdout-path = "serial1:115200n8";
     25 	};
     26 };
     27 
     28 &dpmac5 {
     29 	phy-handle = <&mdio2_phy1>;
     30 	phy-connection-type = "10gbase-r";
     31 };
     32 
     33 &dpmac6 {
     34 	phy-handle = <&mdio2_phy2>;
     35 	phy-connection-type = "10gbase-r";
     36 };
     37 
     38 &dpmac7 {
     39 	phy-handle = <&mdio2_phy3>;
     40 	phy-connection-type = "10gbase-r";
     41 };
     42 
     43 &dpmac8 {
     44 	phy-handle = <&mdio2_phy4>;
     45 	phy-connection-type = "10gbase-r";
     46 };
     47 
     48 &emdio1 {
     49 	status = "disabled";
     50 
     51 	/* CS4340 PHYs */
     52 	mdio1_phy1: emdio1-phy@10 {
     53 		reg = <0x10>;
     54 	};
     55 
     56 	mdio1_phy2: emdio1-phy@11 {
     57 		reg = <0x11>;
     58 	};
     59 
     60 	mdio1_phy3: emdio1-phy@12 {
     61 		reg = <0x12>;
     62 	};
     63 
     64 	mdio1_phy4: emdio1-phy@13 {
     65 		reg = <0x13>;
     66 	};
     67 };
     68 
     69 &emdio2 {
     70 	/* AQR405 PHYs */
     71 	mdio2_phy1: emdio2-phy@0 {
     72 		compatible = "ethernet-phy-ieee802.3-c45";
     73 		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
     74 		reg = <0x0>;
     75 	};
     76 
     77 	mdio2_phy2: emdio2-phy@1 {
     78 		compatible = "ethernet-phy-ieee802.3-c45";
     79 		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
     80 		reg = <0x1>;
     81 	};
     82 
     83 	mdio2_phy3: emdio2-phy@2 {
     84 		compatible = "ethernet-phy-ieee802.3-c45";
     85 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
     86 		reg = <0x2>;
     87 	};
     88 
     89 	mdio2_phy4: emdio2-phy@3 {
     90 		compatible = "ethernet-phy-ieee802.3-c45";
     91 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
     92 		reg = <0x3>;
     93 	};
     94 };
     95