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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * Copyright 2018-2020 NXP
      4  *	Dong Aisheng <aisheng.dong (a] nxp.com>
      5  */
      6 
      7 #include <dt-bindings/clock/imx8-lpcg.h>
      8 #include <dt-bindings/firmware/imx/rsrc.h>
      9 
     10 lsio_subsys: bus@5d000000 {
     11 	compatible = "simple-bus";
     12 	#address-cells = <1>;
     13 	#size-cells = <1>;
     14 	ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
     15 
     16 	lsio_mem_clk: clock-lsio-mem {
     17 		compatible = "fixed-clock";
     18 		#clock-cells = <0>;
     19 		clock-frequency = <200000000>;
     20 		clock-output-names = "lsio_mem_clk";
     21 	};
     22 
     23 	lsio_bus_clk: clock-lsio-bus {
     24 		compatible = "fixed-clock";
     25 		#clock-cells = <0>;
     26 		clock-frequency = <100000000>;
     27 		clock-output-names = "lsio_bus_clk";
     28 	};
     29 
     30 	lsio_gpio0: gpio@5d080000 {
     31 		reg = <0x5d080000 0x10000>;
     32 		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
     33 		gpio-controller;
     34 		#gpio-cells = <2>;
     35 		interrupt-controller;
     36 		#interrupt-cells = <2>;
     37 		power-domains = <&pd IMX_SC_R_GPIO_0>;
     38 	};
     39 
     40 	lsio_gpio1: gpio@5d090000 {
     41 		reg = <0x5d090000 0x10000>;
     42 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
     43 		gpio-controller;
     44 		#gpio-cells = <2>;
     45 		interrupt-controller;
     46 		#interrupt-cells = <2>;
     47 		power-domains = <&pd IMX_SC_R_GPIO_1>;
     48 	};
     49 
     50 	lsio_gpio2: gpio@5d0a0000 {
     51 		reg = <0x5d0a0000 0x10000>;
     52 		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
     53 		gpio-controller;
     54 		#gpio-cells = <2>;
     55 		interrupt-controller;
     56 		#interrupt-cells = <2>;
     57 		power-domains = <&pd IMX_SC_R_GPIO_2>;
     58 	};
     59 
     60 	lsio_gpio3: gpio@5d0b0000 {
     61 		reg = <0x5d0b0000 0x10000>;
     62 		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
     63 		gpio-controller;
     64 		#gpio-cells = <2>;
     65 		interrupt-controller;
     66 		#interrupt-cells = <2>;
     67 		power-domains = <&pd IMX_SC_R_GPIO_3>;
     68 	};
     69 
     70 	lsio_gpio4: gpio@5d0c0000 {
     71 		reg = <0x5d0c0000 0x10000>;
     72 		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
     73 		gpio-controller;
     74 		#gpio-cells = <2>;
     75 		interrupt-controller;
     76 		#interrupt-cells = <2>;
     77 		power-domains = <&pd IMX_SC_R_GPIO_4>;
     78 	};
     79 
     80 	lsio_gpio5: gpio@5d0d0000 {
     81 		reg = <0x5d0d0000 0x10000>;
     82 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
     83 		gpio-controller;
     84 		#gpio-cells = <2>;
     85 		interrupt-controller;
     86 		#interrupt-cells = <2>;
     87 		power-domains = <&pd IMX_SC_R_GPIO_5>;
     88 	};
     89 
     90 	lsio_gpio6: gpio@5d0e0000 {
     91 		reg = <0x5d0e0000 0x10000>;
     92 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
     93 		gpio-controller;
     94 		#gpio-cells = <2>;
     95 		interrupt-controller;
     96 		#interrupt-cells = <2>;
     97 		power-domains = <&pd IMX_SC_R_GPIO_6>;
     98 	};
     99 
    100 	lsio_gpio7: gpio@5d0f0000 {
    101 		reg = <0x5d0f0000 0x10000>;
    102 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
    103 		gpio-controller;
    104 		#gpio-cells = <2>;
    105 		interrupt-controller;
    106 		#interrupt-cells = <2>;
    107 		power-domains = <&pd IMX_SC_R_GPIO_7>;
    108 	};
    109 
    110 	lsio_mu0: mailbox@5d1b0000 {
    111 		reg = <0x5d1b0000 0x10000>;
    112 		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
    113 		#mbox-cells = <2>;
    114 		status = "disabled";
    115 	};
    116 
    117 	lsio_mu1: mailbox@5d1c0000 {
    118 		reg = <0x5d1c0000 0x10000>;
    119 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
    120 		#mbox-cells = <2>;
    121 	};
    122 
    123 	lsio_mu2: mailbox@5d1d0000 {
    124 		reg = <0x5d1d0000 0x10000>;
    125 		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
    126 		#mbox-cells = <2>;
    127 		status = "disabled";
    128 	};
    129 
    130 	lsio_mu3: mailbox@5d1e0000 {
    131 		reg = <0x5d1e0000 0x10000>;
    132 		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
    133 		#mbox-cells = <2>;
    134 		status = "disabled";
    135 	};
    136 
    137 	lsio_mu4: mailbox@5d1f0000 {
    138 		reg = <0x5d1f0000 0x10000>;
    139 		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
    140 		#mbox-cells = <2>;
    141 		status = "disabled";
    142 	};
    143 
    144 	lsio_mu13: mailbox@5d280000 {
    145 		reg = <0x5d280000 0x10000>;
    146 		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
    147 		#mbox-cells = <2>;
    148 		power-domains = <&pd IMX_SC_R_MU_13A>;
    149 	};
    150 
    151 	/* LPCG clocks */
    152 	pwm0_lpcg: clock-controller@5d400000 {
    153 		compatible = "fsl,imx8qxp-lpcg";
    154 		reg = <0x5d400000 0x10000>;
    155 		#clock-cells = <1>;
    156 		clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
    157 			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
    158 			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
    159 			 <&lsio_bus_clk>,
    160 			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
    161 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    162 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    163 				<IMX_LPCG_CLK_6>;
    164 		clock-output-names = "pwm0_lpcg_ipg_clk",
    165 				     "pwm0_lpcg_ipg_hf_clk",
    166 				     "pwm0_lpcg_ipg_s_clk",
    167 				     "pwm0_lpcg_ipg_slv_clk",
    168 				     "pwm0_lpcg_ipg_mstr_clk";
    169 		power-domains = <&pd IMX_SC_R_PWM_0>;
    170 	};
    171 
    172 	pwm1_lpcg: clock-controller@5d410000 {
    173 		compatible = "fsl,imx8qxp-lpcg";
    174 		reg = <0x5d410000 0x10000>;
    175 		#clock-cells = <1>;
    176 		clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
    177 			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
    178 			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
    179 			 <&lsio_bus_clk>,
    180 			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
    181 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    182 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    183 				<IMX_LPCG_CLK_6>;
    184 		clock-output-names = "pwm1_lpcg_ipg_clk",
    185 				     "pwm1_lpcg_ipg_hf_clk",
    186 				     "pwm1_lpcg_ipg_s_clk",
    187 				     "pwm1_lpcg_ipg_slv_clk",
    188 				     "pwm1_lpcg_ipg_mstr_clk";
    189 		power-domains = <&pd IMX_SC_R_PWM_1>;
    190 	};
    191 
    192 	pwm2_lpcg: clock-controller@5d420000 {
    193 		compatible = "fsl,imx8qxp-lpcg";
    194 		reg = <0x5d420000 0x10000>;
    195 		#clock-cells = <1>;
    196 		clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
    197 			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
    198 			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
    199 			 <&lsio_bus_clk>,
    200 			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
    201 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    202 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    203 				<IMX_LPCG_CLK_6>;
    204 		clock-output-names = "pwm2_lpcg_ipg_clk",
    205 				     "pwm2_lpcg_ipg_hf_clk",
    206 				     "pwm2_lpcg_ipg_s_clk",
    207 				     "pwm2_lpcg_ipg_slv_clk",
    208 				     "pwm2_lpcg_ipg_mstr_clk";
    209 		power-domains = <&pd IMX_SC_R_PWM_2>;
    210 	};
    211 
    212 	pwm3_lpcg: clock-controller@5d430000 {
    213 		compatible = "fsl,imx8qxp-lpcg";
    214 		reg = <0x5d430000 0x10000>;
    215 		#clock-cells = <1>;
    216 		clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
    217 			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
    218 			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
    219 			 <&lsio_bus_clk>,
    220 			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
    221 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    222 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    223 				<IMX_LPCG_CLK_6>;
    224 		clock-output-names = "pwm3_lpcg_ipg_clk",
    225 				     "pwm3_lpcg_ipg_hf_clk",
    226 				     "pwm3_lpcg_ipg_s_clk",
    227 				     "pwm3_lpcg_ipg_slv_clk",
    228 				     "pwm3_lpcg_ipg_mstr_clk";
    229 		power-domains = <&pd IMX_SC_R_PWM_3>;
    230 	};
    231 
    232 	pwm4_lpcg: clock-controller@5d440000 {
    233 		compatible = "fsl,imx8qxp-lpcg";
    234 		reg = <0x5d440000 0x10000>;
    235 		#clock-cells = <1>;
    236 		clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
    237 			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
    238 			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
    239 			 <&lsio_bus_clk>,
    240 			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
    241 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    242 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    243 				<IMX_LPCG_CLK_6>;
    244 		clock-output-names = "pwm4_lpcg_ipg_clk",
    245 				     "pwm4_lpcg_ipg_hf_clk",
    246 				     "pwm4_lpcg_ipg_s_clk",
    247 				     "pwm4_lpcg_ipg_slv_clk",
    248 				     "pwm4_lpcg_ipg_mstr_clk";
    249 		power-domains = <&pd IMX_SC_R_PWM_4>;
    250 	};
    251 
    252 	pwm5_lpcg: clock-controller@5d450000 {
    253 		compatible = "fsl,imx8qxp-lpcg";
    254 		reg = <0x5d450000 0x10000>;
    255 		#clock-cells = <1>;
    256 		clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
    257 			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
    258 			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
    259 			 <&lsio_bus_clk>,
    260 			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
    261 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    262 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    263 				<IMX_LPCG_CLK_6>;
    264 		clock-output-names = "pwm5_lpcg_ipg_clk",
    265 				     "pwm5_lpcg_ipg_hf_clk",
    266 				     "pwm5_lpcg_ipg_s_clk",
    267 				     "pwm5_lpcg_ipg_slv_clk",
    268 				     "pwm5_lpcg_ipg_mstr_clk";
    269 		power-domains = <&pd IMX_SC_R_PWM_5>;
    270 	};
    271 
    272 	pwm6_lpcg: clock-controller@5d460000 {
    273 		compatible = "fsl,imx8qxp-lpcg";
    274 		reg = <0x5d460000 0x10000>;
    275 		#clock-cells = <1>;
    276 		clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
    277 			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
    278 			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
    279 			 <&lsio_bus_clk>,
    280 			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
    281 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    282 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    283 				<IMX_LPCG_CLK_6>;
    284 		clock-output-names = "pwm6_lpcg_ipg_clk",
    285 				     "pwm6_lpcg_ipg_hf_clk",
    286 				     "pwm6_lpcg_ipg_s_clk",
    287 				     "pwm6_lpcg_ipg_slv_clk",
    288 				     "pwm6_lpcg_ipg_mstr_clk";
    289 		power-domains = <&pd IMX_SC_R_PWM_6>;
    290 	};
    291 
    292 	pwm7_lpcg: clock-controller@5d470000 {
    293 		compatible = "fsl,imx8qxp-lpcg";
    294 		reg = <0x5d470000 0x10000>;
    295 		#clock-cells = <1>;
    296 		clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
    297 			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
    298 			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
    299 			 <&lsio_bus_clk>,
    300 			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
    301 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    302 				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    303 				<IMX_LPCG_CLK_6>;
    304 		clock-output-names = "pwm7_lpcg_ipg_clk",
    305 				     "pwm7_lpcg_ipg_hf_clk",
    306 				     "pwm7_lpcg_ipg_s_clk",
    307 				     "pwm7_lpcg_ipg_slv_clk",
    308 				     "pwm7_lpcg_ipg_mstr_clk";
    309 		power-domains = <&pd IMX_SC_R_PWM_7>;
    310 	};
    311 };
    312