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      1 /*	$NetBSD: imx95-power.h,v 1.1.1.1 2026/01/18 05:24:48 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
      4 /*
      5  *  Copyright 2024 NXP
      6  */
      7 
      8 #ifndef __IMX95_POWER_H__
      9 #define __IMX95_POWER_H__
     10 
     11 #define IMX95_PD_ANA		0
     12 #define IMX95_PD_AON		1
     13 #define IMX95_PD_BBSM		2
     14 #define IMX95_PD_CAMERA		3
     15 #define IMX95_PD_CCMSRCGPC	4
     16 #define IMX95_PD_A55C0		5
     17 #define IMX95_PD_A55C1		6
     18 #define IMX95_PD_A55C2		7
     19 #define IMX95_PD_A55C3		8
     20 #define IMX95_PD_A55C4		9
     21 #define IMX95_PD_A55C5		10
     22 #define IMX95_PD_A55P		11
     23 #define IMX95_PD_DDR		12
     24 #define IMX95_PD_DISPLAY	13
     25 #define IMX95_PD_GPU		14
     26 #define IMX95_PD_HSIO_TOP	15
     27 #define IMX95_PD_HSIO_WAON	16
     28 #define IMX95_PD_M7		17
     29 #define IMX95_PD_NETC		18
     30 #define IMX95_PD_NOC		19
     31 #define IMX95_PD_NPU		20
     32 #define IMX95_PD_VPU		21
     33 #define IMX95_PD_WAKEUP		22
     34 
     35 #define IMX95_PERF_ELE		0
     36 #define IMX95_PERF_M33		1
     37 #define IMX95_PERF_WAKEUP	2
     38 #define IMX95_PERF_M7		3
     39 #define IMX95_PERF_DRAM		4
     40 #define IMX95_PERF_HSIO		5
     41 #define IMX95_PERF_NPU		6
     42 #define IMX95_PERF_NOC		7
     43 #define IMX95_PERF_A55		8
     44 #define IMX95_PERF_GPU		9
     45 #define IMX95_PERF_VPU		10
     46 #define IMX95_PERF_CAM		11
     47 #define IMX95_PERF_DISP		12
     48 
     49 #endif
     50