1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/power/r8a77995-sysc.h> 12 13 / { 14 compatible = "renesas,r8a77995"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 /* External CAN clock - to be overridden by boards that provide it */ 36 can_clk: can { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 a53_0: cpu@0 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 device_type = "cpu"; 50 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 51 next-level-cache = <&L2_CA53>; 52 enable-method = "psci"; 53 }; 54 55 L2_CA53: cache-controller-1 { 56 compatible = "cache"; 57 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 58 cache-unified; 59 cache-level = <2>; 60 }; 61 }; 62 63 extal_clk: extal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 /* This value must be overridden by the board */ 67 clock-frequency = <0>; 68 }; 69 70 pmu_a53 { 71 compatible = "arm,cortex-a53-pmu"; 72 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0", "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 scif_clk: scif { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <0>; 84 }; 85 86 soc { 87 compatible = "simple-bus"; 88 interrupt-parent = <&gic>; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 rwdt: watchdog@e6020000 { 94 compatible = "renesas,r8a77995-wdt", 95 "renesas,rcar-gen3-wdt"; 96 reg = <0 0xe6020000 0 0x0c>; 97 clocks = <&cpg CPG_MOD 402>; 98 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 99 resets = <&cpg 402>; 100 status = "disabled"; 101 }; 102 103 gpio0: gpio@e6050000 { 104 compatible = "renesas,gpio-r8a77995", 105 "renesas,rcar-gen3-gpio"; 106 reg = <0 0xe6050000 0 0x50>; 107 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 108 #gpio-cells = <2>; 109 gpio-controller; 110 gpio-ranges = <&pfc 0 0 9>; 111 #interrupt-cells = <2>; 112 interrupt-controller; 113 clocks = <&cpg CPG_MOD 912>; 114 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 115 resets = <&cpg 912>; 116 }; 117 118 gpio1: gpio@e6051000 { 119 compatible = "renesas,gpio-r8a77995", 120 "renesas,rcar-gen3-gpio"; 121 reg = <0 0xe6051000 0 0x50>; 122 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 123 #gpio-cells = <2>; 124 gpio-controller; 125 gpio-ranges = <&pfc 0 32 32>; 126 #interrupt-cells = <2>; 127 interrupt-controller; 128 clocks = <&cpg CPG_MOD 911>; 129 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 130 resets = <&cpg 911>; 131 }; 132 133 gpio2: gpio@e6052000 { 134 compatible = "renesas,gpio-r8a77995", 135 "renesas,rcar-gen3-gpio"; 136 reg = <0 0xe6052000 0 0x50>; 137 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 138 #gpio-cells = <2>; 139 gpio-controller; 140 gpio-ranges = <&pfc 0 64 32>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 clocks = <&cpg CPG_MOD 910>; 144 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 145 resets = <&cpg 910>; 146 }; 147 148 gpio3: gpio@e6053000 { 149 compatible = "renesas,gpio-r8a77995", 150 "renesas,rcar-gen3-gpio"; 151 reg = <0 0xe6053000 0 0x50>; 152 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 96 10>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&cpg CPG_MOD 909>; 159 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 160 resets = <&cpg 909>; 161 }; 162 163 gpio4: gpio@e6054000 { 164 compatible = "renesas,gpio-r8a77995", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6054000 0 0x50>; 167 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 128 32>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 908>; 174 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 175 resets = <&cpg 908>; 176 }; 177 178 gpio5: gpio@e6055000 { 179 compatible = "renesas,gpio-r8a77995", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6055000 0 0x50>; 182 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 160 21>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 907>; 189 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 190 resets = <&cpg 907>; 191 }; 192 193 gpio6: gpio@e6055400 { 194 compatible = "renesas,gpio-r8a77995", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6055400 0 0x50>; 197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 192 14>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 906>; 204 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 205 resets = <&cpg 906>; 206 }; 207 208 pfc: pinctrl@e6060000 { 209 compatible = "renesas,pfc-r8a77995"; 210 reg = <0 0xe6060000 0 0x508>; 211 }; 212 213 cmt0: timer@e60f0000 { 214 compatible = "renesas,r8a77995-cmt0", 215 "renesas,rcar-gen3-cmt0"; 216 reg = <0 0xe60f0000 0 0x1004>; 217 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cpg CPG_MOD 303>; 220 clock-names = "fck"; 221 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 222 resets = <&cpg 303>; 223 status = "disabled"; 224 }; 225 226 cmt1: timer@e6130000 { 227 compatible = "renesas,r8a77995-cmt1", 228 "renesas,rcar-gen3-cmt1"; 229 reg = <0 0xe6130000 0 0x1004>; 230 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cpg CPG_MOD 302>; 239 clock-names = "fck"; 240 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 241 resets = <&cpg 302>; 242 status = "disabled"; 243 }; 244 245 cmt2: timer@e6140000 { 246 compatible = "renesas,r8a77995-cmt1", 247 "renesas,rcar-gen3-cmt1"; 248 reg = <0 0xe6140000 0 0x1004>; 249 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cpg CPG_MOD 301>; 258 clock-names = "fck"; 259 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 260 resets = <&cpg 301>; 261 status = "disabled"; 262 }; 263 264 cmt3: timer@e6148000 { 265 compatible = "renesas,r8a77995-cmt1", 266 "renesas,rcar-gen3-cmt1"; 267 reg = <0 0xe6148000 0 0x1004>; 268 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 300>; 277 clock-names = "fck"; 278 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 279 resets = <&cpg 300>; 280 status = "disabled"; 281 }; 282 283 cpg: clock-controller@e6150000 { 284 compatible = "renesas,r8a77995-cpg-mssr"; 285 reg = <0 0xe6150000 0 0x1000>; 286 clocks = <&extal_clk>; 287 clock-names = "extal"; 288 #clock-cells = <2>; 289 #power-domain-cells = <0>; 290 #reset-cells = <1>; 291 }; 292 293 rst: reset-controller@e6160000 { 294 compatible = "renesas,r8a77995-rst"; 295 reg = <0 0xe6160000 0 0x0200>; 296 }; 297 298 sysc: system-controller@e6180000 { 299 compatible = "renesas,r8a77995-sysc"; 300 reg = <0 0xe6180000 0 0x0400>; 301 #power-domain-cells = <1>; 302 }; 303 304 thermal: thermal@e6190000 { 305 compatible = "renesas,thermal-r8a77995"; 306 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 307 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 522>; 311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 312 resets = <&cpg 522>; 313 #thermal-sensor-cells = <0>; 314 }; 315 316 intc_ex: interrupt-controller@e61c0000 { 317 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 reg = <0 0xe61c0000 0 0x200>; 321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 407>; 328 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 329 resets = <&cpg 407>; 330 }; 331 332 tmu0: timer@e61e0000 { 333 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 334 reg = <0 0xe61e0000 0 0x30>; 335 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 125>; 339 clock-names = "fck"; 340 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 341 resets = <&cpg 125>; 342 status = "disabled"; 343 }; 344 345 tmu1: timer@e6fc0000 { 346 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 347 reg = <0 0xe6fc0000 0 0x30>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 124>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 354 resets = <&cpg 124>; 355 status = "disabled"; 356 }; 357 358 tmu2: timer@e6fd0000 { 359 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 360 reg = <0 0xe6fd0000 0 0x30>; 361 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cpg CPG_MOD 123>; 365 clock-names = "fck"; 366 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 367 resets = <&cpg 123>; 368 status = "disabled"; 369 }; 370 371 tmu3: timer@e6fe0000 { 372 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 373 reg = <0 0xe6fe0000 0 0x30>; 374 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 122>; 378 clock-names = "fck"; 379 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 380 resets = <&cpg 122>; 381 status = "disabled"; 382 }; 383 384 tmu4: timer@ffc00000 { 385 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 386 reg = <0 0xffc00000 0 0x30>; 387 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 121>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 393 resets = <&cpg 121>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@e6500000 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,i2c-r8a77995", 401 "renesas,rcar-gen3-i2c"; 402 reg = <0 0xe6500000 0 0x40>; 403 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cpg CPG_MOD 931>; 405 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 406 resets = <&cpg 931>; 407 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 408 <&dmac2 0x91>, <&dmac2 0x90>; 409 dma-names = "tx", "rx", "tx", "rx"; 410 i2c-scl-internal-delay-ns = <6>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@e6508000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "renesas,i2c-r8a77995", 418 "renesas,rcar-gen3-i2c"; 419 reg = <0 0xe6508000 0 0x40>; 420 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 930>; 422 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 423 resets = <&cpg 930>; 424 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 425 <&dmac2 0x93>, <&dmac2 0x92>; 426 dma-names = "tx", "rx", "tx", "rx"; 427 i2c-scl-internal-delay-ns = <6>; 428 status = "disabled"; 429 }; 430 431 i2c2: i2c@e6510000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "renesas,i2c-r8a77995", 435 "renesas,rcar-gen3-i2c"; 436 reg = <0 0xe6510000 0 0x40>; 437 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 929>; 439 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 440 resets = <&cpg 929>; 441 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 442 <&dmac2 0x95>, <&dmac2 0x94>; 443 dma-names = "tx", "rx", "tx", "rx"; 444 i2c-scl-internal-delay-ns = <6>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@e66d0000 { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 compatible = "renesas,i2c-r8a77995", 452 "renesas,rcar-gen3-i2c"; 453 reg = <0 0xe66d0000 0 0x40>; 454 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cpg CPG_MOD 928>; 456 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 457 resets = <&cpg 928>; 458 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 459 dma-names = "tx", "rx"; 460 i2c-scl-internal-delay-ns = <6>; 461 status = "disabled"; 462 }; 463 464 hscif0: serial@e6540000 { 465 compatible = "renesas,hscif-r8a77995", 466 "renesas,rcar-gen3-hscif", 467 "renesas,hscif"; 468 reg = <0 0xe6540000 0 0x60>; 469 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 520>, 471 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 472 <&scif_clk>; 473 clock-names = "fck", "brg_int", "scif_clk"; 474 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 475 <&dmac2 0x31>, <&dmac2 0x30>; 476 dma-names = "tx", "rx", "tx", "rx"; 477 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 478 resets = <&cpg 520>; 479 status = "disabled"; 480 }; 481 482 hscif3: serial@e66a0000 { 483 compatible = "renesas,hscif-r8a77995", 484 "renesas,rcar-gen3-hscif", 485 "renesas,hscif"; 486 reg = <0 0xe66a0000 0 0x60>; 487 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cpg CPG_MOD 517>, 489 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 490 <&scif_clk>; 491 clock-names = "fck", "brg_int", "scif_clk"; 492 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 493 dma-names = "tx", "rx"; 494 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 495 resets = <&cpg 517>; 496 status = "disabled"; 497 }; 498 499 hsusb: usb@e6590000 { 500 compatible = "renesas,usbhs-r8a77995", 501 "renesas,rcar-gen3-usbhs"; 502 reg = <0 0xe6590000 0 0x200>; 503 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 505 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 506 <&usb_dmac1 0>, <&usb_dmac1 1>; 507 dma-names = "ch0", "ch1", "ch2", "ch3"; 508 renesas,buswait = <11>; 509 phys = <&usb2_phy0 3>; 510 phy-names = "usb"; 511 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 512 resets = <&cpg 704>, <&cpg 703>; 513 status = "disabled"; 514 }; 515 516 usb_dmac0: dma-controller@e65a0000 { 517 compatible = "renesas,r8a77995-usb-dmac", 518 "renesas,usb-dmac"; 519 reg = <0 0xe65a0000 0 0x100>; 520 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "ch0", "ch1"; 523 clocks = <&cpg CPG_MOD 330>; 524 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 525 resets = <&cpg 330>; 526 #dma-cells = <1>; 527 dma-channels = <2>; 528 }; 529 530 usb_dmac1: dma-controller@e65b0000 { 531 compatible = "renesas,r8a77995-usb-dmac", 532 "renesas,usb-dmac"; 533 reg = <0 0xe65b0000 0 0x100>; 534 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "ch0", "ch1"; 537 clocks = <&cpg CPG_MOD 331>; 538 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 539 resets = <&cpg 331>; 540 #dma-cells = <1>; 541 dma-channels = <2>; 542 }; 543 544 arm_cc630p: crypto@e6601000 { 545 compatible = "arm,cryptocell-630p-ree"; 546 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 547 reg = <0x0 0xe6601000 0 0x1000>; 548 clocks = <&cpg CPG_MOD 229>; 549 resets = <&cpg 229>; 550 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 551 }; 552 553 canfd: can@e66c0000 { 554 compatible = "renesas,r8a77995-canfd", 555 "renesas,rcar-gen3-canfd"; 556 reg = <0 0xe66c0000 0 0x8000>; 557 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 914>, 560 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 561 <&can_clk>; 562 clock-names = "fck", "canfd", "can_clk"; 563 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 564 assigned-clock-rates = <40000000>; 565 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 566 resets = <&cpg 914>; 567 status = "disabled"; 568 569 channel0 { 570 status = "disabled"; 571 }; 572 573 channel1 { 574 status = "disabled"; 575 }; 576 }; 577 578 dmac0: dma-controller@e6700000 { 579 compatible = "renesas,dmac-r8a77995", 580 "renesas,rcar-dmac"; 581 reg = <0 0xe6700000 0 0x10000>; 582 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "error", 592 "ch0", "ch1", "ch2", "ch3", 593 "ch4", "ch5", "ch6", "ch7"; 594 clocks = <&cpg CPG_MOD 219>; 595 clock-names = "fck"; 596 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 597 resets = <&cpg 219>; 598 #dma-cells = <1>; 599 dma-channels = <8>; 600 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 601 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 602 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 603 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; 604 }; 605 606 dmac1: dma-controller@e7300000 { 607 compatible = "renesas,dmac-r8a77995", 608 "renesas,rcar-dmac"; 609 reg = <0 0xe7300000 0 0x10000>; 610 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 619 interrupt-names = "error", 620 "ch0", "ch1", "ch2", "ch3", 621 "ch4", "ch5", "ch6", "ch7"; 622 clocks = <&cpg CPG_MOD 218>; 623 clock-names = "fck"; 624 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 625 resets = <&cpg 218>; 626 #dma-cells = <1>; 627 dma-channels = <8>; 628 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 629 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 630 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 631 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 632 }; 633 634 dmac2: dma-controller@e7310000 { 635 compatible = "renesas,dmac-r8a77995", 636 "renesas,rcar-dmac"; 637 reg = <0 0xe7310000 0 0x10000>; 638 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "error", 648 "ch0", "ch1", "ch2", "ch3", 649 "ch4", "ch5", "ch6", "ch7"; 650 clocks = <&cpg CPG_MOD 217>; 651 clock-names = "fck"; 652 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 653 resets = <&cpg 217>; 654 #dma-cells = <1>; 655 dma-channels = <8>; 656 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 657 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 658 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 659 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 660 }; 661 662 ipmmu_ds0: iommu@e6740000 { 663 compatible = "renesas,ipmmu-r8a77995"; 664 reg = <0 0xe6740000 0 0x1000>; 665 renesas,ipmmu-main = <&ipmmu_mm 0>; 666 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 667 #iommu-cells = <1>; 668 }; 669 670 ipmmu_ds1: iommu@e7740000 { 671 compatible = "renesas,ipmmu-r8a77995"; 672 reg = <0 0xe7740000 0 0x1000>; 673 renesas,ipmmu-main = <&ipmmu_mm 1>; 674 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 675 #iommu-cells = <1>; 676 }; 677 678 ipmmu_hc: iommu@e6570000 { 679 compatible = "renesas,ipmmu-r8a77995"; 680 reg = <0 0xe6570000 0 0x1000>; 681 renesas,ipmmu-main = <&ipmmu_mm 2>; 682 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 683 #iommu-cells = <1>; 684 }; 685 686 ipmmu_mm: iommu@e67b0000 { 687 compatible = "renesas,ipmmu-r8a77995"; 688 reg = <0 0xe67b0000 0 0x1000>; 689 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 691 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 692 #iommu-cells = <1>; 693 }; 694 695 ipmmu_mp: iommu@ec670000 { 696 compatible = "renesas,ipmmu-r8a77995"; 697 reg = <0 0xec670000 0 0x1000>; 698 renesas,ipmmu-main = <&ipmmu_mm 4>; 699 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 700 #iommu-cells = <1>; 701 }; 702 703 ipmmu_pv0: iommu@fd800000 { 704 compatible = "renesas,ipmmu-r8a77995"; 705 reg = <0 0xfd800000 0 0x1000>; 706 renesas,ipmmu-main = <&ipmmu_mm 6>; 707 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 708 #iommu-cells = <1>; 709 }; 710 711 ipmmu_rt: iommu@ffc80000 { 712 compatible = "renesas,ipmmu-r8a77995"; 713 reg = <0 0xffc80000 0 0x1000>; 714 renesas,ipmmu-main = <&ipmmu_mm 10>; 715 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 716 #iommu-cells = <1>; 717 }; 718 719 ipmmu_vc0: iommu@fe6b0000 { 720 compatible = "renesas,ipmmu-r8a77995"; 721 reg = <0 0xfe6b0000 0 0x1000>; 722 renesas,ipmmu-main = <&ipmmu_mm 12>; 723 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 724 #iommu-cells = <1>; 725 }; 726 727 ipmmu_vi0: iommu@febd0000 { 728 compatible = "renesas,ipmmu-r8a77995"; 729 reg = <0 0xfebd0000 0 0x1000>; 730 renesas,ipmmu-main = <&ipmmu_mm 14>; 731 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 732 #iommu-cells = <1>; 733 }; 734 735 ipmmu_vp0: iommu@fe990000 { 736 compatible = "renesas,ipmmu-r8a77995"; 737 reg = <0 0xfe990000 0 0x1000>; 738 renesas,ipmmu-main = <&ipmmu_mm 16>; 739 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 740 #iommu-cells = <1>; 741 }; 742 743 avb: ethernet@e6800000 { 744 compatible = "renesas,etheravb-r8a77995", 745 "renesas,etheravb-rcar-gen3"; 746 reg = <0 0xe6800000 0 0x800>; 747 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 772 interrupt-names = "ch0", "ch1", "ch2", "ch3", 773 "ch4", "ch5", "ch6", "ch7", 774 "ch8", "ch9", "ch10", "ch11", 775 "ch12", "ch13", "ch14", "ch15", 776 "ch16", "ch17", "ch18", "ch19", 777 "ch20", "ch21", "ch22", "ch23", 778 "ch24"; 779 clocks = <&cpg CPG_MOD 812>; 780 clock-names = "fck"; 781 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 782 resets = <&cpg 812>; 783 phy-mode = "rgmii"; 784 rx-internal-delay-ps = <1800>; 785 iommus = <&ipmmu_ds0 16>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 status = "disabled"; 789 }; 790 791 can0: can@e6c30000 { 792 compatible = "renesas,can-r8a77995", 793 "renesas,rcar-gen3-can"; 794 reg = <0 0xe6c30000 0 0x1000>; 795 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 916>, 797 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 798 <&can_clk>; 799 clock-names = "clkp1", "clkp2", "can_clk"; 800 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 801 assigned-clock-rates = <40000000>; 802 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 803 resets = <&cpg 916>; 804 status = "disabled"; 805 }; 806 807 can1: can@e6c38000 { 808 compatible = "renesas,can-r8a77995", 809 "renesas,rcar-gen3-can"; 810 reg = <0 0xe6c38000 0 0x1000>; 811 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 915>, 813 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 814 <&can_clk>; 815 clock-names = "clkp1", "clkp2", "can_clk"; 816 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 817 assigned-clock-rates = <40000000>; 818 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 819 resets = <&cpg 915>; 820 status = "disabled"; 821 }; 822 823 pwm0: pwm@e6e30000 { 824 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 825 reg = <0 0xe6e30000 0 0x8>; 826 #pwm-cells = <2>; 827 clocks = <&cpg CPG_MOD 523>; 828 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 829 resets = <&cpg 523>; 830 status = "disabled"; 831 }; 832 833 pwm1: pwm@e6e31000 { 834 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 835 reg = <0 0xe6e31000 0 0x8>; 836 #pwm-cells = <2>; 837 clocks = <&cpg CPG_MOD 523>; 838 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 839 resets = <&cpg 523>; 840 status = "disabled"; 841 }; 842 843 pwm2: pwm@e6e32000 { 844 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 845 reg = <0 0xe6e32000 0 0x8>; 846 #pwm-cells = <2>; 847 clocks = <&cpg CPG_MOD 523>; 848 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 849 resets = <&cpg 523>; 850 status = "disabled"; 851 }; 852 853 pwm3: pwm@e6e33000 { 854 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 855 reg = <0 0xe6e33000 0 0x8>; 856 #pwm-cells = <2>; 857 clocks = <&cpg CPG_MOD 523>; 858 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 859 resets = <&cpg 523>; 860 status = "disabled"; 861 }; 862 863 scif0: serial@e6e60000 { 864 compatible = "renesas,scif-r8a77995", 865 "renesas,rcar-gen3-scif", "renesas,scif"; 866 reg = <0 0xe6e60000 0 64>; 867 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cpg CPG_MOD 207>, 869 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 870 <&scif_clk>; 871 clock-names = "fck", "brg_int", "scif_clk"; 872 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 873 <&dmac2 0x51>, <&dmac2 0x50>; 874 dma-names = "tx", "rx", "tx", "rx"; 875 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 876 resets = <&cpg 207>; 877 status = "disabled"; 878 }; 879 880 scif1: serial@e6e68000 { 881 compatible = "renesas,scif-r8a77995", 882 "renesas,rcar-gen3-scif", "renesas,scif"; 883 reg = <0 0xe6e68000 0 64>; 884 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 206>, 886 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 887 <&scif_clk>; 888 clock-names = "fck", "brg_int", "scif_clk"; 889 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 890 <&dmac2 0x53>, <&dmac2 0x52>; 891 dma-names = "tx", "rx", "tx", "rx"; 892 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 893 resets = <&cpg 206>; 894 status = "disabled"; 895 }; 896 897 scif2: serial@e6e88000 { 898 compatible = "renesas,scif-r8a77995", 899 "renesas,rcar-gen3-scif", "renesas,scif"; 900 reg = <0 0xe6e88000 0 64>; 901 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD 310>, 903 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 904 <&scif_clk>; 905 clock-names = "fck", "brg_int", "scif_clk"; 906 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 907 <&dmac2 0x13>, <&dmac2 0x12>; 908 dma-names = "tx", "rx", "tx", "rx"; 909 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 910 resets = <&cpg 310>; 911 status = "disabled"; 912 }; 913 914 scif3: serial@e6c50000 { 915 compatible = "renesas,scif-r8a77995", 916 "renesas,rcar-gen3-scif", "renesas,scif"; 917 reg = <0 0xe6c50000 0 64>; 918 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 204>, 920 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 921 <&scif_clk>; 922 clock-names = "fck", "brg_int", "scif_clk"; 923 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 924 dma-names = "tx", "rx"; 925 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 926 resets = <&cpg 204>; 927 status = "disabled"; 928 }; 929 930 scif4: serial@e6c40000 { 931 compatible = "renesas,scif-r8a77995", 932 "renesas,rcar-gen3-scif", "renesas,scif"; 933 reg = <0 0xe6c40000 0 64>; 934 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cpg CPG_MOD 203>, 936 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 937 <&scif_clk>; 938 clock-names = "fck", "brg_int", "scif_clk"; 939 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 940 dma-names = "tx", "rx"; 941 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 942 resets = <&cpg 203>; 943 status = "disabled"; 944 }; 945 946 scif5: serial@e6f30000 { 947 compatible = "renesas,scif-r8a77995", 948 "renesas,rcar-gen3-scif", "renesas,scif"; 949 reg = <0 0xe6f30000 0 64>; 950 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cpg CPG_MOD 202>, 952 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 953 <&scif_clk>; 954 clock-names = "fck", "brg_int", "scif_clk"; 955 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 956 <&dmac2 0x5b>, <&dmac2 0x5a>; 957 dma-names = "tx", "rx", "tx", "rx"; 958 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 959 resets = <&cpg 202>; 960 status = "disabled"; 961 }; 962 963 msiof0: spi@e6e90000 { 964 compatible = "renesas,msiof-r8a77995", 965 "renesas,rcar-gen3-msiof"; 966 reg = <0 0xe6e90000 0 0x64>; 967 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&cpg CPG_MOD 211>; 969 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 970 <&dmac2 0x41>, <&dmac2 0x40>; 971 dma-names = "tx", "rx", "tx", "rx"; 972 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 973 resets = <&cpg 211>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 msiof1: spi@e6ea0000 { 980 compatible = "renesas,msiof-r8a77995", 981 "renesas,rcar-gen3-msiof"; 982 reg = <0 0xe6ea0000 0 0x64>; 983 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cpg CPG_MOD 210>; 985 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 986 <&dmac2 0x43>, <&dmac2 0x42>; 987 dma-names = "tx", "rx", "tx", "rx"; 988 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 989 resets = <&cpg 210>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 msiof2: spi@e6c00000 { 996 compatible = "renesas,msiof-r8a77995", 997 "renesas,rcar-gen3-msiof"; 998 reg = <0 0xe6c00000 0 0x64>; 999 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cpg CPG_MOD 209>; 1001 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1002 dma-names = "tx", "rx"; 1003 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1004 resets = <&cpg 209>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 msiof3: spi@e6c10000 { 1011 compatible = "renesas,msiof-r8a77995", 1012 "renesas,rcar-gen3-msiof"; 1013 reg = <0 0xe6c10000 0 0x64>; 1014 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cpg CPG_MOD 208>; 1016 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1017 dma-names = "tx", "rx"; 1018 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1019 resets = <&cpg 208>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 vin4: video@e6ef4000 { 1026 compatible = "renesas,vin-r8a77995"; 1027 reg = <0 0xe6ef4000 0 0x1000>; 1028 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cpg CPG_MOD 807>; 1030 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1031 resets = <&cpg 807>; 1032 renesas,id = <4>; 1033 status = "disabled"; 1034 }; 1035 1036 rcar_sound: sound@ec500000 { 1037 /* 1038 * #sound-dai-cells is required 1039 * 1040 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1041 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1042 */ 1043 /* 1044 * #clock-cells is required for audio_clkout0/1/2/3 1045 * 1046 * clkout : #clock-cells = <0>; <&rcar_sound>; 1047 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1048 */ 1049 compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; 1050 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1051 <0 0xec5a0000 0 0x100>, /* ADG */ 1052 <0 0xec540000 0 0x1000>, /* SSIU */ 1053 <0 0xec541000 0 0x280>, /* SSI */ 1054 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1055 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1056 1057 clocks = <&cpg CPG_MOD 1005>, 1058 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, 1059 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, 1060 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1061 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1062 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1063 <&audio_clk_a>, <&audio_clk_b>, 1064 <&cpg CPG_CORE R8A77995_CLK_ZA2>; 1065 clock-names = "ssi-all", 1066 "ssi.4", "ssi.3", 1067 "src.6", "src.5", 1068 "mix.1", "mix.0", 1069 "ctu.1", "ctu.0", 1070 "dvc.0", "dvc.1", 1071 "clk_a", "clk_b", "clk_i"; 1072 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1073 resets = <&cpg 1005>, 1074 <&cpg 1011>, <&cpg 1012>; 1075 reset-names = "ssi-all", 1076 "ssi.4", "ssi.3"; 1077 status = "disabled"; 1078 1079 rcar_sound,ctu { 1080 ctu00: ctu-0 { }; 1081 ctu01: ctu-1 { }; 1082 ctu02: ctu-2 { }; 1083 ctu03: ctu-3 { }; 1084 ctu10: ctu-4 { }; 1085 ctu11: ctu-5 { }; 1086 ctu12: ctu-6 { }; 1087 ctu13: ctu-7 { }; 1088 }; 1089 1090 rcar_sound,dvc { 1091 dvc0: dvc-0 { 1092 dmas = <&audma0 0xbc>; 1093 dma-names = "tx"; 1094 }; 1095 dvc1: dvc-1 { 1096 dmas = <&audma0 0xbe>; 1097 dma-names = "tx"; 1098 }; 1099 }; 1100 1101 rcar_sound,mix { 1102 mix0: mix-0 { }; 1103 mix1: mix-1 { }; 1104 }; 1105 1106 rcar_sound,src { 1107 src5: src-5 { 1108 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1109 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1110 dma-names = "rx", "tx"; 1111 }; 1112 src6: src-6 { 1113 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1114 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1115 dma-names = "rx", "tx"; 1116 }; 1117 }; 1118 1119 rcar_sound,ssi { 1120 ssi3: ssi-3 { 1121 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1122 dmas = <&audma0 0x07>, <&audma0 0x08>, 1123 <&audma0 0x6f>, <&audma0 0x70>; 1124 dma-names = "rx", "tx", "rxu", "txu"; 1125 }; 1126 ssi4: ssi-4 { 1127 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1128 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1129 <&audma0 0x71>, <&audma0 0x72>; 1130 dma-names = "rx", "tx", "rxu", "txu"; 1131 }; 1132 }; 1133 }; 1134 1135 audma0: dma-controller@ec700000 { 1136 compatible = "renesas,dmac-r8a77995", 1137 "renesas,rcar-dmac"; 1138 reg = <0 0xec700000 0 0x10000>; 1139 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1156 interrupt-names = "error", 1157 "ch0", "ch1", "ch2", "ch3", 1158 "ch4", "ch5", "ch6", "ch7", 1159 "ch8", "ch9", "ch10", "ch11", 1160 "ch12", "ch13", "ch14", "ch15"; 1161 clocks = <&cpg CPG_MOD 502>; 1162 clock-names = "fck"; 1163 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1164 resets = <&cpg 502>; 1165 #dma-cells = <1>; 1166 dma-channels = <16>; 1167 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1168 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1169 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1170 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1171 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1172 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1173 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1174 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1175 }; 1176 1177 ohci0: usb@ee080000 { 1178 compatible = "generic-ohci"; 1179 reg = <0 0xee080000 0 0x100>; 1180 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1182 phys = <&usb2_phy0 1>; 1183 phy-names = "usb"; 1184 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1185 resets = <&cpg 703>, <&cpg 704>; 1186 status = "disabled"; 1187 }; 1188 1189 ehci0: usb@ee080100 { 1190 compatible = "generic-ehci"; 1191 reg = <0 0xee080100 0 0x100>; 1192 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1194 phys = <&usb2_phy0 2>; 1195 phy-names = "usb"; 1196 companion = <&ohci0>; 1197 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1198 resets = <&cpg 703>, <&cpg 704>; 1199 status = "disabled"; 1200 }; 1201 1202 usb2_phy0: usb-phy@ee080200 { 1203 compatible = "renesas,usb2-phy-r8a77995", 1204 "renesas,rcar-gen3-usb2-phy"; 1205 reg = <0 0xee080200 0 0x700>; 1206 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1208 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1209 resets = <&cpg 703>, <&cpg 704>; 1210 #phy-cells = <1>; 1211 status = "disabled"; 1212 }; 1213 1214 sdhi2: mmc@ee140000 { 1215 compatible = "renesas,sdhi-r8a77995", 1216 "renesas,rcar-gen3-sdhi"; 1217 reg = <0 0xee140000 0 0x2000>; 1218 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&cpg CPG_MOD 312>; 1220 max-frequency = <200000000>; 1221 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1222 resets = <&cpg 312>; 1223 iommus = <&ipmmu_ds1 34>; 1224 status = "disabled"; 1225 }; 1226 1227 gic: interrupt-controller@f1010000 { 1228 compatible = "arm,gic-400"; 1229 #interrupt-cells = <3>; 1230 #address-cells = <0>; 1231 interrupt-controller; 1232 reg = <0x0 0xf1010000 0 0x1000>, 1233 <0x0 0xf1020000 0 0x20000>, 1234 <0x0 0xf1040000 0 0x20000>, 1235 <0x0 0xf1060000 0 0x20000>; 1236 interrupts = <GIC_PPI 9 1237 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 1238 clocks = <&cpg CPG_MOD 408>; 1239 clock-names = "clk"; 1240 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1241 resets = <&cpg 408>; 1242 }; 1243 1244 vspbs: vsp@fe960000 { 1245 compatible = "renesas,vsp2"; 1246 reg = <0 0xfe960000 0 0x8000>; 1247 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&cpg CPG_MOD 627>; 1249 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1250 resets = <&cpg 627>; 1251 renesas,fcp = <&fcpvb0>; 1252 }; 1253 1254 vspd0: vsp@fea20000 { 1255 compatible = "renesas,vsp2"; 1256 reg = <0 0xfea20000 0 0x5000>; 1257 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&cpg CPG_MOD 623>; 1259 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1260 resets = <&cpg 623>; 1261 renesas,fcp = <&fcpvd0>; 1262 }; 1263 1264 vspd1: vsp@fea28000 { 1265 compatible = "renesas,vsp2"; 1266 reg = <0 0xfea28000 0 0x5000>; 1267 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&cpg CPG_MOD 622>; 1269 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1270 resets = <&cpg 622>; 1271 renesas,fcp = <&fcpvd1>; 1272 }; 1273 1274 fcpvb0: fcp@fe96f000 { 1275 compatible = "renesas,fcpv"; 1276 reg = <0 0xfe96f000 0 0x200>; 1277 clocks = <&cpg CPG_MOD 607>; 1278 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1279 resets = <&cpg 607>; 1280 iommus = <&ipmmu_vp0 5>; 1281 }; 1282 1283 fcpvd0: fcp@fea27000 { 1284 compatible = "renesas,fcpv"; 1285 reg = <0 0xfea27000 0 0x200>; 1286 clocks = <&cpg CPG_MOD 603>; 1287 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1288 resets = <&cpg 603>; 1289 iommus = <&ipmmu_vi0 8>; 1290 }; 1291 1292 fcpvd1: fcp@fea2f000 { 1293 compatible = "renesas,fcpv"; 1294 reg = <0 0xfea2f000 0 0x200>; 1295 clocks = <&cpg CPG_MOD 602>; 1296 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1297 resets = <&cpg 602>; 1298 iommus = <&ipmmu_vi0 9>; 1299 }; 1300 1301 cmm0: cmm@fea40000 { 1302 compatible = "renesas,r8a77995-cmm", 1303 "renesas,rcar-gen3-cmm"; 1304 reg = <0 0xfea40000 0 0x1000>; 1305 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1306 clocks = <&cpg CPG_MOD 711>; 1307 resets = <&cpg 711>; 1308 }; 1309 1310 cmm1: cmm@fea50000 { 1311 compatible = "renesas,r8a77995-cmm", 1312 "renesas,rcar-gen3-cmm"; 1313 reg = <0 0xfea50000 0 0x1000>; 1314 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1315 clocks = <&cpg CPG_MOD 710>; 1316 resets = <&cpg 710>; 1317 }; 1318 1319 du: display@feb00000 { 1320 compatible = "renesas,du-r8a77995"; 1321 reg = <0 0xfeb00000 0 0x40000>; 1322 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1325 clock-names = "du.0", "du.1"; 1326 resets = <&cpg 724>; 1327 reset-names = "du.0"; 1328 1329 renesas,cmms = <&cmm0>, <&cmm1>; 1330 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1331 1332 status = "disabled"; 1333 1334 ports { 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 1338 port@0 { 1339 reg = <0>; 1340 du_out_rgb: endpoint { 1341 }; 1342 }; 1343 1344 port@1 { 1345 reg = <1>; 1346 du_out_lvds0: endpoint { 1347 remote-endpoint = <&lvds0_in>; 1348 }; 1349 }; 1350 1351 port@2 { 1352 reg = <2>; 1353 du_out_lvds1: endpoint { 1354 remote-endpoint = <&lvds1_in>; 1355 }; 1356 }; 1357 }; 1358 }; 1359 1360 lvds0: lvds-encoder@feb90000 { 1361 compatible = "renesas,r8a77995-lvds"; 1362 reg = <0 0xfeb90000 0 0x20>; 1363 clocks = <&cpg CPG_MOD 727>; 1364 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1365 resets = <&cpg 727>; 1366 status = "disabled"; 1367 1368 renesas,companion = <&lvds1>; 1369 1370 ports { 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 1374 port@0 { 1375 reg = <0>; 1376 lvds0_in: endpoint { 1377 remote-endpoint = <&du_out_lvds0>; 1378 }; 1379 }; 1380 1381 port@1 { 1382 reg = <1>; 1383 lvds0_out: endpoint { 1384 }; 1385 }; 1386 }; 1387 }; 1388 1389 lvds1: lvds-encoder@feb90100 { 1390 compatible = "renesas,r8a77995-lvds"; 1391 reg = <0 0xfeb90100 0 0x20>; 1392 clocks = <&cpg CPG_MOD 727>; 1393 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1394 resets = <&cpg 726>; 1395 status = "disabled"; 1396 1397 ports { 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 1401 port@0 { 1402 reg = <0>; 1403 lvds1_in: endpoint { 1404 remote-endpoint = <&du_out_lvds1>; 1405 }; 1406 }; 1407 1408 port@1 { 1409 reg = <1>; 1410 lvds1_out: endpoint { 1411 }; 1412 }; 1413 }; 1414 }; 1415 1416 prr: chipid@fff00044 { 1417 compatible = "renesas,prr"; 1418 reg = <0 0xfff00044 0 4>; 1419 }; 1420 }; 1421 1422 thermal-zones { 1423 cpu_thermal: cpu-thermal { 1424 polling-delay-passive = <250>; 1425 polling-delay = <1000>; 1426 thermal-sensors = <&thermal>; 1427 1428 cooling-maps { 1429 }; 1430 1431 trips { 1432 cpu-crit { 1433 temperature = <120000>; 1434 hysteresis = <2000>; 1435 type = "critical"; 1436 }; 1437 }; 1438 }; 1439 }; 1440 1441 timer { 1442 compatible = "arm,armv8-timer"; 1443 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1444 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1445 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1446 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1447 }; 1448 }; 1449
Indexes created Tue Oct 14 21:09:58 GMT 2025