1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 / { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13 }; 14 15 &cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 58 59 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 60 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 61 62 gic_its: msi-controller@1820000 { 63 compatible = "arm,gic-v3-its"; 64 reg = <0x00 0x01820000 0x00 0x10000>; 65 socionext,synquacer-pre-its = <0x1000000 0x400000>; 66 msi-controller; 67 #msi-cells = <1>; 68 }; 69 }; 70 71 main_gpio_intr: interrupt-controller@a00000 { 72 compatible = "ti,sci-intr"; 73 reg = <0x00 0x00a00000 0x00 0x800>; 74 ti,intr-trigger-type = <1>; 75 interrupt-controller; 76 interrupt-parent = <&gic500>; 77 #interrupt-cells = <1>; 78 ti,sci = <&dmsc>; 79 ti,sci-dev-id = <131>; 80 ti,interrupt-ranges = <8 392 56>; 81 }; 82 83 main_navss: bus@30000000 { 84 compatible = "simple-mfd"; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 88 ti,sci-dev-id = <199>; 89 dma-coherent; 90 dma-ranges; 91 92 main_navss_intr: interrupt-controller@310e0000 { 93 compatible = "ti,sci-intr"; 94 reg = <0x00 0x310e0000 0x00 0x4000>; 95 ti,intr-trigger-type = <4>; 96 interrupt-controller; 97 interrupt-parent = <&gic500>; 98 #interrupt-cells = <1>; 99 ti,sci = <&dmsc>; 100 ti,sci-dev-id = <213>; 101 ti,interrupt-ranges = <0 64 64>, 102 <64 448 64>, 103 <128 672 64>; 104 }; 105 106 main_udmass_inta: msi-controller@33d00000 { 107 compatible = "ti,sci-inta"; 108 reg = <0x00 0x33d00000 0x00 0x100000>; 109 interrupt-controller; 110 #interrupt-cells = <0>; 111 interrupt-parent = <&main_navss_intr>; 112 msi-controller; 113 ti,sci = <&dmsc>; 114 ti,sci-dev-id = <209>; 115 ti,interrupt-ranges = <0 0 256>; 116 }; 117 118 secure_proxy_main: mailbox@32c00000 { 119 compatible = "ti,am654-secure-proxy"; 120 #mbox-cells = <1>; 121 reg-names = "target_data", "rt", "scfg"; 122 reg = <0x00 0x32c00000 0x00 0x100000>, 123 <0x00 0x32400000 0x00 0x100000>, 124 <0x00 0x32800000 0x00 0x100000>; 125 interrupt-names = "rx_011"; 126 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 127 }; 128 129 hwspinlock: spinlock@30e00000 { 130 compatible = "ti,am654-hwspinlock"; 131 reg = <0x00 0x30e00000 0x00 0x1000>; 132 #hwlock-cells = <1>; 133 }; 134 135 mailbox0_cluster0: mailbox@31f80000 { 136 compatible = "ti,am654-mailbox"; 137 reg = <0x00 0x31f80000 0x00 0x200>; 138 #mbox-cells = <1>; 139 ti,mbox-num-users = <4>; 140 ti,mbox-num-fifos = <16>; 141 interrupt-parent = <&main_navss_intr>; 142 }; 143 144 mailbox0_cluster1: mailbox@31f81000 { 145 compatible = "ti,am654-mailbox"; 146 reg = <0x00 0x31f81000 0x00 0x200>; 147 #mbox-cells = <1>; 148 ti,mbox-num-users = <4>; 149 ti,mbox-num-fifos = <16>; 150 interrupt-parent = <&main_navss_intr>; 151 }; 152 153 mailbox0_cluster2: mailbox@31f82000 { 154 compatible = "ti,am654-mailbox"; 155 reg = <0x00 0x31f82000 0x00 0x200>; 156 #mbox-cells = <1>; 157 ti,mbox-num-users = <4>; 158 ti,mbox-num-fifos = <16>; 159 interrupt-parent = <&main_navss_intr>; 160 }; 161 162 mailbox0_cluster3: mailbox@31f83000 { 163 compatible = "ti,am654-mailbox"; 164 reg = <0x00 0x31f83000 0x00 0x200>; 165 #mbox-cells = <1>; 166 ti,mbox-num-users = <4>; 167 ti,mbox-num-fifos = <16>; 168 interrupt-parent = <&main_navss_intr>; 169 }; 170 171 mailbox0_cluster4: mailbox@31f84000 { 172 compatible = "ti,am654-mailbox"; 173 reg = <0x00 0x31f84000 0x00 0x200>; 174 #mbox-cells = <1>; 175 ti,mbox-num-users = <4>; 176 ti,mbox-num-fifos = <16>; 177 interrupt-parent = <&main_navss_intr>; 178 }; 179 180 mailbox0_cluster5: mailbox@31f85000 { 181 compatible = "ti,am654-mailbox"; 182 reg = <0x00 0x31f85000 0x00 0x200>; 183 #mbox-cells = <1>; 184 ti,mbox-num-users = <4>; 185 ti,mbox-num-fifos = <16>; 186 interrupt-parent = <&main_navss_intr>; 187 }; 188 189 mailbox0_cluster6: mailbox@31f86000 { 190 compatible = "ti,am654-mailbox"; 191 reg = <0x00 0x31f86000 0x00 0x200>; 192 #mbox-cells = <1>; 193 ti,mbox-num-users = <4>; 194 ti,mbox-num-fifos = <16>; 195 interrupt-parent = <&main_navss_intr>; 196 }; 197 198 mailbox0_cluster7: mailbox@31f87000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f87000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 }; 206 207 mailbox0_cluster8: mailbox@31f88000 { 208 compatible = "ti,am654-mailbox"; 209 reg = <0x00 0x31f88000 0x00 0x200>; 210 #mbox-cells = <1>; 211 ti,mbox-num-users = <4>; 212 ti,mbox-num-fifos = <16>; 213 interrupt-parent = <&main_navss_intr>; 214 }; 215 216 mailbox0_cluster9: mailbox@31f89000 { 217 compatible = "ti,am654-mailbox"; 218 reg = <0x00 0x31f89000 0x00 0x200>; 219 #mbox-cells = <1>; 220 ti,mbox-num-users = <4>; 221 ti,mbox-num-fifos = <16>; 222 interrupt-parent = <&main_navss_intr>; 223 }; 224 225 mailbox0_cluster10: mailbox@31f8a000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f8a000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 }; 233 234 mailbox0_cluster11: mailbox@31f8b000 { 235 compatible = "ti,am654-mailbox"; 236 reg = <0x00 0x31f8b000 0x00 0x200>; 237 #mbox-cells = <1>; 238 ti,mbox-num-users = <4>; 239 ti,mbox-num-fifos = <16>; 240 interrupt-parent = <&main_navss_intr>; 241 }; 242 243 main_ringacc: ringacc@3c000000 { 244 compatible = "ti,am654-navss-ringacc"; 245 reg = <0x00 0x3c000000 0x00 0x400000>, 246 <0x00 0x38000000 0x00 0x400000>, 247 <0x00 0x31120000 0x00 0x100>, 248 <0x00 0x33000000 0x00 0x40000>; 249 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 250 ti,num-rings = <1024>; 251 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 252 ti,sci = <&dmsc>; 253 ti,sci-dev-id = <211>; 254 msi-parent = <&main_udmass_inta>; 255 }; 256 257 main_udmap: dma-controller@31150000 { 258 compatible = "ti,j721e-navss-main-udmap"; 259 reg = <0x00 0x31150000 0x00 0x100>, 260 <0x00 0x34000000 0x00 0x100000>, 261 <0x00 0x35000000 0x00 0x100000>; 262 reg-names = "gcfg", "rchanrt", "tchanrt"; 263 msi-parent = <&main_udmass_inta>; 264 #dma-cells = <1>; 265 266 ti,sci = <&dmsc>; 267 ti,sci-dev-id = <212>; 268 ti,ringacc = <&main_ringacc>; 269 270 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 271 <0x0f>, /* TX_HCHAN */ 272 <0x10>; /* TX_UHCHAN */ 273 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 274 <0x0b>, /* RX_HCHAN */ 275 <0x0c>; /* RX_UHCHAN */ 276 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 277 }; 278 279 cpts@310d0000 { 280 compatible = "ti,j721e-cpts"; 281 reg = <0x00 0x310d0000 0x00 0x400>; 282 reg-names = "cpts"; 283 clocks = <&k3_clks 201 1>; 284 clock-names = "cpts"; 285 interrupts-extended = <&main_navss_intr 391>; 286 interrupt-names = "cpts"; 287 ti,cpts-periodic-outputs = <6>; 288 ti,cpts-ext-ts-inputs = <8>; 289 }; 290 }; 291 292 main_pmx0: pinctrl@11c000 { 293 compatible = "pinctrl-single"; 294 /* Proxy 0 addressing */ 295 reg = <0x00 0x11c000 0x00 0x2b4>; 296 #pinctrl-cells = <1>; 297 pinctrl-single,register-width = <32>; 298 pinctrl-single,function-mask = <0xffffffff>; 299 }; 300 301 main_uart0: serial@2800000 { 302 compatible = "ti,j721e-uart", "ti,am654-uart"; 303 reg = <0x00 0x02800000 0x00 0x100>; 304 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 305 clock-frequency = <48000000>; 306 current-speed = <115200>; 307 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 308 clocks = <&k3_clks 146 2>; 309 clock-names = "fclk"; 310 }; 311 312 main_uart1: serial@2810000 { 313 compatible = "ti,j721e-uart", "ti,am654-uart"; 314 reg = <0x00 0x02810000 0x00 0x100>; 315 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 316 clock-frequency = <48000000>; 317 current-speed = <115200>; 318 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 319 clocks = <&k3_clks 278 2>; 320 clock-names = "fclk"; 321 }; 322 323 main_uart2: serial@2820000 { 324 compatible = "ti,j721e-uart", "ti,am654-uart"; 325 reg = <0x00 0x02820000 0x00 0x100>; 326 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 327 clock-frequency = <48000000>; 328 current-speed = <115200>; 329 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 330 clocks = <&k3_clks 279 2>; 331 clock-names = "fclk"; 332 }; 333 334 main_uart3: serial@2830000 { 335 compatible = "ti,j721e-uart", "ti,am654-uart"; 336 reg = <0x00 0x02830000 0x00 0x100>; 337 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 338 clock-frequency = <48000000>; 339 current-speed = <115200>; 340 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 341 clocks = <&k3_clks 280 2>; 342 clock-names = "fclk"; 343 }; 344 345 main_uart4: serial@2840000 { 346 compatible = "ti,j721e-uart", "ti,am654-uart"; 347 reg = <0x00 0x02840000 0x00 0x100>; 348 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 349 clock-frequency = <48000000>; 350 current-speed = <115200>; 351 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 352 clocks = <&k3_clks 281 2>; 353 clock-names = "fclk"; 354 }; 355 356 main_uart5: serial@2850000 { 357 compatible = "ti,j721e-uart", "ti,am654-uart"; 358 reg = <0x00 0x02850000 0x00 0x100>; 359 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 360 clock-frequency = <48000000>; 361 current-speed = <115200>; 362 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 282 2>; 364 clock-names = "fclk"; 365 }; 366 367 main_uart6: serial@2860000 { 368 compatible = "ti,j721e-uart", "ti,am654-uart"; 369 reg = <0x00 0x02860000 0x00 0x100>; 370 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 371 clock-frequency = <48000000>; 372 current-speed = <115200>; 373 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 283 2>; 375 clock-names = "fclk"; 376 }; 377 378 main_uart7: serial@2870000 { 379 compatible = "ti,j721e-uart", "ti,am654-uart"; 380 reg = <0x00 0x02870000 0x00 0x100>; 381 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 382 clock-frequency = <48000000>; 383 current-speed = <115200>; 384 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 385 clocks = <&k3_clks 284 2>; 386 clock-names = "fclk"; 387 }; 388 389 main_uart8: serial@2880000 { 390 compatible = "ti,j721e-uart", "ti,am654-uart"; 391 reg = <0x00 0x02880000 0x00 0x100>; 392 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 393 clock-frequency = <48000000>; 394 current-speed = <115200>; 395 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 396 clocks = <&k3_clks 285 2>; 397 clock-names = "fclk"; 398 }; 399 400 main_uart9: serial@2890000 { 401 compatible = "ti,j721e-uart", "ti,am654-uart"; 402 reg = <0x00 0x02890000 0x00 0x100>; 403 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 404 clock-frequency = <48000000>; 405 current-speed = <115200>; 406 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 286 2>; 408 clock-names = "fclk"; 409 }; 410 411 main_i2c0: i2c@2000000 { 412 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 413 reg = <0x00 0x2000000 0x00 0x100>; 414 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clock-names = "fck"; 418 clocks = <&k3_clks 187 1>; 419 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 420 }; 421 422 main_i2c1: i2c@2010000 { 423 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 424 reg = <0x00 0x2010000 0x00 0x100>; 425 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clock-names = "fck"; 429 clocks = <&k3_clks 188 1>; 430 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 431 }; 432 433 main_i2c2: i2c@2020000 { 434 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 435 reg = <0x00 0x2020000 0x00 0x100>; 436 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 clock-names = "fck"; 440 clocks = <&k3_clks 189 1>; 441 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 442 }; 443 444 main_i2c3: i2c@2030000 { 445 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 446 reg = <0x00 0x2030000 0x00 0x100>; 447 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clock-names = "fck"; 451 clocks = <&k3_clks 190 1>; 452 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 453 }; 454 455 main_i2c4: i2c@2040000 { 456 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 457 reg = <0x00 0x2040000 0x00 0x100>; 458 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clock-names = "fck"; 462 clocks = <&k3_clks 191 1>; 463 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 464 }; 465 466 main_i2c5: i2c@2050000 { 467 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 468 reg = <0x00 0x2050000 0x00 0x100>; 469 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clock-names = "fck"; 473 clocks = <&k3_clks 192 1>; 474 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 475 }; 476 477 main_i2c6: i2c@2060000 { 478 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 479 reg = <0x00 0x2060000 0x00 0x100>; 480 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clock-names = "fck"; 484 clocks = <&k3_clks 193 1>; 485 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 486 }; 487 488 main_sdhci0: mmc@4f80000 { 489 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 490 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 491 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 492 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 493 clock-names = "clk_ahb", "clk_xin"; 494 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 495 ti,otap-del-sel-legacy = <0x0>; 496 ti,otap-del-sel-mmc-hs = <0x0>; 497 ti,otap-del-sel-ddr52 = <0x6>; 498 ti,otap-del-sel-hs200 = <0x8>; 499 ti,otap-del-sel-hs400 = <0x5>; 500 ti,itap-del-sel-legacy = <0x10>; 501 ti,itap-del-sel-mmc-hs = <0xa>; 502 ti,strobe-sel = <0x77>; 503 ti,clkbuf-sel = <0x7>; 504 ti,trm-icp = <0x8>; 505 bus-width = <8>; 506 mmc-ddr-1_8v; 507 mmc-hs200-1_8v; 508 mmc-hs400-1_8v; 509 dma-coherent; 510 }; 511 512 main_sdhci1: mmc@4fb0000 { 513 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 514 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 515 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 516 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 517 clock-names = "clk_ahb", "clk_xin"; 518 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 519 ti,otap-del-sel-legacy = <0x0>; 520 ti,otap-del-sel-sd-hs = <0x0>; 521 ti,otap-del-sel-sdr12 = <0xf>; 522 ti,otap-del-sel-sdr25 = <0xf>; 523 ti,otap-del-sel-sdr50 = <0xc>; 524 ti,otap-del-sel-sdr104 = <0x5>; 525 ti,otap-del-sel-ddr50 = <0xc>; 526 ti,itap-del-sel-legacy = <0x0>; 527 ti,itap-del-sel-sd-hs = <0x0>; 528 ti,itap-del-sel-sdr12 = <0x0>; 529 ti,itap-del-sel-sdr25 = <0x0>; 530 ti,clkbuf-sel = <0x7>; 531 ti,trm-icp = <0x8>; 532 dma-coherent; 533 }; 534 535 serdes_wiz0: wiz@5060000 { 536 compatible = "ti,j721e-wiz-10g"; 537 #address-cells = <1>; 538 #size-cells = <1>; 539 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 541 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 542 num-lanes = <4>; 543 #reset-cells = <1>; 544 ranges = <0x5060000 0x0 0x5060000 0x10000>; 545 546 assigned-clocks = <&k3_clks 292 85>; 547 assigned-clock-parents = <&k3_clks 292 89>; 548 549 wiz0_pll0_refclk: pll0-refclk { 550 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 551 clock-output-names = "wiz0_pll0_refclk"; 552 #clock-cells = <0>; 553 assigned-clocks = <&wiz0_pll0_refclk>; 554 assigned-clock-parents = <&k3_clks 292 85>; 555 }; 556 557 wiz0_pll1_refclk: pll1-refclk { 558 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 559 clock-output-names = "wiz0_pll1_refclk"; 560 #clock-cells = <0>; 561 assigned-clocks = <&wiz0_pll1_refclk>; 562 assigned-clock-parents = <&k3_clks 292 85>; 563 }; 564 565 wiz0_refclk_dig: refclk-dig { 566 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 567 clock-output-names = "wiz0_refclk_dig"; 568 #clock-cells = <0>; 569 assigned-clocks = <&wiz0_refclk_dig>; 570 assigned-clock-parents = <&k3_clks 292 85>; 571 }; 572 573 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 574 clocks = <&wiz0_refclk_dig>; 575 #clock-cells = <0>; 576 }; 577 578 serdes0: serdes@5060000 { 579 compatible = "ti,j721e-serdes-10g"; 580 reg = <0x05060000 0x00010000>; 581 reg-names = "torrent_phy"; 582 resets = <&serdes_wiz0 0>; 583 reset-names = "torrent_reset"; 584 clocks = <&wiz0_pll0_refclk>; 585 clock-names = "refclk"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 }; 590 591 pcie1_rc: pcie@2910000 { 592 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 593 reg = <0x00 0x02910000 0x00 0x1000>, 594 <0x00 0x02917000 0x00 0x400>, 595 <0x00 0x0d800000 0x00 0x00800000>, 596 <0x00 0x18000000 0x00 0x00001000>; 597 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 598 interrupt-names = "link_state"; 599 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 600 device_type = "pci"; 601 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 602 max-link-speed = <3>; 603 num-lanes = <4>; 604 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 605 clocks = <&k3_clks 240 6>; 606 clock-names = "fck"; 607 #address-cells = <3>; 608 #size-cells = <2>; 609 bus-range = <0x0 0xf>; 610 cdns,no-bar-match-nbits = <64>; 611 vendor-id = /bits/ 16 <0x104c>; 612 device-id = /bits/ 16 <0xb00f>; 613 msi-map = <0x0 &gic_its 0x0 0x10000>; 614 dma-coherent; 615 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 616 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 617 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 618 }; 619 620 pcie1_ep: pcie-ep@2910000 { 621 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 622 reg = <0x00 0x02910000 0x00 0x1000>, 623 <0x00 0x02917000 0x00 0x400>, 624 <0x00 0x0d800000 0x00 0x00800000>, 625 <0x00 0x18000000 0x00 0x08000000>; 626 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 627 interrupt-names = "link_state"; 628 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 629 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 630 max-link-speed = <3>; 631 num-lanes = <4>; 632 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 633 clocks = <&k3_clks 240 6>; 634 clock-names = "fck"; 635 max-functions = /bits/ 8 <6>; 636 dma-coherent; 637 }; 638 639 usbss0: cdns-usb@4104000 { 640 compatible = "ti,j721e-usb"; 641 reg = <0x00 0x4104000 0x00 0x100>; 642 dma-coherent; 643 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 644 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 645 clock-names = "ref", "lpm"; 646 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 647 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges; 651 652 usb0: usb@6000000 { 653 compatible = "cdns,usb3"; 654 reg = <0x00 0x6000000 0x00 0x10000>, 655 <0x00 0x6010000 0x00 0x10000>, 656 <0x00 0x6020000 0x00 0x10000>; 657 reg-names = "otg", "xhci", "dev"; 658 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 659 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 660 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 661 interrupt-names = "host", 662 "peripheral", 663 "otg"; 664 maximum-speed = "super-speed"; 665 dr_mode = "otg"; 666 cdns,phyrst-a-enable; 667 }; 668 }; 669 670 main_gpio0: gpio@600000 { 671 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 672 reg = <0x00 0x00600000 0x00 0x100>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 interrupt-parent = <&main_gpio_intr>; 676 interrupts = <145>, <146>, <147>, <148>, 677 <149>; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 ti,ngpio = <69>; 681 ti,davinci-gpio-unbanked = <0>; 682 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 683 clocks = <&k3_clks 105 0>; 684 clock-names = "gpio"; 685 }; 686 687 main_gpio2: gpio@610000 { 688 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 689 reg = <0x00 0x00610000 0x00 0x100>; 690 gpio-controller; 691 #gpio-cells = <2>; 692 interrupt-parent = <&main_gpio_intr>; 693 interrupts = <154>, <155>, <156>, <157>, 694 <158>; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 ti,ngpio = <69>; 698 ti,davinci-gpio-unbanked = <0>; 699 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 700 clocks = <&k3_clks 107 0>; 701 clock-names = "gpio"; 702 }; 703 704 main_gpio4: gpio@620000 { 705 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 706 reg = <0x00 0x00620000 0x00 0x100>; 707 gpio-controller; 708 #gpio-cells = <2>; 709 interrupt-parent = <&main_gpio_intr>; 710 interrupts = <163>, <164>, <165>, <166>, 711 <167>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 ti,ngpio = <69>; 715 ti,davinci-gpio-unbanked = <0>; 716 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 717 clocks = <&k3_clks 109 0>; 718 clock-names = "gpio"; 719 }; 720 721 main_gpio6: gpio@630000 { 722 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 723 reg = <0x00 0x00630000 0x00 0x100>; 724 gpio-controller; 725 #gpio-cells = <2>; 726 interrupt-parent = <&main_gpio_intr>; 727 interrupts = <172>, <173>, <174>, <175>, 728 <176>; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 ti,ngpio = <69>; 732 ti,davinci-gpio-unbanked = <0>; 733 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 734 clocks = <&k3_clks 111 0>; 735 clock-names = "gpio"; 736 }; 737 738 main_r5fss0: r5fss@5c00000 { 739 compatible = "ti,j7200-r5fss"; 740 ti,cluster-mode = <1>; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 744 <0x5d00000 0x00 0x5d00000 0x20000>; 745 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 746 747 main_r5fss0_core0: r5f@5c00000 { 748 compatible = "ti,j7200-r5f"; 749 reg = <0x5c00000 0x00010000>, 750 <0x5c10000 0x00010000>; 751 reg-names = "atcm", "btcm"; 752 ti,sci = <&dmsc>; 753 ti,sci-dev-id = <245>; 754 ti,sci-proc-ids = <0x06 0xff>; 755 resets = <&k3_reset 245 1>; 756 firmware-name = "j7200-main-r5f0_0-fw"; 757 ti,atcm-enable = <1>; 758 ti,btcm-enable = <1>; 759 ti,loczrama = <1>; 760 }; 761 762 main_r5fss0_core1: r5f@5d00000 { 763 compatible = "ti,j7200-r5f"; 764 reg = <0x5d00000 0x00008000>, 765 <0x5d10000 0x00008000>; 766 reg-names = "atcm", "btcm"; 767 ti,sci = <&dmsc>; 768 ti,sci-dev-id = <246>; 769 ti,sci-proc-ids = <0x07 0xff>; 770 resets = <&k3_reset 246 1>; 771 firmware-name = "j7200-main-r5f0_1-fw"; 772 ti,atcm-enable = <1>; 773 ti,btcm-enable = <1>; 774 ti,loczrama = <1>; 775 }; 776 }; 777 }; 778
Indexes created Fri Oct 17 00:09:41 GMT 2025