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      1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2 
      3 / {
      4 	fabric_clk3: fabric-clk3 {
      5 		compatible = "fixed-clock";
      6 		#clock-cells = <0>;
      7 		clock-frequency = <50000000>;
      8 	};
      9 
     10 	fabric_clk1: fabric-clk1 {
     11 		compatible = "fixed-clock";
     12 		#clock-cells = <0>;
     13 		clock-frequency = <125000000>;
     14 	};
     15 
     16 	fabric-bus@40000000 {
     17 		compatible = "simple-bus";
     18 		#address-cells = <2>;
     19 		#size-cells = <2>;
     20 		ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
     21 			 <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
     22 			 <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
     23 			 <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
     24 			 <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
     25 
     26 		cape_gpios_p8: gpio@41100000 {
     27 			compatible = "microchip,coregpio-rtl-v3";
     28 			reg = <0x0 0x41100000 0x0 0x1000>;
     29 			clocks = <&fabric_clk3>;
     30 			gpio-controller;
     31 			#gpio-cells = <2>;
     32 			ngpios = <16>;
     33 			gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
     34 					  "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
     35 					  "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
     36 					  "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
     37 		};
     38 
     39 		cape_gpios_p9: gpio@41200000 {
     40 			compatible = "microchip,coregpio-rtl-v3";
     41 			reg = <0x0 0x41200000 0x0 0x1000>;
     42 			clocks = <&fabric_clk3>;
     43 			gpio-controller;
     44 			#gpio-cells = <2>;
     45 			ngpios = <20>;
     46 			gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
     47 					  "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
     48 					  "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
     49 					  "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
     50 					  "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
     51 		};
     52 
     53 		hsi_gpios: gpio@44000000 {
     54 			compatible = "microchip,coregpio-rtl-v3";
     55 			reg = <0x0 0x44000000 0x0 0x1000>;
     56 			clocks = <&fabric_clk3>;
     57 			gpio-controller;
     58 			#gpio-cells = <2>;
     59 			ngpios = <20>;
     60 			gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
     61 					  "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
     62 					  "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
     63 					  "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
     64 					  "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
     65 					  "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
     66 					  "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
     67 		};
     68 	};
     69 
     70 	refclk_ccc: cccrefclk {
     71 		compatible = "fixed-clock";
     72 		#clock-cells = <0>;
     73 	};
     74 };
     75 
     76 &ccc_nw {
     77 	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
     78 		 <&refclk_ccc>, <&refclk_ccc>;
     79 	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
     80 		      "dll0_ref", "dll1_ref";
     81 	status = "okay";
     82 };
     83