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      1 /*	$NetBSD: actions,s700-cmu.h,v 1.1.1.1 2019/01/22 14:57:02 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0
      4  *
      5  * Device Tree binding constants for Actions Semi S700 Clock Management Unit
      6  *
      7  * Copyright (c) 2014 Actions Semi Inc.
      8  * Author: David Liu <liuwei (at) actions-semi.com>
      9  *
     10  * Author: Pathiban Nallathambi <pn (at) denx.de>
     11  * Author: Saravanan Sekar <sravanhome (at) gmail.com>
     12  */
     13 
     14 #ifndef __DT_BINDINGS_CLOCK_S700_H
     15 #define __DT_BINDINGS_CLOCK_S700_H
     16 
     17 #define CLK_NONE			0
     18 
     19 /* pll clocks */
     20 #define CLK_CORE_PLL			1
     21 #define CLK_DEV_PLL			2
     22 #define CLK_DDR_PLL			3
     23 #define CLK_NAND_PLL			4
     24 #define CLK_DISPLAY_PLL			5
     25 #define CLK_TVOUT_PLL			6
     26 #define CLK_CVBS_PLL			7
     27 #define CLK_AUDIO_PLL			8
     28 #define CLK_ETHERNET_PLL		9
     29 
     30 /* system clock */
     31 #define CLK_CPU				10
     32 #define CLK_DEV				11
     33 #define CLK_AHB				12
     34 #define CLK_APB				13
     35 #define CLK_DMAC			14
     36 #define CLK_NOC0_CLK_MUX		15
     37 #define CLK_NOC1_CLK_MUX		16
     38 #define CLK_HP_CLK_MUX			17
     39 #define CLK_HP_CLK_DIV			18
     40 #define CLK_NOC1_CLK_DIV		19
     41 #define CLK_NOC0			20
     42 #define CLK_NOC1			21
     43 #define CLK_SENOR_SRC			22
     44 
     45 /* peripheral device clock */
     46 #define CLK_GPIO			23
     47 #define CLK_TIMER			24
     48 #define CLK_DSI				25
     49 #define CLK_CSI				26
     50 #define CLK_SI				27
     51 #define CLK_DE				28
     52 #define CLK_HDE				29
     53 #define CLK_VDE				30
     54 #define CLK_VCE				31
     55 #define CLK_NAND			32
     56 #define CLK_SD0				33
     57 #define CLK_SD1				34
     58 #define CLK_SD2				35
     59 
     60 #define CLK_UART0			36
     61 #define CLK_UART1			37
     62 #define CLK_UART2			38
     63 #define CLK_UART3			39
     64 #define CLK_UART4			40
     65 #define CLK_UART5			41
     66 #define CLK_UART6			42
     67 
     68 #define CLK_PWM0			43
     69 #define CLK_PWM1			44
     70 #define CLK_PWM2			45
     71 #define CLK_PWM3			46
     72 #define CLK_PWM4			47
     73 #define CLK_PWM5			48
     74 #define CLK_GPU3D			49
     75 
     76 #define CLK_I2C0			50
     77 #define CLK_I2C1			51
     78 #define CLK_I2C2			52
     79 #define CLK_I2C3			53
     80 
     81 #define CLK_SPI0			54
     82 #define CLK_SPI1			55
     83 #define CLK_SPI2			56
     84 #define CLK_SPI3			57
     85 
     86 #define CLK_USB3_480MPLL0		58
     87 #define CLK_USB3_480MPHY0		59
     88 #define CLK_USB3_5GPHY			60
     89 #define CLK_USB3_CCE			61
     90 #define CLK_USB3_MAC			62
     91 
     92 #define CLK_LCD				63
     93 #define CLK_HDMI_AUDIO			64
     94 #define CLK_I2SRX			65
     95 #define CLK_I2STX			66
     96 
     97 #define CLK_SENSOR0			67
     98 #define CLK_SENSOR1			68
     99 
    100 #define CLK_HDMI_DEV			69
    101 
    102 #define CLK_ETHERNET			70
    103 #define CLK_RMII_REF			71
    104 
    105 #define CLK_USB2H0_PLLEN		72
    106 #define CLK_USB2H0_PHY			73
    107 #define CLK_USB2H0_CCE			74
    108 #define CLK_USB2H1_PLLEN		75
    109 #define CLK_USB2H1_PHY			76
    110 #define CLK_USB2H1_CCE			77
    111 
    112 #define CLK_TVOUT			78
    113 
    114 #define CLK_THERMAL_SENSOR		79
    115 
    116 #define CLK_IRC_SWITCH			80
    117 #define CLK_PCM1			81
    118 #define CLK_NR_CLKS			(CLK_PCM1 + 1)
    119 
    120 #endif /* __DT_BINDINGS_CLOCK_S700_H */
    121