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      1 /*	$NetBSD: actions,s900-cmu.h,v 1.1.1.1 2018/06/27 16:27:08 jmcneill Exp $	*/
      2 
      3 // SPDX-License-Identifier: GPL-2.0+
      4 //
      5 // Device Tree binding constants for Actions Semi S900 Clock Management Unit
      6 //
      7 // Copyright (c) 2014 Actions Semi Inc.
      8 // Copyright (c) 2018 Linaro Ltd.
      9 
     10 #ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
     11 #define __DT_BINDINGS_CLOCK_S900_CMU_H
     12 
     13 #define CLK_NONE			0
     14 
     15 /* fixed rate clocks */
     16 #define CLK_LOSC			1
     17 #define CLK_HOSC			2
     18 
     19 /* pll clocks */
     20 #define CLK_CORE_PLL			3
     21 #define CLK_DEV_PLL			4
     22 #define CLK_DDR_PLL			5
     23 #define CLK_NAND_PLL			6
     24 #define CLK_DISPLAY_PLL			7
     25 #define CLK_DSI_PLL			8
     26 #define CLK_ASSIST_PLL			9
     27 #define CLK_AUDIO_PLL			10
     28 
     29 /* system clock */
     30 #define CLK_CPU				15
     31 #define CLK_DEV				16
     32 #define CLK_NOC				17
     33 #define CLK_NOC_MUX			18
     34 #define CLK_NOC_DIV			19
     35 #define CLK_AHB				20
     36 #define CLK_APB				21
     37 #define CLK_DMAC			22
     38 
     39 /* peripheral device clock */
     40 #define CLK_GPIO			23
     41 
     42 #define CLK_BISP			24
     43 #define CLK_CSI0			25
     44 #define CLK_CSI1			26
     45 
     46 #define CLK_DE0				27
     47 #define CLK_DE1				28
     48 #define CLK_DE2				29
     49 #define CLK_DE3				30
     50 #define CLK_DSI				32
     51 
     52 #define CLK_GPU				33
     53 #define CLK_GPU_CORE			34
     54 #define CLK_GPU_MEM			35
     55 #define CLK_GPU_SYS			36
     56 
     57 #define CLK_HDE				37
     58 #define CLK_I2C0			38
     59 #define CLK_I2C1			39
     60 #define CLK_I2C2			40
     61 #define CLK_I2C3			41
     62 #define CLK_I2C4			42
     63 #define CLK_I2C5			43
     64 #define CLK_I2SRX			44
     65 #define CLK_I2STX			45
     66 #define CLK_IMX				46
     67 #define CLK_LCD				47
     68 #define CLK_NAND0			48
     69 #define CLK_NAND1			49
     70 #define CLK_PWM0			50
     71 #define CLK_PWM1			51
     72 #define CLK_PWM2			52
     73 #define CLK_PWM3			53
     74 #define CLK_PWM4			54
     75 #define CLK_PWM5			55
     76 #define CLK_SD0				56
     77 #define CLK_SD1				57
     78 #define CLK_SD2				58
     79 #define CLK_SD3				59
     80 #define CLK_SENSOR			60
     81 #define CLK_SPEED_SENSOR		61
     82 #define CLK_SPI0			62
     83 #define CLK_SPI1			63
     84 #define CLK_SPI2			64
     85 #define CLK_SPI3			65
     86 #define CLK_THERMAL_SENSOR		66
     87 #define CLK_UART0			67
     88 #define CLK_UART1			68
     89 #define CLK_UART2			69
     90 #define CLK_UART3			70
     91 #define CLK_UART4			71
     92 #define CLK_UART5			72
     93 #define CLK_UART6			73
     94 #define CLK_VCE				74
     95 #define CLK_VDE				75
     96 
     97 #define CLK_USB3_480MPLL0		76
     98 #define CLK_USB3_480MPHY0		77
     99 #define CLK_USB3_5GPHY			78
    100 #define CLK_USB3_CCE			79
    101 #define CLK_USB3_MAC			80
    102 
    103 #define CLK_TIMER			83
    104 
    105 #define CLK_HDMI_AUDIO			84
    106 
    107 #define CLK_24M				85
    108 
    109 #define CLK_EDP				86
    110 
    111 #define CLK_24M_EDP			87
    112 #define CLK_EDP_PLL			88
    113 #define CLK_EDP_LINK			89
    114 
    115 #define CLK_USB2H0_PLLEN		90
    116 #define CLK_USB2H0_PHY			91
    117 #define CLK_USB2H0_CCE			92
    118 #define CLK_USB2H1_PLLEN		93
    119 #define CLK_USB2H1_PHY			94
    120 #define CLK_USB2H1_CCE			95
    121 
    122 #define CLK_DDR0			96
    123 #define CLK_DDR1			97
    124 #define CLK_DMM				98
    125 
    126 #define CLK_ETH_MAC			99
    127 #define CLK_RMII_REF			100
    128 
    129 #define CLK_NR_CLKS			(CLK_RMII_REF + 1)
    130 
    131 #endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
    132