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      1 /*	$NetBSD: amlogic,c3-pll-clkc.h,v 1.1.1.1 2026/01/18 05:21:28 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
      4 /*
      5  * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
      6  * Author: Chuan Liu <chuan.liu (at) amlogic.com>
      7  */
      8 
      9 #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
     10 #define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
     11 
     12 #define CLKID_FCLK_50M_EN			0
     13 #define CLKID_FCLK_50M				1
     14 #define CLKID_FCLK_DIV2_DIV			2
     15 #define CLKID_FCLK_DIV2				3
     16 #define CLKID_FCLK_DIV2P5_DIV			4
     17 #define CLKID_FCLK_DIV2P5			5
     18 #define CLKID_FCLK_DIV3_DIV			6
     19 #define CLKID_FCLK_DIV3				7
     20 #define CLKID_FCLK_DIV4_DIV			8
     21 #define CLKID_FCLK_DIV4				9
     22 #define CLKID_FCLK_DIV5_DIV			10
     23 #define CLKID_FCLK_DIV5				11
     24 #define CLKID_FCLK_DIV7_DIV			12
     25 #define CLKID_FCLK_DIV7				13
     26 #define CLKID_GP0_PLL_DCO			14
     27 #define CLKID_GP0_PLL				15
     28 #define CLKID_HIFI_PLL_DCO			16
     29 #define CLKID_HIFI_PLL				17
     30 #define CLKID_MCLK_PLL_DCO			18
     31 #define CLKID_MCLK_PLL_OD			19
     32 #define CLKID_MCLK_PLL				20
     33 #define CLKID_MCLK0_SEL				21
     34 #define CLKID_MCLK0_SEL_EN			22
     35 #define CLKID_MCLK0_DIV				23
     36 #define CLKID_MCLK0				24
     37 #define CLKID_MCLK1_SEL				25
     38 #define CLKID_MCLK1_SEL_EN			26
     39 #define CLKID_MCLK1_DIV				27
     40 #define CLKID_MCLK1				28
     41 
     42 #endif  /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
     43