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      1 /*	$NetBSD: bcm-sr.h,v 1.1.1.2 2018/06/27 16:27:08 jmcneill Exp $	*/
      2 
      3 /*
      4  *  BSD LICENSE
      5  *
      6  *  Copyright(c) 2017 Broadcom. All rights reserved.
      7  *
      8  *  Redistribution and use in source and binary forms, with or without
      9  *  modification, are permitted provided that the following conditions
     10  *  are met:
     11  *
     12  *    * Redistributions of source code must retain the above copyright
     13  *      notice, this list of conditions and the following disclaimer.
     14  *    * Redistributions in binary form must reproduce the above copyright
     15  *      notice, this list of conditions and the following disclaimer in
     16  *      the documentation and/or other materials provided with the
     17  *      distribution.
     18  *    * Neither the name of Broadcom Corporation nor the names of its
     19  *      contributors may be used to endorse or promote products derived
     20  *      from this software without specific prior written permission.
     21  *
     22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33  */
     34 
     35 #ifndef _CLOCK_BCM_SR_H
     36 #define _CLOCK_BCM_SR_H
     37 
     38 /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
     39 #define BCM_SR_GENPLL0			0
     40 #define BCM_SR_GENPLL0_125M_CLK		1
     41 #define BCM_SR_GENPLL0_SCR_CLK		2
     42 #define BCM_SR_GENPLL0_250M_CLK		3
     43 #define BCM_SR_GENPLL0_PCIE_AXI_CLK	4
     44 #define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK	5
     45 #define BCM_SR_GENPLL0_PAXC_AXI_CLK	6
     46 
     47 /* GENPLL 1 clock channel ID MHB PCIE NITRO */
     48 #define BCM_SR_GENPLL1			0
     49 #define BCM_SR_GENPLL1_PCIE_TL_CLK	1
     50 #define BCM_SR_GENPLL1_MHB_APB_CLK	2
     51 
     52 /* GENPLL 2 clock channel ID NITRO MHB*/
     53 #define BCM_SR_GENPLL2			0
     54 #define BCM_SR_GENPLL2_NIC_CLK		1
     55 #define BCM_SR_GENPLL2_TS_500_CLK	2
     56 #define BCM_SR_GENPLL2_125_NITRO_CLK	3
     57 #define BCM_SR_GENPLL2_CHIMP_CLK	4
     58 #define BCM_SR_GENPLL2_NIC_FLASH_CLK	5
     59 #define BCM_SR_GENPLL2_FS4_CLK		6
     60 
     61 /* GENPLL 3 HSLS clock channel ID */
     62 #define BCM_SR_GENPLL3			0
     63 #define BCM_SR_GENPLL3_HSLS_CLK		1
     64 #define BCM_SR_GENPLL3_SDIO_CLK		2
     65 
     66 /* GENPLL 4 SCR clock channel ID */
     67 #define BCM_SR_GENPLL4			0
     68 #define BCM_SR_GENPLL4_CCN_CLK		1
     69 #define BCM_SR_GENPLL4_TPIU_PLL_CLK	2
     70 #define BCM_SR_GENPLL4_NOC_CLK		3
     71 #define BCM_SR_GENPLL4_CHCLK_FS4_CLK	4
     72 #define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK	5
     73 
     74 /* GENPLL 5 FS4 clock channel ID */
     75 #define BCM_SR_GENPLL5			0
     76 #define BCM_SR_GENPLL5_FS4_HF_CLK	1
     77 #define BCM_SR_GENPLL5_CRYPTO_AE_CLK	2
     78 #define BCM_SR_GENPLL5_RAID_AE_CLK	3
     79 
     80 /* GENPLL 6 NITRO clock channel ID */
     81 #define BCM_SR_GENPLL6			0
     82 #define BCM_SR_GENPLL6_48_USB_CLK	1
     83 
     84 /* LCPLL0  clock channel ID */
     85 #define BCM_SR_LCPLL0			0
     86 #define BCM_SR_LCPLL0_SATA_REFP_CLK	1
     87 #define BCM_SR_LCPLL0_SATA_REFN_CLK	2
     88 #define BCM_SR_LCPLL0_SATA_350_CLK	3
     89 #define BCM_SR_LCPLL0_SATA_500_CLK	4
     90 
     91 /* LCPLL1  clock channel ID */
     92 #define BCM_SR_LCPLL1			0
     93 #define BCM_SR_LCPLL1_WAN_CLK		1
     94 #define BCM_SR_LCPLL1_USB_REF_CLK	2
     95 #define BCM_SR_LCPLL1_CRMU_TS_CLK	3
     96 
     97 /* LCPLL PCIE  clock channel ID */
     98 #define BCM_SR_LCPLL_PCIE		0
     99 #define BCM_SR_LCPLL_PCIE_PHY_REF_CLK	1
    100 
    101 /* GENPLL EMEM0 clock channel ID */
    102 #define BCM_SR_EMEMPLL0			0
    103 #define BCM_SR_EMEMPLL0_EMEM_CLK	1
    104 
    105 /* GENPLL EMEM0 clock channel ID */
    106 #define BCM_SR_EMEMPLL1			0
    107 #define BCM_SR_EMEMPLL1_EMEM_CLK	1
    108 
    109 /* GENPLL EMEM0 clock channel ID */
    110 #define BCM_SR_EMEMPLL2			0
    111 #define BCM_SR_EMEMPLL2_EMEM_CLK	1
    112 
    113 #endif /* _CLOCK_BCM_SR_H */
    114