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      1 /*	$NetBSD: bt1-ccu.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
      6  *
      7  * Baikal-T1 CCU clock indices
      8  */
      9 #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
     10 #define __DT_BINDINGS_CLOCK_BT1_CCU_H
     11 
     12 #define CCU_CPU_PLL			0
     13 #define CCU_SATA_PLL			1
     14 #define CCU_DDR_PLL			2
     15 #define CCU_PCIE_PLL			3
     16 #define CCU_ETH_PLL			4
     17 
     18 #define CCU_AXI_MAIN_CLK		0
     19 #define CCU_AXI_DDR_CLK			1
     20 #define CCU_AXI_SATA_CLK		2
     21 #define CCU_AXI_GMAC0_CLK		3
     22 #define CCU_AXI_GMAC1_CLK		4
     23 #define CCU_AXI_XGMAC_CLK		5
     24 #define CCU_AXI_PCIE_M_CLK		6
     25 #define CCU_AXI_PCIE_S_CLK		7
     26 #define CCU_AXI_USB_CLK			8
     27 #define CCU_AXI_HWA_CLK			9
     28 #define CCU_AXI_SRAM_CLK		10
     29 
     30 #define CCU_SYS_SATA_REF_CLK		0
     31 #define CCU_SYS_APB_CLK			1
     32 #define CCU_SYS_GMAC0_TX_CLK		2
     33 #define CCU_SYS_GMAC0_PTP_CLK		3
     34 #define CCU_SYS_GMAC1_TX_CLK		4
     35 #define CCU_SYS_GMAC1_PTP_CLK		5
     36 #define CCU_SYS_XGMAC_REF_CLK		6
     37 #define CCU_SYS_XGMAC_PTP_CLK		7
     38 #define CCU_SYS_USB_CLK			8
     39 #define CCU_SYS_PVT_CLK			9
     40 #define CCU_SYS_HWA_CLK			10
     41 #define CCU_SYS_UART_CLK		11
     42 #define CCU_SYS_I2C1_CLK		12
     43 #define CCU_SYS_I2C2_CLK		13
     44 #define CCU_SYS_GPIO_CLK		14
     45 #define CCU_SYS_TIMER0_CLK		15
     46 #define CCU_SYS_TIMER1_CLK		16
     47 #define CCU_SYS_TIMER2_CLK		17
     48 #define CCU_SYS_WDT_CLK			18
     49 
     50 #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
     51