1 /* $NetBSD: exynos5410.h,v 1.1.1.3 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * Copyright (c) 2016 Krzysztof Kozlowski 7 * 8 * Device Tree binding constants for Exynos5421 clock controller. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 12 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 13 14 /* core clocks */ 15 #define CLK_FIN_PLL 1 16 #define CLK_FOUT_APLL 2 17 #define CLK_FOUT_CPLL 3 18 #define CLK_FOUT_MPLL 4 19 #define CLK_FOUT_BPLL 5 20 #define CLK_FOUT_KPLL 6 21 #define CLK_FOUT_EPLL 7 22 23 /* gate for special clocks (sclk) */ 24 #define CLK_SCLK_UART0 128 25 #define CLK_SCLK_UART1 129 26 #define CLK_SCLK_UART2 130 27 #define CLK_SCLK_UART3 131 28 #define CLK_SCLK_MMC0 132 29 #define CLK_SCLK_MMC1 133 30 #define CLK_SCLK_MMC2 134 31 #define CLK_SCLK_USBD300 150 32 #define CLK_SCLK_USBD301 151 33 #define CLK_SCLK_USBPHY300 152 34 #define CLK_SCLK_USBPHY301 153 35 #define CLK_SCLK_PWM 155 36 37 /* gate clocks */ 38 #define CLK_UART0 257 39 #define CLK_UART1 258 40 #define CLK_UART2 259 41 #define CLK_UART3 260 42 #define CLK_I2C0 261 43 #define CLK_I2C1 262 44 #define CLK_I2C2 263 45 #define CLK_I2C3 264 46 #define CLK_USI0 265 47 #define CLK_USI1 266 48 #define CLK_USI2 267 49 #define CLK_USI3 268 50 #define CLK_TSADC 270 51 #define CLK_PWM 279 52 #define CLK_MCT 315 53 #define CLK_WDT 316 54 #define CLK_RTC 317 55 #define CLK_TMU 318 56 #define CLK_MMC0 351 57 #define CLK_MMC1 352 58 #define CLK_MMC2 353 59 #define CLK_PDMA0 362 60 #define CLK_PDMA1 363 61 #define CLK_USBH20 365 62 #define CLK_USBD300 366 63 #define CLK_USBD301 367 64 #define CLK_SSS 471 65 66 #define CLK_NR_CLKS 512 67 68 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 69
Indexes created Sat Sep 27 21:09:56 GMT 2025