1 /* $NetBSD: exynos5420.h,v 1.1.1.5 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * Author: Andrzej Hajda <a.hajda (at) samsung.com> 7 * 8 * Device Tree binding constants for Exynos5420 clock controller. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 12 #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 13 14 /* core clocks */ 15 #define CLK_FIN_PLL 1 16 #define CLK_FOUT_APLL 2 17 #define CLK_FOUT_CPLL 3 18 #define CLK_FOUT_DPLL 4 19 #define CLK_FOUT_EPLL 5 20 #define CLK_FOUT_RPLL 6 21 #define CLK_FOUT_IPLL 7 22 #define CLK_FOUT_SPLL 8 23 #define CLK_FOUT_VPLL 9 24 #define CLK_FOUT_MPLL 10 25 #define CLK_FOUT_BPLL 11 26 #define CLK_FOUT_KPLL 12 27 #define CLK_ARM_CLK 13 28 #define CLK_KFC_CLK 14 29 30 /* gate for special clocks (sclk) */ 31 #define CLK_SCLK_UART0 128 32 #define CLK_SCLK_UART1 129 33 #define CLK_SCLK_UART2 130 34 #define CLK_SCLK_UART3 131 35 #define CLK_SCLK_MMC0 132 36 #define CLK_SCLK_MMC1 133 37 #define CLK_SCLK_MMC2 134 38 #define CLK_SCLK_SPI0 135 39 #define CLK_SCLK_SPI1 136 40 #define CLK_SCLK_SPI2 137 41 #define CLK_SCLK_I2S1 138 42 #define CLK_SCLK_I2S2 139 43 #define CLK_SCLK_PCM1 140 44 #define CLK_SCLK_PCM2 141 45 #define CLK_SCLK_SPDIF 142 46 #define CLK_SCLK_HDMI 143 47 #define CLK_SCLK_PIXEL 144 48 #define CLK_SCLK_DP1 145 49 #define CLK_SCLK_MIPI1 146 50 #define CLK_SCLK_FIMD1 147 51 #define CLK_SCLK_MAUDIO0 148 52 #define CLK_SCLK_MAUPCM0 149 53 #define CLK_SCLK_USBD300 150 54 #define CLK_SCLK_USBD301 151 55 #define CLK_SCLK_USBPHY300 152 56 #define CLK_SCLK_USBPHY301 153 57 #define CLK_SCLK_UNIPRO 154 58 #define CLK_SCLK_PWM 155 59 #define CLK_SCLK_GSCL_WA 156 60 #define CLK_SCLK_GSCL_WB 157 61 #define CLK_SCLK_HDMIPHY 158 62 #define CLK_MAU_EPLL 159 63 #define CLK_SCLK_HSIC_12M 160 64 #define CLK_SCLK_MPHY_IXTAL24 161 65 #define CLK_SCLK_BPLL 162 66 67 /* gate clocks */ 68 #define CLK_UART0 257 69 #define CLK_UART1 258 70 #define CLK_UART2 259 71 #define CLK_UART3 260 72 #define CLK_I2C0 261 73 #define CLK_I2C1 262 74 #define CLK_I2C2 263 75 #define CLK_I2C3 264 76 #define CLK_USI0 265 77 #define CLK_USI1 266 78 #define CLK_USI2 267 79 #define CLK_USI3 268 80 #define CLK_I2C_HDMI 269 81 #define CLK_TSADC 270 82 #define CLK_SPI0 271 83 #define CLK_SPI1 272 84 #define CLK_SPI2 273 85 #define CLK_KEYIF 274 86 #define CLK_I2S1 275 87 #define CLK_I2S2 276 88 #define CLK_PCM1 277 89 #define CLK_PCM2 278 90 #define CLK_PWM 279 91 #define CLK_SPDIF 280 92 #define CLK_USI4 281 93 #define CLK_USI5 282 94 #define CLK_USI6 283 95 #define CLK_ACLK66_PSGEN 300 96 #define CLK_CHIPID 301 97 #define CLK_SYSREG 302 98 #define CLK_TZPC0 303 99 #define CLK_TZPC1 304 100 #define CLK_TZPC2 305 101 #define CLK_TZPC3 306 102 #define CLK_TZPC4 307 103 #define CLK_TZPC5 308 104 #define CLK_TZPC6 309 105 #define CLK_TZPC7 310 106 #define CLK_TZPC8 311 107 #define CLK_TZPC9 312 108 #define CLK_HDMI_CEC 313 109 #define CLK_SECKEY 314 110 #define CLK_MCT 315 111 #define CLK_WDT 316 112 #define CLK_RTC 317 113 #define CLK_TMU 318 114 #define CLK_TMU_GPU 319 115 #define CLK_PCLK66_GPIO 330 116 #define CLK_ACLK200_FSYS2 350 117 #define CLK_MMC0 351 118 #define CLK_MMC1 352 119 #define CLK_MMC2 353 120 #define CLK_SROMC 354 121 #define CLK_UFS 355 122 #define CLK_ACLK200_FSYS 360 123 #define CLK_TSI 361 124 #define CLK_PDMA0 362 125 #define CLK_PDMA1 363 126 #define CLK_RTIC 364 127 #define CLK_USBH20 365 128 #define CLK_USBD300 366 129 #define CLK_USBD301 367 130 #define CLK_ACLK400_MSCL 380 131 #define CLK_MSCL0 381 132 #define CLK_MSCL1 382 133 #define CLK_MSCL2 383 134 #define CLK_SMMU_MSCL0 384 135 #define CLK_SMMU_MSCL1 385 136 #define CLK_SMMU_MSCL2 386 137 #define CLK_ACLK333 400 138 #define CLK_MFC 401 139 #define CLK_SMMU_MFCL 402 140 #define CLK_SMMU_MFCR 403 141 #define CLK_ACLK200_DISP1 410 142 #define CLK_DSIM1 411 143 #define CLK_DP1 412 144 #define CLK_HDMI 413 145 #define CLK_ACLK300_DISP1 420 146 #define CLK_FIMD1 421 147 #define CLK_SMMU_FIMD1M0 422 148 #define CLK_SMMU_FIMD1M1 423 149 #define CLK_ACLK166 430 150 #define CLK_MIXER 431 151 #define CLK_ACLK266 440 152 #define CLK_ROTATOR 441 153 #define CLK_MDMA1 442 154 #define CLK_SMMU_ROTATOR 443 155 #define CLK_SMMU_MDMA1 444 156 #define CLK_ACLK300_JPEG 450 157 #define CLK_JPEG 451 158 #define CLK_JPEG2 452 159 #define CLK_SMMU_JPEG 453 160 #define CLK_SMMU_JPEG2 454 161 #define CLK_ACLK300_GSCL 460 162 #define CLK_SMMU_GSCL0 461 163 #define CLK_SMMU_GSCL1 462 164 #define CLK_GSCL_WA 463 165 #define CLK_GSCL_WB 464 166 #define CLK_GSCL0 465 167 #define CLK_GSCL1 466 168 #define CLK_FIMC_3AA 467 169 #define CLK_ACLK266_G2D 470 170 #define CLK_SSS 471 171 #define CLK_SLIM_SSS 472 172 #define CLK_MDMA0 473 173 #define CLK_ACLK333_G2D 480 174 #define CLK_G2D 481 175 #define CLK_ACLK333_432_GSCL 490 176 #define CLK_SMMU_3AA 491 177 #define CLK_SMMU_FIMCL0 492 178 #define CLK_SMMU_FIMCL1 493 179 #define CLK_SMMU_FIMCL3 494 180 #define CLK_FIMC_LITE3 495 181 #define CLK_FIMC_LITE0 496 182 #define CLK_FIMC_LITE1 497 183 #define CLK_ACLK_G3D 500 184 #define CLK_G3D 501 185 #define CLK_SMMU_MIXER 502 186 #define CLK_SMMU_G2D 503 187 #define CLK_SMMU_MDMA0 504 188 #define CLK_MC 505 189 #define CLK_TOP_RTC 506 190 #define CLK_SCLK_UART_ISP 510 191 #define CLK_SCLK_SPI0_ISP 511 192 #define CLK_SCLK_SPI1_ISP 512 193 #define CLK_SCLK_PWM_ISP 513 194 #define CLK_SCLK_ISP_SENSOR0 514 195 #define CLK_SCLK_ISP_SENSOR1 515 196 #define CLK_SCLK_ISP_SENSOR2 516 197 #define CLK_ACLK432_SCALER 517 198 #define CLK_ACLK432_CAM 518 199 #define CLK_ACLK_FL1550_CAM 519 200 #define CLK_ACLK550_CAM 520 201 #define CLK_CLKM_PHY0 521 202 #define CLK_CLKM_PHY1 522 203 #define CLK_ACLK_PPMU_DREX0_0 523 204 #define CLK_ACLK_PPMU_DREX0_1 524 205 #define CLK_ACLK_PPMU_DREX1_0 525 206 #define CLK_ACLK_PPMU_DREX1_1 526 207 #define CLK_PCLK_PPMU_DREX0_0 527 208 #define CLK_PCLK_PPMU_DREX0_1 528 209 #define CLK_PCLK_PPMU_DREX1_0 529 210 #define CLK_PCLK_PPMU_DREX1_1 530 211 212 /* mux clocks */ 213 #define CLK_MOUT_HDMI 640 214 #define CLK_MOUT_G3D 641 215 #define CLK_MOUT_VPLL 642 216 #define CLK_MOUT_MAUDIO0 643 217 #define CLK_MOUT_USER_ACLK333 644 218 #define CLK_MOUT_SW_ACLK333 645 219 #define CLK_MOUT_USER_ACLK200_DISP1 646 220 #define CLK_MOUT_SW_ACLK200 647 221 #define CLK_MOUT_USER_ACLK300_DISP1 648 222 #define CLK_MOUT_SW_ACLK300 649 223 #define CLK_MOUT_USER_ACLK400_DISP1 650 224 #define CLK_MOUT_SW_ACLK400 651 225 #define CLK_MOUT_USER_ACLK300_GSCL 652 226 #define CLK_MOUT_SW_ACLK300_GSCL 653 227 #define CLK_MOUT_MCLK_CDREX 654 228 #define CLK_MOUT_BPLL 655 229 #define CLK_MOUT_MX_MSPLL_CCORE 656 230 #define CLK_MOUT_EPLL 657 231 #define CLK_MOUT_MAU_EPLL 658 232 #define CLK_MOUT_USER_MAU_EPLL 659 233 #define CLK_MOUT_SCLK_SPLL 660 234 #define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 235 #define CLK_MOUT_SW_ACLK_G3D 662 236 #define CLK_MOUT_APLL 663 237 #define CLK_MOUT_MSPLL_CPU 664 238 #define CLK_MOUT_KPLL 665 239 #define CLK_MOUT_MSPLL_KFC 666 240 241 242 /* divider clocks */ 243 #define CLK_DOUT_PIXEL 768 244 #define CLK_DOUT_ACLK400_WCORE 769 245 #define CLK_DOUT_ACLK400_ISP 770 246 #define CLK_DOUT_ACLK400_MSCL 771 247 #define CLK_DOUT_ACLK200 772 248 #define CLK_DOUT_ACLK200_FSYS2 773 249 #define CLK_DOUT_ACLK100_NOC 774 250 #define CLK_DOUT_PCLK200_FSYS 775 251 #define CLK_DOUT_ACLK200_FSYS 776 252 #define CLK_DOUT_ACLK333_432_GSCL 777 253 #define CLK_DOUT_ACLK333_432_ISP 778 254 #define CLK_DOUT_ACLK66 779 255 #define CLK_DOUT_ACLK333_432_ISP0 780 256 #define CLK_DOUT_ACLK266 781 257 #define CLK_DOUT_ACLK166 782 258 #define CLK_DOUT_ACLK333 783 259 #define CLK_DOUT_ACLK333_G2D 784 260 #define CLK_DOUT_ACLK266_G2D 785 261 #define CLK_DOUT_ACLK_G3D 786 262 #define CLK_DOUT_ACLK300_JPEG 787 263 #define CLK_DOUT_ACLK300_DISP1 788 264 #define CLK_DOUT_ACLK300_GSCL 789 265 #define CLK_DOUT_ACLK400_DISP1 790 266 #define CLK_DOUT_PCLK_CDREX 791 267 #define CLK_DOUT_SCLK_CDREX 792 268 #define CLK_DOUT_ACLK_CDREX1 793 269 #define CLK_DOUT_CCLK_DREX0 794 270 #define CLK_DOUT_CLK2X_PHY0 795 271 #define CLK_DOUT_PCLK_CORE_MEM 796 272 #define CLK_FF_DOUT_SPLL2 797 273 #define CLK_DOUT_PCLK_DREX0 798 274 #define CLK_DOUT_PCLK_DREX1 799 275 276 /* must be greater than maximal clock id */ 277 #define CLK_NR_CLKS 800 278 279 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 280
Indexes created Fri Sep 26 20:09:58 GMT 2025