exynos5420.h revision 1.1.1.1.4.2
1 /* $NetBSD: exynos5420.h,v 1.1.1.1.4.2 2017/07/18 16:08:56 snj Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * Author: Andrzej Hajda <a.hajda (at) samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Device Tree binding constants for Exynos5420 clock controller. 12 */ 13 14 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 15 #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 16 17 /* core clocks */ 18 #define CLK_FIN_PLL 1 19 #define CLK_FOUT_APLL 2 20 #define CLK_FOUT_CPLL 3 21 #define CLK_FOUT_DPLL 4 22 #define CLK_FOUT_EPLL 5 23 #define CLK_FOUT_RPLL 6 24 #define CLK_FOUT_IPLL 7 25 #define CLK_FOUT_SPLL 8 26 #define CLK_FOUT_VPLL 9 27 #define CLK_FOUT_MPLL 10 28 #define CLK_FOUT_BPLL 11 29 #define CLK_FOUT_KPLL 12 30 #define CLK_ARM_CLK 13 31 #define CLK_KFC_CLK 14 32 33 /* gate for special clocks (sclk) */ 34 #define CLK_SCLK_UART0 128 35 #define CLK_SCLK_UART1 129 36 #define CLK_SCLK_UART2 130 37 #define CLK_SCLK_UART3 131 38 #define CLK_SCLK_MMC0 132 39 #define CLK_SCLK_MMC1 133 40 #define CLK_SCLK_MMC2 134 41 #define CLK_SCLK_SPI0 135 42 #define CLK_SCLK_SPI1 136 43 #define CLK_SCLK_SPI2 137 44 #define CLK_SCLK_I2S1 138 45 #define CLK_SCLK_I2S2 139 46 #define CLK_SCLK_PCM1 140 47 #define CLK_SCLK_PCM2 141 48 #define CLK_SCLK_SPDIF 142 49 #define CLK_SCLK_HDMI 143 50 #define CLK_SCLK_PIXEL 144 51 #define CLK_SCLK_DP1 145 52 #define CLK_SCLK_MIPI1 146 53 #define CLK_SCLK_FIMD1 147 54 #define CLK_SCLK_MAUDIO0 148 55 #define CLK_SCLK_MAUPCM0 149 56 #define CLK_SCLK_USBD300 150 57 #define CLK_SCLK_USBD301 151 58 #define CLK_SCLK_USBPHY300 152 59 #define CLK_SCLK_USBPHY301 153 60 #define CLK_SCLK_UNIPRO 154 61 #define CLK_SCLK_PWM 155 62 #define CLK_SCLK_GSCL_WA 156 63 #define CLK_SCLK_GSCL_WB 157 64 #define CLK_SCLK_HDMIPHY 158 65 #define CLK_MAU_EPLL 159 66 #define CLK_SCLK_HSIC_12M 160 67 #define CLK_SCLK_MPHY_IXTAL24 161 68 69 /* gate clocks */ 70 #define CLK_UART0 257 71 #define CLK_UART1 258 72 #define CLK_UART2 259 73 #define CLK_UART3 260 74 #define CLK_I2C0 261 75 #define CLK_I2C1 262 76 #define CLK_I2C2 263 77 #define CLK_I2C3 264 78 #define CLK_USI0 265 79 #define CLK_USI1 266 80 #define CLK_USI2 267 81 #define CLK_USI3 268 82 #define CLK_I2C_HDMI 269 83 #define CLK_TSADC 270 84 #define CLK_SPI0 271 85 #define CLK_SPI1 272 86 #define CLK_SPI2 273 87 #define CLK_KEYIF 274 88 #define CLK_I2S1 275 89 #define CLK_I2S2 276 90 #define CLK_PCM1 277 91 #define CLK_PCM2 278 92 #define CLK_PWM 279 93 #define CLK_SPDIF 280 94 #define CLK_USI4 281 95 #define CLK_USI5 282 96 #define CLK_USI6 283 97 #define CLK_ACLK66_PSGEN 300 98 #define CLK_CHIPID 301 99 #define CLK_SYSREG 302 100 #define CLK_TZPC0 303 101 #define CLK_TZPC1 304 102 #define CLK_TZPC2 305 103 #define CLK_TZPC3 306 104 #define CLK_TZPC4 307 105 #define CLK_TZPC5 308 106 #define CLK_TZPC6 309 107 #define CLK_TZPC7 310 108 #define CLK_TZPC8 311 109 #define CLK_TZPC9 312 110 #define CLK_HDMI_CEC 313 111 #define CLK_SECKEY 314 112 #define CLK_MCT 315 113 #define CLK_WDT 316 114 #define CLK_RTC 317 115 #define CLK_TMU 318 116 #define CLK_TMU_GPU 319 117 #define CLK_PCLK66_GPIO 330 118 #define CLK_ACLK200_FSYS2 350 119 #define CLK_MMC0 351 120 #define CLK_MMC1 352 121 #define CLK_MMC2 353 122 #define CLK_SROMC 354 123 #define CLK_UFS 355 124 #define CLK_ACLK200_FSYS 360 125 #define CLK_TSI 361 126 #define CLK_PDMA0 362 127 #define CLK_PDMA1 363 128 #define CLK_RTIC 364 129 #define CLK_USBH20 365 130 #define CLK_USBD300 366 131 #define CLK_USBD301 367 132 #define CLK_ACLK400_MSCL 380 133 #define CLK_MSCL0 381 134 #define CLK_MSCL1 382 135 #define CLK_MSCL2 383 136 #define CLK_SMMU_MSCL0 384 137 #define CLK_SMMU_MSCL1 385 138 #define CLK_SMMU_MSCL2 386 139 #define CLK_ACLK333 400 140 #define CLK_MFC 401 141 #define CLK_SMMU_MFCL 402 142 #define CLK_SMMU_MFCR 403 143 #define CLK_ACLK200_DISP1 410 144 #define CLK_DSIM1 411 145 #define CLK_DP1 412 146 #define CLK_HDMI 413 147 #define CLK_ACLK300_DISP1 420 148 #define CLK_FIMD1 421 149 #define CLK_SMMU_FIMD1M0 422 150 #define CLK_SMMU_FIMD1M1 423 151 #define CLK_ACLK166 430 152 #define CLK_MIXER 431 153 #define CLK_ACLK266 440 154 #define CLK_ROTATOR 441 155 #define CLK_MDMA1 442 156 #define CLK_SMMU_ROTATOR 443 157 #define CLK_SMMU_MDMA1 444 158 #define CLK_ACLK300_JPEG 450 159 #define CLK_JPEG 451 160 #define CLK_JPEG2 452 161 #define CLK_SMMU_JPEG 453 162 #define CLK_SMMU_JPEG2 454 163 #define CLK_ACLK300_GSCL 460 164 #define CLK_SMMU_GSCL0 461 165 #define CLK_SMMU_GSCL1 462 166 #define CLK_GSCL_WA 463 167 #define CLK_GSCL_WB 464 168 #define CLK_GSCL0 465 169 #define CLK_GSCL1 466 170 #define CLK_FIMC_3AA 467 171 #define CLK_ACLK266_G2D 470 172 #define CLK_SSS 471 173 #define CLK_SLIM_SSS 472 174 #define CLK_MDMA0 473 175 #define CLK_ACLK333_G2D 480 176 #define CLK_G2D 481 177 #define CLK_ACLK333_432_GSCL 490 178 #define CLK_SMMU_3AA 491 179 #define CLK_SMMU_FIMCL0 492 180 #define CLK_SMMU_FIMCL1 493 181 #define CLK_SMMU_FIMCL3 494 182 #define CLK_FIMC_LITE3 495 183 #define CLK_FIMC_LITE0 496 184 #define CLK_FIMC_LITE1 497 185 #define CLK_ACLK_G3D 500 186 #define CLK_G3D 501 187 #define CLK_SMMU_MIXER 502 188 #define CLK_SMMU_G2D 503 189 #define CLK_SMMU_MDMA0 504 190 #define CLK_MC 505 191 #define CLK_TOP_RTC 506 192 #define CLK_SCLK_UART_ISP 510 193 #define CLK_SCLK_SPI0_ISP 511 194 #define CLK_SCLK_SPI1_ISP 512 195 #define CLK_SCLK_PWM_ISP 513 196 #define CLK_SCLK_ISP_SENSOR0 514 197 #define CLK_SCLK_ISP_SENSOR1 515 198 #define CLK_SCLK_ISP_SENSOR2 516 199 #define CLK_ACLK432_SCALER 517 200 #define CLK_ACLK432_CAM 518 201 #define CLK_ACLK_FL1550_CAM 519 202 #define CLK_ACLK550_CAM 520 203 204 /* mux clocks */ 205 #define CLK_MOUT_HDMI 640 206 #define CLK_MOUT_G3D 641 207 #define CLK_MOUT_VPLL 642 208 #define CLK_MOUT_MAUDIO0 643 209 #define CLK_MOUT_USER_ACLK333 644 210 #define CLK_MOUT_SW_ACLK333 645 211 #define CLK_MOUT_USER_ACLK200_DISP1 646 212 #define CLK_MOUT_SW_ACLK200 647 213 #define CLK_MOUT_USER_ACLK300_DISP1 648 214 #define CLK_MOUT_SW_ACLK300 649 215 #define CLK_MOUT_USER_ACLK400_DISP1 650 216 #define CLK_MOUT_SW_ACLK400 651 217 #define CLK_MOUT_USER_ACLK300_GSCL 652 218 #define CLK_MOUT_SW_ACLK300_GSCL 653 219 #define CLK_MOUT_MCLK_CDREX 654 220 #define CLK_MOUT_BPLL 655 221 #define CLK_MOUT_MX_MSPLL_CCORE 656 222 223 /* divider clocks */ 224 #define CLK_DOUT_PIXEL 768 225 #define CLK_DOUT_ACLK400_WCORE 769 226 #define CLK_DOUT_ACLK400_ISP 770 227 #define CLK_DOUT_ACLK400_MSCL 771 228 #define CLK_DOUT_ACLK200 772 229 #define CLK_DOUT_ACLK200_FSYS2 773 230 #define CLK_DOUT_ACLK100_NOC 774 231 #define CLK_DOUT_PCLK200_FSYS 775 232 #define CLK_DOUT_ACLK200_FSYS 776 233 #define CLK_DOUT_ACLK333_432_GSCL 777 234 #define CLK_DOUT_ACLK333_432_ISP 778 235 #define CLK_DOUT_ACLK66 779 236 #define CLK_DOUT_ACLK333_432_ISP0 780 237 #define CLK_DOUT_ACLK266 781 238 #define CLK_DOUT_ACLK166 782 239 #define CLK_DOUT_ACLK333 783 240 #define CLK_DOUT_ACLK333_G2D 784 241 #define CLK_DOUT_ACLK266_G2D 785 242 #define CLK_DOUT_ACLK_G3D 786 243 #define CLK_DOUT_ACLK300_JPEG 787 244 #define CLK_DOUT_ACLK300_DISP1 788 245 #define CLK_DOUT_ACLK300_GSCL 789 246 #define CLK_DOUT_ACLK400_DISP1 790 247 #define CLK_DOUT_PCLK_CDREX 791 248 #define CLK_DOUT_SCLK_CDREX 792 249 #define CLK_DOUT_ACLK_CDREX1 793 250 #define CLK_DOUT_CCLK_DREX0 794 251 #define CLK_DOUT_CLK2X_PHY0 795 252 #define CLK_DOUT_PCLK_CORE_MEM 796 253 254 /* must be greater than maximal clock id */ 255 #define CLK_NR_CLKS 797 256 257 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 258
Indexes created Mon Oct 20 11:09:49 GMT 2025