1 /* $NetBSD: exynos7-clk.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * Author: Naveen Krishna Ch <naveenkrishna.ch (at) gmail.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS7_H 11 12 /* TOPC */ 13 #define DOUT_ACLK_PERIS 1 14 #define DOUT_SCLK_BUS0_PLL 2 15 #define DOUT_SCLK_BUS1_PLL 3 16 #define DOUT_SCLK_CC_PLL 4 17 #define DOUT_SCLK_MFC_PLL 5 18 #define DOUT_ACLK_CCORE_133 6 19 #define DOUT_ACLK_MSCL_532 7 20 #define ACLK_MSCL_532 8 21 #define DOUT_SCLK_AUD_PLL 9 22 #define FOUT_AUD_PLL 10 23 #define SCLK_AUD_PLL 11 24 #define SCLK_MFC_PLL_B 12 25 #define SCLK_MFC_PLL_A 13 26 #define SCLK_BUS1_PLL_B 14 27 #define SCLK_BUS1_PLL_A 15 28 #define SCLK_BUS0_PLL_B 16 29 #define SCLK_BUS0_PLL_A 17 30 #define SCLK_CC_PLL_B 18 31 #define SCLK_CC_PLL_A 19 32 #define ACLK_CCORE_133 20 33 #define ACLK_PERIS_66 21 34 #define TOPC_NR_CLK 22 35 36 /* TOP0 */ 37 #define DOUT_ACLK_PERIC1 1 38 #define DOUT_ACLK_PERIC0 2 39 #define CLK_SCLK_UART0 3 40 #define CLK_SCLK_UART1 4 41 #define CLK_SCLK_UART2 5 42 #define CLK_SCLK_UART3 6 43 #define CLK_SCLK_SPI0 7 44 #define CLK_SCLK_SPI1 8 45 #define CLK_SCLK_SPI2 9 46 #define CLK_SCLK_SPI3 10 47 #define CLK_SCLK_SPI4 11 48 #define CLK_SCLK_SPDIF 12 49 #define CLK_SCLK_PCM1 13 50 #define CLK_SCLK_I2S1 14 51 #define CLK_ACLK_PERIC0_66 15 52 #define CLK_ACLK_PERIC1_66 16 53 #define TOP0_NR_CLK 17 54 55 /* TOP1 */ 56 #define DOUT_ACLK_FSYS1_200 1 57 #define DOUT_ACLK_FSYS0_200 2 58 #define DOUT_SCLK_MMC2 3 59 #define DOUT_SCLK_MMC1 4 60 #define DOUT_SCLK_MMC0 5 61 #define CLK_SCLK_MMC2 6 62 #define CLK_SCLK_MMC1 7 63 #define CLK_SCLK_MMC0 8 64 #define CLK_ACLK_FSYS0_200 9 65 #define CLK_ACLK_FSYS1_200 10 66 #define CLK_SCLK_PHY_FSYS1 11 67 #define CLK_SCLK_PHY_FSYS1_26M 12 68 #define MOUT_SCLK_UFSUNIPRO20 13 69 #define DOUT_SCLK_UFSUNIPRO20 14 70 #define CLK_SCLK_UFSUNIPRO20 15 71 #define DOUT_SCLK_PHY_FSYS1 16 72 #define DOUT_SCLK_PHY_FSYS1_26M 17 73 #define TOP1_NR_CLK 18 74 75 /* CCORE */ 76 #define PCLK_RTC 1 77 #define CCORE_NR_CLK 2 78 79 /* PERIC0 */ 80 #define PCLK_UART0 1 81 #define SCLK_UART0 2 82 #define PCLK_HSI2C0 3 83 #define PCLK_HSI2C1 4 84 #define PCLK_HSI2C4 5 85 #define PCLK_HSI2C5 6 86 #define PCLK_HSI2C9 7 87 #define PCLK_HSI2C10 8 88 #define PCLK_HSI2C11 9 89 #define PCLK_PWM 10 90 #define SCLK_PWM 11 91 #define PCLK_ADCIF 12 92 #define PERIC0_NR_CLK 13 93 94 /* PERIC1 */ 95 #define PCLK_UART1 1 96 #define PCLK_UART2 2 97 #define PCLK_UART3 3 98 #define SCLK_UART1 4 99 #define SCLK_UART2 5 100 #define SCLK_UART3 6 101 #define PCLK_HSI2C2 7 102 #define PCLK_HSI2C3 8 103 #define PCLK_HSI2C6 9 104 #define PCLK_HSI2C7 10 105 #define PCLK_HSI2C8 11 106 #define PCLK_SPI0 12 107 #define PCLK_SPI1 13 108 #define PCLK_SPI2 14 109 #define PCLK_SPI3 15 110 #define PCLK_SPI4 16 111 #define SCLK_SPI0 17 112 #define SCLK_SPI1 18 113 #define SCLK_SPI2 19 114 #define SCLK_SPI3 20 115 #define SCLK_SPI4 21 116 #define PCLK_I2S1 22 117 #define PCLK_PCM1 23 118 #define PCLK_SPDIF 24 119 #define SCLK_I2S1 25 120 #define SCLK_PCM1 26 121 #define SCLK_SPDIF 27 122 #define PERIC1_NR_CLK 28 123 124 /* PERIS */ 125 #define PCLK_CHIPID 1 126 #define SCLK_CHIPID 2 127 #define PCLK_WDT 3 128 #define PCLK_TMU 4 129 #define SCLK_TMU 5 130 #define PERIS_NR_CLK 6 131 132 /* FSYS0 */ 133 #define ACLK_MMC2 1 134 #define ACLK_AXIUS_USBDRD30X_FSYS0X 2 135 #define ACLK_USBDRD300 3 136 #define SCLK_USBDRD300_SUSPENDCLK 4 137 #define SCLK_USBDRD300_REFCLK 5 138 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 139 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 140 #define OSCCLK_PHY_CLKOUT_USB30_PHY 8 141 #define ACLK_PDMA0 9 142 #define ACLK_PDMA1 10 143 #define FSYS0_NR_CLK 11 144 145 /* FSYS1 */ 146 #define ACLK_MMC1 1 147 #define ACLK_MMC0 2 148 #define PHYCLK_UFS20_TX0_SYMBOL 3 149 #define PHYCLK_UFS20_RX0_SYMBOL 4 150 #define PHYCLK_UFS20_RX1_SYMBOL 5 151 #define ACLK_UFS20_LINK 6 152 #define SCLK_UFSUNIPRO20_USER 7 153 #define PHYCLK_UFS20_RX1_SYMBOL_USER 8 154 #define PHYCLK_UFS20_RX0_SYMBOL_USER 9 155 #define PHYCLK_UFS20_TX0_SYMBOL_USER 10 156 #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 157 #define SCLK_COMBO_PHY_EMBEDDED_26M 12 158 #define DOUT_PCLK_FSYS1 13 159 #define PCLK_GPIO_FSYS1 14 160 #define MOUT_FSYS1_PHYCLK_SEL1 15 161 #define FSYS1_NR_CLK 16 162 163 /* MSCL */ 164 #define USERMUX_ACLK_MSCL_532 1 165 #define DOUT_PCLK_MSCL 2 166 #define ACLK_MSCL_0 3 167 #define ACLK_MSCL_1 4 168 #define ACLK_JPEG 5 169 #define ACLK_G2D 6 170 #define ACLK_LH_ASYNC_SI_MSCL_0 7 171 #define ACLK_LH_ASYNC_SI_MSCL_1 8 172 #define ACLK_AXI2ACEL_BRIDGE 9 173 #define ACLK_XIU_MSCLX_0 10 174 #define ACLK_XIU_MSCLX_1 11 175 #define ACLK_QE_MSCL_0 12 176 #define ACLK_QE_MSCL_1 13 177 #define ACLK_QE_JPEG 14 178 #define ACLK_QE_G2D 15 179 #define ACLK_PPMU_MSCL_0 16 180 #define ACLK_PPMU_MSCL_1 17 181 #define ACLK_MSCLNP_133 18 182 #define ACLK_AHB2APB_MSCL0P 19 183 #define ACLK_AHB2APB_MSCL1P 20 184 185 #define PCLK_MSCL_0 21 186 #define PCLK_MSCL_1 22 187 #define PCLK_JPEG 23 188 #define PCLK_G2D 24 189 #define PCLK_QE_MSCL_0 25 190 #define PCLK_QE_MSCL_1 26 191 #define PCLK_QE_JPEG 27 192 #define PCLK_QE_G2D 28 193 #define PCLK_PPMU_MSCL_0 29 194 #define PCLK_PPMU_MSCL_1 30 195 #define PCLK_AXI2ACEL_BRIDGE 31 196 #define PCLK_PMU_MSCL 32 197 #define MSCL_NR_CLK 33 198 199 /* AUD */ 200 #define SCLK_I2S 1 201 #define SCLK_PCM 2 202 #define PCLK_I2S 3 203 #define PCLK_PCM 4 204 #define ACLK_ADMA 5 205 #define AUD_NR_CLK 6 206 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 207
Indexes created Sun Sep 28 16:09:52 GMT 2025