1/*	$NetBSD: fsd-clk.h,v 1.1.1.1 2026/01/18 05:21:29 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
6 *             https://www.samsung.com
7 * Copyright (c) 2017-2022 Tesla, Inc.
8 *             https://www.tesla.com
9 *
10 * The constants defined in this header are being used in dts
11 * and fsd platform driver.
12 */
13
14#ifndef _DT_BINDINGS_CLOCK_FSD_H
15#define _DT_BINDINGS_CLOCK_FSD_H
16
17/* CMU */
18#define DOUT_CMU_PLL_SHARED0_DIV4		1
19#define DOUT_CMU_PERIC_SHARED1DIV36		2
20#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK	3
21#define DOUT_CMU_PERIC_SHARED0DIV20		4
22#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK	5
23#define DOUT_CMU_PLL_SHARED0_DIV6		6
24#define DOUT_CMU_FSYS0_SHARED1DIV4		7
25#define DOUT_CMU_FSYS0_SHARED0DIV4		8
26#define DOUT_CMU_FSYS1_SHARED0DIV8		9
27#define DOUT_CMU_FSYS1_SHARED0DIV4		10
28#define CMU_CPUCL_SWITCH_GATE			11
29#define DOUT_CMU_IMEM_TCUCLK			12
30#define DOUT_CMU_IMEM_ACLK			13
31#define DOUT_CMU_IMEM_DMACLK			14
32#define GAT_CMU_FSYS0_SHARED0DIV4		15
33#define CMU_NR_CLK				16
34
35/* PERIC */
36#define PERIC_SCLK_UART0			1
37#define PERIC_PCLK_UART0			2
38#define PERIC_SCLK_UART1			3
39#define PERIC_PCLK_UART1			4
40#define PERIC_DMA0_IPCLKPORT_ACLK		5
41#define PERIC_DMA1_IPCLKPORT_ACLK		6
42#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0		7
43#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0		8
44#define PERIC_PCLK_SPI0                         9
45#define PERIC_SCLK_SPI0                         10
46#define PERIC_PCLK_SPI1                         11
47#define PERIC_SCLK_SPI1                         12
48#define PERIC_PCLK_SPI2                         13
49#define PERIC_SCLK_SPI2                         14
50#define PERIC_PCLK_TDM0                         15
51#define PERIC_PCLK_HSI2C0			16
52#define PERIC_PCLK_HSI2C1			17
53#define PERIC_PCLK_HSI2C2			18
54#define PERIC_PCLK_HSI2C3			19
55#define PERIC_PCLK_HSI2C4			20
56#define PERIC_PCLK_HSI2C5			21
57#define PERIC_PCLK_HSI2C6			22
58#define PERIC_PCLK_HSI2C7			23
59#define PERIC_MCAN0_IPCLKPORT_CCLK		24
60#define PERIC_MCAN0_IPCLKPORT_PCLK		25
61#define PERIC_MCAN1_IPCLKPORT_CCLK		26
62#define PERIC_MCAN1_IPCLKPORT_PCLK		27
63#define PERIC_MCAN2_IPCLKPORT_CCLK		28
64#define PERIC_MCAN2_IPCLKPORT_PCLK		29
65#define PERIC_MCAN3_IPCLKPORT_CCLK		30
66#define PERIC_MCAN3_IPCLKPORT_PCLK		31
67#define PERIC_PCLK_ADCIF			32
68#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I  33
69#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I		34
70#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I		35
71#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I	36
72#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I	37
73#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK	38
74#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK	39
75#define PERIC_HCLK_TDM0				40
76#define PERIC_PCLK_TDM1				41
77#define PERIC_HCLK_TDM1				42
78#define PERIC_EQOS_PHYRXCLK_MUX			43
79#define PERIC_EQOS_PHYRXCLK			44
80#define PERIC_DOUT_RGMII_CLK			45
81#define PERIC_NR_CLK				46
82
83/* FSYS0 */
84#define UFS0_MPHY_REFCLK_IXTAL24		1
85#define UFS0_MPHY_REFCLK_IXTAL26		2
86#define UFS1_MPHY_REFCLK_IXTAL24		3
87#define UFS1_MPHY_REFCLK_IXTAL26		4
88#define UFS0_TOP0_HCLK_BUS			5
89#define UFS0_TOP0_ACLK				6
90#define UFS0_TOP0_CLK_UNIPRO			7
91#define UFS0_TOP0_FMP_CLK			8
92#define UFS1_TOP1_HCLK_BUS			9
93#define UFS1_TOP1_ACLK				10
94#define UFS1_TOP1_CLK_UNIPRO			11
95#define UFS1_TOP1_FMP_CLK			12
96#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC		13
97#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC		14
98#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC	15
99#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC		16
100#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
101#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I	18
102#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I	19
103#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I	20
104#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I	21
105#define FSYS0_DOUT_FSYS0_PERIBUS_GRP		22
106#define FSYS0_NR_CLK				23
107
108/* FSYS1 */
109#define PCIE_LINK0_IPCLKPORT_DBI_ACLK		1
110#define PCIE_LINK0_IPCLKPORT_AUX_ACLK		2
111#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK		3
112#define PCIE_LINK0_IPCLKPORT_SLV_ACLK		4
113#define PCIE_LINK1_IPCLKPORT_DBI_ACLK		5
114#define PCIE_LINK1_IPCLKPORT_AUX_ACLK		6
115#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK		7
116#define PCIE_LINK1_IPCLKPORT_SLV_ACLK		8
117#define FSYS1_NR_CLK				9
118
119/* IMEM */
120#define IMEM_DMA0_IPCLKPORT_ACLK		1
121#define IMEM_DMA1_IPCLKPORT_ACLK		2
122#define IMEM_WDT0_IPCLKPORT_PCLK		3
123#define IMEM_WDT1_IPCLKPORT_PCLK		4
124#define IMEM_WDT2_IPCLKPORT_PCLK		5
125#define IMEM_MCT_PCLK				6
126#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS	7
127#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS	8
128#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS		9
129#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS		10
130#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS		11
131#define IMEM_NR_CLK				12
132
133/* MFC */
134#define MFC_MFC_IPCLKPORT_ACLK			1
135#define MFC_NR_CLK				2
136
137/* CAM_CSI */
138#define CAM_CSI0_0_IPCLKPORT_I_ACLK		1
139#define CAM_CSI0_1_IPCLKPORT_I_ACLK		2
140#define CAM_CSI0_2_IPCLKPORT_I_ACLK		3
141#define CAM_CSI0_3_IPCLKPORT_I_ACLK		4
142#define CAM_CSI1_0_IPCLKPORT_I_ACLK		5
143#define CAM_CSI1_1_IPCLKPORT_I_ACLK		6
144#define CAM_CSI1_2_IPCLKPORT_I_ACLK		7
145#define CAM_CSI1_3_IPCLKPORT_I_ACLK		8
146#define CAM_CSI2_0_IPCLKPORT_I_ACLK		9
147#define CAM_CSI2_1_IPCLKPORT_I_ACLK		10
148#define CAM_CSI2_2_IPCLKPORT_I_ACLK		11
149#define CAM_CSI2_3_IPCLKPORT_I_ACLK		12
150#define CAM_CSI_NR_CLK				13
151
152#endif /*_DT_BINDINGS_CLOCK_FSD_H */
153