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      1 /*	$NetBSD: g12a-clkc.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
      4 /*
      5  * Meson-G12A clock tree IDs
      6  *
      7  * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
      8  */
      9 
     10 #ifndef __G12A_CLKC_H
     11 #define __G12A_CLKC_H
     12 
     13 #define CLKID_SYS_PLL				0
     14 #define CLKID_FIXED_PLL				1
     15 #define CLKID_FCLK_DIV2				2
     16 #define CLKID_FCLK_DIV3				3
     17 #define CLKID_FCLK_DIV4				4
     18 #define CLKID_FCLK_DIV5				5
     19 #define CLKID_FCLK_DIV7				6
     20 #define CLKID_GP0_PLL				7
     21 #define CLKID_CLK81				10
     22 #define CLKID_MPLL0				11
     23 #define CLKID_MPLL1				12
     24 #define CLKID_MPLL2				13
     25 #define CLKID_MPLL3				14
     26 #define CLKID_DDR				15
     27 #define CLKID_DOS				16
     28 #define CLKID_AUDIO_LOCKER			17
     29 #define CLKID_MIPI_DSI_HOST			18
     30 #define CLKID_ETH_PHY				19
     31 #define CLKID_ISA				20
     32 #define CLKID_PL301				21
     33 #define CLKID_PERIPHS				22
     34 #define CLKID_SPICC0				23
     35 #define CLKID_I2C				24
     36 #define CLKID_SANA				25
     37 #define CLKID_SD				26
     38 #define CLKID_RNG0				27
     39 #define CLKID_UART0				28
     40 #define CLKID_SPICC1				29
     41 #define CLKID_HIU_IFACE				30
     42 #define CLKID_MIPI_DSI_PHY			31
     43 #define CLKID_ASSIST_MISC			32
     44 #define CLKID_SD_EMMC_A				33
     45 #define CLKID_SD_EMMC_B				34
     46 #define CLKID_SD_EMMC_C				35
     47 #define CLKID_AUDIO_CODEC			36
     48 #define CLKID_AUDIO				37
     49 #define CLKID_ETH				38
     50 #define CLKID_DEMUX				39
     51 #define CLKID_AUDIO_IFIFO			40
     52 #define CLKID_ADC				41
     53 #define CLKID_UART1				42
     54 #define CLKID_G2D				43
     55 #define CLKID_RESET				44
     56 #define CLKID_PCIE_COMB				45
     57 #define CLKID_PARSER				46
     58 #define CLKID_USB				47
     59 #define CLKID_PCIE_PHY				48
     60 #define CLKID_AHB_ARB0				49
     61 #define CLKID_AHB_DATA_BUS			50
     62 #define CLKID_AHB_CTRL_BUS			51
     63 #define CLKID_HTX_HDCP22			52
     64 #define CLKID_HTX_PCLK				53
     65 #define CLKID_BT656				54
     66 #define CLKID_USB1_DDR_BRIDGE			55
     67 #define CLKID_MMC_PCLK				56
     68 #define CLKID_UART2				57
     69 #define CLKID_VPU_INTR				58
     70 #define CLKID_GIC				59
     71 #define CLKID_SD_EMMC_A_CLK0			60
     72 #define CLKID_SD_EMMC_B_CLK0			61
     73 #define CLKID_SD_EMMC_C_CLK0			62
     74 #define CLKID_HIFI_PLL				74
     75 #define CLKID_VCLK2_VENCI0			80
     76 #define CLKID_VCLK2_VENCI1			81
     77 #define CLKID_VCLK2_VENCP0			82
     78 #define CLKID_VCLK2_VENCP1			83
     79 #define CLKID_VCLK2_VENCT0			84
     80 #define CLKID_VCLK2_VENCT1			85
     81 #define CLKID_VCLK2_OTHER			86
     82 #define CLKID_VCLK2_ENCI			87
     83 #define CLKID_VCLK2_ENCP			88
     84 #define CLKID_DAC_CLK				89
     85 #define CLKID_AOCLK				90
     86 #define CLKID_IEC958				91
     87 #define CLKID_ENC480P				92
     88 #define CLKID_RNG1				93
     89 #define CLKID_VCLK2_ENCT			94
     90 #define CLKID_VCLK2_ENCL			95
     91 #define CLKID_VCLK2_VENCLMMC			96
     92 #define CLKID_VCLK2_VENCL			97
     93 #define CLKID_VCLK2_OTHER1			98
     94 #define CLKID_FCLK_DIV2P5			99
     95 #define CLKID_DMA				105
     96 #define CLKID_EFUSE				106
     97 #define CLKID_ROM_BOOT				107
     98 #define CLKID_RESET_SEC				108
     99 #define CLKID_SEC_AHB_APB3			109
    100 #define CLKID_VPU_0_SEL				110
    101 #define CLKID_VPU_0				112
    102 #define CLKID_VPU_1_SEL				113
    103 #define CLKID_VPU_1				115
    104 #define CLKID_VPU				116
    105 #define CLKID_VAPB_0_SEL			117
    106 #define CLKID_VAPB_0				119
    107 #define CLKID_VAPB_1_SEL			120
    108 #define CLKID_VAPB_1				122
    109 #define CLKID_VAPB_SEL				123
    110 #define CLKID_VAPB				124
    111 #define CLKID_HDMI_PLL				128
    112 #define CLKID_VID_PLL				129
    113 #define CLKID_VCLK				138
    114 #define CLKID_VCLK2				139
    115 #define CLKID_VCLK_DIV1				148
    116 #define CLKID_VCLK_DIV2				149
    117 #define CLKID_VCLK_DIV4				150
    118 #define CLKID_VCLK_DIV6				151
    119 #define CLKID_VCLK_DIV12			152
    120 #define CLKID_VCLK2_DIV1			153
    121 #define CLKID_VCLK2_DIV2			154
    122 #define CLKID_VCLK2_DIV4			155
    123 #define CLKID_VCLK2_DIV6			156
    124 #define CLKID_VCLK2_DIV12			157
    125 #define CLKID_CTS_ENCI				162
    126 #define CLKID_CTS_ENCP				163
    127 #define CLKID_CTS_VDAC				164
    128 #define CLKID_HDMI_TX				165
    129 #define CLKID_HDMI				168
    130 #define CLKID_MALI_0_SEL			169
    131 #define CLKID_MALI_0				171
    132 #define CLKID_MALI_1_SEL			172
    133 #define CLKID_MALI_1				174
    134 #define CLKID_MALI				175
    135 #define CLKID_MPLL_50M				177
    136 #define CLKID_CPU_CLK				187
    137 #define CLKID_PCIE_PLL				201
    138 #define CLKID_VDEC_1				204
    139 #define CLKID_VDEC_HEVC				207
    140 #define CLKID_VDEC_HEVCF			210
    141 #define CLKID_TS				212
    142 #define CLKID_CPUB_CLK				224
    143 #define CLKID_GP1_PLL				243
    144 #define CLKID_DSU_CLK				252
    145 #define CLKID_CPU1_CLK				253
    146 #define CLKID_CPU2_CLK				254
    147 #define CLKID_CPU3_CLK				255
    148 #define CLKID_SPICC0_SCLK			258
    149 #define CLKID_SPICC1_SCLK			261
    150 #define CLKID_NNA_AXI_CLK			264
    151 #define CLKID_NNA_CORE_CLK			267
    152 #define CLKID_MIPI_DSI_PXCLK_SEL		269
    153 #define CLKID_MIPI_DSI_PXCLK			270
    154 
    155 #endif /* __G12A_CLKC_H */
    156