1/*	$NetBSD: ingenic,jz4780-cgu.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
6 *
7 * They are roughly ordered as:
8 *   - external clocks
9 *   - PLLs
10 *   - muxes/dividers in the order they appear in the jz4780 programmers manual
11 *   - gates in order of their bit in the CLKGR* registers
12 */
13
14#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
15#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
16
17#define JZ4780_CLK_EXCLK		0
18#define JZ4780_CLK_RTCLK		1
19#define JZ4780_CLK_APLL			2
20#define JZ4780_CLK_MPLL			3
21#define JZ4780_CLK_EPLL			4
22#define JZ4780_CLK_VPLL			5
23#define JZ4780_CLK_OTGPHY		6
24#define JZ4780_CLK_SCLKA		7
25#define JZ4780_CLK_CPUMUX		8
26#define JZ4780_CLK_CPU			9
27#define JZ4780_CLK_L2CACHE		10
28#define JZ4780_CLK_AHB0			11
29#define JZ4780_CLK_AHB2PMUX		12
30#define JZ4780_CLK_AHB2			13
31#define JZ4780_CLK_PCLK			14
32#define JZ4780_CLK_DDR			15
33#define JZ4780_CLK_VPU			16
34#define JZ4780_CLK_I2SPLL		17
35#define JZ4780_CLK_I2S			18
36#define JZ4780_CLK_LCD0PIXCLK	19
37#define JZ4780_CLK_LCD1PIXCLK	20
38#define JZ4780_CLK_MSCMUX		21
39#define JZ4780_CLK_MSC0			22
40#define JZ4780_CLK_MSC1			23
41#define JZ4780_CLK_MSC2			24
42#define JZ4780_CLK_UHC			25
43#define JZ4780_CLK_SSIPLL		26
44#define JZ4780_CLK_SSI			27
45#define JZ4780_CLK_CIMMCLK		28
46#define JZ4780_CLK_PCMPLL		29
47#define JZ4780_CLK_PCM			30
48#define JZ4780_CLK_GPU			31
49#define JZ4780_CLK_HDMI			32
50#define JZ4780_CLK_BCH			33
51#define JZ4780_CLK_NEMC			34
52#define JZ4780_CLK_OTG0			35
53#define JZ4780_CLK_SSI0			36
54#define JZ4780_CLK_SMB0			37
55#define JZ4780_CLK_SMB1			38
56#define JZ4780_CLK_SCC			39
57#define JZ4780_CLK_AIC			40
58#define JZ4780_CLK_TSSI0		41
59#define JZ4780_CLK_OWI			42
60#define JZ4780_CLK_KBC			43
61#define JZ4780_CLK_SADC			44
62#define JZ4780_CLK_UART0		45
63#define JZ4780_CLK_UART1		46
64#define JZ4780_CLK_UART2		47
65#define JZ4780_CLK_UART3		48
66#define JZ4780_CLK_SSI1			49
67#define JZ4780_CLK_SSI2			50
68#define JZ4780_CLK_PDMA			51
69#define JZ4780_CLK_GPS			52
70#define JZ4780_CLK_MAC			53
71#define JZ4780_CLK_SMB2			54
72#define JZ4780_CLK_CIM			55
73#define JZ4780_CLK_LCD			56
74#define JZ4780_CLK_TVE			57
75#define JZ4780_CLK_IPU			58
76#define JZ4780_CLK_DDR0			59
77#define JZ4780_CLK_DDR1			60
78#define JZ4780_CLK_SMB3			61
79#define JZ4780_CLK_TSSI1		62
80#define JZ4780_CLK_COMPRESS		63
81#define JZ4780_CLK_AIC1			64
82#define JZ4780_CLK_GPVLC		65
83#define JZ4780_CLK_OTG1			66
84#define JZ4780_CLK_UART4		67
85#define JZ4780_CLK_AHBMON		68
86#define JZ4780_CLK_SMB4			69
87#define JZ4780_CLK_DES			70
88#define JZ4780_CLK_X2D			71
89#define JZ4780_CLK_CORE1		72
90#define JZ4780_CLK_EXCLK_DIV512	73
91#define JZ4780_CLK_RTC			74
92
93#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
94