1 /* $NetBSD: ingenic,x1000-cgu.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides clock numbers for the ingenic,x1000-cgu DT binding. 6 * 7 * They are roughly ordered as: 8 * - external clocks 9 * - PLLs 10 * - muxes/dividers in the order they appear in the x1000 programmers manual 11 * - gates in order of their bit in the CLKGR* registers 12 */ 13 14 #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ 15 #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ 16 17 #define X1000_CLK_EXCLK 0 18 #define X1000_CLK_RTCLK 1 19 #define X1000_CLK_APLL 2 20 #define X1000_CLK_MPLL 3 21 #define X1000_CLK_OTGPHY 4 22 #define X1000_CLK_SCLKA 5 23 #define X1000_CLK_CPUMUX 6 24 #define X1000_CLK_CPU 7 25 #define X1000_CLK_L2CACHE 8 26 #define X1000_CLK_AHB0 9 27 #define X1000_CLK_AHB2PMUX 10 28 #define X1000_CLK_AHB2 11 29 #define X1000_CLK_PCLK 12 30 #define X1000_CLK_DDR 13 31 #define X1000_CLK_MAC 14 32 #define X1000_CLK_LCD 15 33 #define X1000_CLK_MSCMUX 16 34 #define X1000_CLK_MSC0 17 35 #define X1000_CLK_MSC1 18 36 #define X1000_CLK_OTG 19 37 #define X1000_CLK_SSIPLL 20 38 #define X1000_CLK_SSIPLL_DIV2 21 39 #define X1000_CLK_SSIMUX 22 40 #define X1000_CLK_EMC 23 41 #define X1000_CLK_EFUSE 24 42 #define X1000_CLK_SFC 25 43 #define X1000_CLK_I2C0 26 44 #define X1000_CLK_I2C1 27 45 #define X1000_CLK_I2C2 28 46 #define X1000_CLK_UART0 29 47 #define X1000_CLK_UART1 30 48 #define X1000_CLK_UART2 31 49 #define X1000_CLK_TCU 32 50 #define X1000_CLK_SSI 33 51 #define X1000_CLK_OST 34 52 #define X1000_CLK_PDMA 35 53 #define X1000_CLK_EXCLK_DIV512 36 54 #define X1000_CLK_RTC 37 55 #define X1000_CLK_AIC 38 56 #define X1000_CLK_I2SPLLMUX 39 57 #define X1000_CLK_I2SPLL 40 58 #define X1000_CLK_I2S 41 59 60 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ 61
Indexes created Mon Apr 27 00:23:16 UTC 2026